/* opc12 i4 c4 rbase */ \
{NAME, 1, 0x368+OPC, 20, LD_STOR_INS_INC, {{i4,16}, {rbase,12}}}, \
/* opc12 i4 rbase disps12 */ \
{NAME, 2, 0x368+OPC, 20, LD_STOR_INS_INC, {{i4,16}, {rbase_dispu12,12}}}, \
/* opc4 i4 c4 rbase */ \
{NAME, 1, 0x364+OPC, 20, STOR_IMM_INS, {{i4,16}, {rbase,12}}}, \
/* opc12 i4 rbase disps12 */ \
{NAME, 2, 0x364+OPC, 20, STOR_IMM_INS, {{i4,16}, {rbase_dispu12,12}}}, \
/* opc12 i4 rbase disps28 */ \
{NAME, 3, 0x374+OPC, 20, STOR_IMM_INS, {{i4,16}, {rbase_dispu28,12}}}, \
/* opc12 i4 rbase ridx scl2 disps6 */ \
{NAME, 2, 0x36C+OPC, 20, STOR_IMM_INS, {{i4,16}, {rbase_ridx_scl2_dispu6,0}}},\
/* opc12 i4 rbase ridx scl2 disps22 */ \
{NAME, 3, 0x37C+OPC, 20, STOR_IMM_INS, {{i4,16}, {rbase_ridx_scl2_dispu22,0}}}
ST_REG_INST ("storb", 0x20, 0x4, DISPUB4),
ST_I_INST ("storb", 0x0),
ST_REG_INST ("storw", 0x21, 0x5, DISPUW4),
ST_I_INST ("storw", 0x1),
ST_REG_INST ("stord", 0x22, 0x6, DISPUD4),
ST_I_INST ("stord", 0x2),
/* Create a bit instruction. */
#define CSTBIT_INST(NAME, OP, OPC1, DIFF, SHIFT, OPC2) \
/* OP=i3 -->> opc13 i3 */ \
/* OP=i4 -->> opc12 i4 */ \
/* OP=i5 -->> opc11 i5 */ \
\
/* opcNN iN abs16 */ \
/* opcNN iN (Rindex)abs20 */ \
{NAME, 2, OPC3, 25, LD_STOR_INS, {{uimm4,20}, {rindex8_abs20,0}}}, \
/* opcNN iN (prp) disps14(RPbase) */ \
{NAME, 2, OPC4, 22, LD_STOR_INS, {{uimm4,4},{rpindex_disps14,0}}}, \
/* opcNN iN (rp) disps0(RPbase) */ \
{NAME, 1, OPC1+1, 24, LD_STOR_INS, {{uimm4,20}, {rpbase_disps0,16}}}, \
/* opcNN iN disps20(Rbase) */ \
{NAME, 3, OPC2, 12, LD_STOR_INS, {{uimm4,4}, {rbase_disps20,16}}}, \
/* opcNN iN (rp) disps16(RPBase) */ \
{NAME, 2, OPC1+2, 24, LD_STOR_INS, {{uimm4,20}, {rpbase_disps16,0}}}, \
/* opcNN iN (rp) disps20(RPBase) */ \
{NAME, 3, OPC2+1, 12, LD_STOR_INS, {{uimm4,4}, {rpbase_disps20,16}}}, \
/* opcNN iN rrp (Rindex)disps20(RPbase) */ \
{NAME, 3, OPC2+2, 12, LD_STOR_INS, {{uimm4,4}, {rpindex_disps20,16}}}
ST_REG_INST ("storb", 0x00134, 0xFE, 0xC8, 0x319, 0x65, rpbase_disps4, regr),
ST_IMM_INST ("storb", 0x81, 0x00120, 0x42, 0x218),
ST_REG_INST ("stord", 0x00138, 0xEE, 0xC7, 0x31A, 0x66, rpbase_dispe4, regp),
ST_REG_INST ("storw", 0x0013C, 0xDE, 0xC9, 0x31B, 0x67, rpbase_dispe4, regr),
ST_IMM_INST ("storw", 0xC1, 0x00130, 0x62, 0x318),
/* Create instruction with no operands. */
#define NO_OP_INST(NAME, OPC) \
/* opc16 */ \
{NAME, 1, OPC, 16, 0, {{0, 0}}}
NO_OP_INST ("cinv[i]", 0x000A),
NO_OP_INST ("cinv[i,u]", 0x000B),
NO_OP_INST ("cinv[d]", 0x000C),
NO_OP_INST ("cinv[d,u]", 0x000D),
NO_OP_INST ("cinv[d,i]", 0x000E),
