static void sun4i_tcon0_mode_set_common(struct sun4i_tcon *tcon, const struct drm_display_mode *mode) { /* Configure the dot clock */ clk_set_rate(tcon->dclk, mode->crtc_clock * 1000); /* Set the resolution */ regmap_write(tcon->regs, SUN4I_TCON0_BASIC0_REG, SUN4I_TCON0_BASIC0_X(mode->crtc_hdisplay) | SUN4I_TCON0_BASIC0_Y(mode->crtc_vdisplay)); }
void sun4i_tcon0_mode_set(struct sun4i_tcon *tcon, struct drm_display_mode *mode) { unsigned int bp, hsync, vsync; u8 clk_delay; u32 val = 0; /* Adjust clock delay */ clk_delay = sun4i_tcon_get_clk_delay(mode, 0); regmap_update_bits(tcon->regs, SUN4I_TCON0_CTL_REG, SUN4I_TCON0_CTL_CLK_DELAY_MASK, SUN4I_TCON0_CTL_CLK_DELAY(clk_delay)); /* Set the resolution */ regmap_write(tcon->regs, SUN4I_TCON0_BASIC0_REG, SUN4I_TCON0_BASIC0_X(mode->crtc_hdisplay) | SUN4I_TCON0_BASIC0_Y(mode->crtc_vdisplay)); /* * This is called a backporch in the register documentation, * but it really is the front porch + hsync */ bp = mode->crtc_htotal - mode->crtc_hsync_start; DRM_DEBUG_DRIVER("Setting horizontal total %d, backporch %d\n", mode->crtc_htotal, bp); /* Set horizontal display timings */ regmap_write(tcon->regs, SUN4I_TCON0_BASIC1_REG, SUN4I_TCON0_BASIC1_H_TOTAL(mode->crtc_htotal) | SUN4I_TCON0_BASIC1_H_BACKPORCH(bp)); /* * This is called a backporch in the register documentation, * but it really is the front porch + hsync */ bp = mode->crtc_vtotal - mode->crtc_vsync_start; DRM_DEBUG_DRIVER("Setting vertical total %d, backporch %d\n", mode->crtc_vtotal, bp); /* Set vertical display timings */ regmap_write(tcon->regs, SUN4I_TCON0_BASIC2_REG, SUN4I_TCON0_BASIC2_V_TOTAL(mode->crtc_vtotal) | SUN4I_TCON0_BASIC2_V_BACKPORCH(bp)); /* Set Hsync and Vsync length */ hsync = mode->crtc_hsync_end - mode->crtc_hsync_start; vsync = mode->crtc_vsync_end - mode->crtc_vsync_start; DRM_DEBUG_DRIVER("Setting HSYNC %d, VSYNC %d\n", hsync, vsync); regmap_write(tcon->regs, SUN4I_TCON0_BASIC3_REG, SUN4I_TCON0_BASIC3_V_SYNC(vsync) | SUN4I_TCON0_BASIC3_H_SYNC(hsync)); /* Setup the polarity of the various signals */ if (!(mode->flags & DRM_MODE_FLAG_PHSYNC)) val |= SUN4I_TCON0_IO_POL_HSYNC_POSITIVE; if (!(mode->flags & DRM_MODE_FLAG_PVSYNC)) val |= SUN4I_TCON0_IO_POL_VSYNC_POSITIVE; regmap_update_bits(tcon->regs, SUN4I_TCON0_IO_POL_REG, SUN4I_TCON0_IO_POL_HSYNC_POSITIVE | SUN4I_TCON0_IO_POL_VSYNC_POSITIVE, val); /* Map output pins to channel 0 */ regmap_update_bits(tcon->regs, SUN4I_TCON_GCTL_REG, SUN4I_TCON_GCTL_IOMAP_MASK, SUN4I_TCON_GCTL_IOMAP_TCON0); /* Enable the output on the pins */ regmap_write(tcon->regs, SUN4I_TCON0_IO_TRI_REG, 0); }