static void sunxi_hdmi_mode_set(const struct ctfb_res_modes *mode, int clk_div, int clk_double) { struct sunxi_hdmi_reg * const hdmi = (struct sunxi_hdmi_reg *)SUNXI_HDMI_BASE; int x, y; /* Write clear interrupt status bits */ writel(SUNXI_HDMI_IRQ_STATUS_BITS, &hdmi->irq); if (sunxi_display.monitor == sunxi_monitor_hdmi) sunxi_hdmi_setup_info_frames(mode); /* Set input sync enable */ writel(SUNXI_HDMI_UNKNOWN_INPUT_SYNC, &hdmi->unknown); /* Init various registers, select pll3 as clock source */ writel(SUNXI_HDMI_VIDEO_POL_TX_CLK, &hdmi->video_polarity); writel(SUNXI_HDMI_PAD_CTRL0_RUN, &hdmi->pad_ctrl0); writel(SUNXI_HDMI_PAD_CTRL1, &hdmi->pad_ctrl1); writel(SUNXI_HDMI_PLL_CTRL, &hdmi->pll_ctrl); writel(SUNXI_HDMI_PLL_DBG0_PLL3, &hdmi->pll_dbg0); /* Setup clk div and doubler */ clrsetbits_le32(&hdmi->pll_ctrl, SUNXI_HDMI_PLL_CTRL_DIV_MASK, SUNXI_HDMI_PLL_CTRL_DIV(clk_div)); if (!clk_double) setbits_le32(&hdmi->pad_ctrl1, SUNXI_HDMI_PAD_CTRL1_HALVE); /* Setup timing registers */ writel(SUNXI_HDMI_Y(mode->yres) | SUNXI_HDMI_X(mode->xres), &hdmi->video_size); x = mode->hsync_len + mode->left_margin; y = mode->vsync_len + mode->upper_margin; writel(SUNXI_HDMI_Y(y) | SUNXI_HDMI_X(x), &hdmi->video_bp); x = mode->right_margin; y = mode->lower_margin; writel(SUNXI_HDMI_Y(y) | SUNXI_HDMI_X(x), &hdmi->video_fp); x = mode->hsync_len; y = mode->vsync_len; writel(SUNXI_HDMI_Y(y) | SUNXI_HDMI_X(x), &hdmi->video_spw); if (mode->sync & FB_SYNC_HOR_HIGH_ACT) setbits_le32(&hdmi->video_polarity, SUNXI_HDMI_VIDEO_POL_HOR); if (mode->sync & FB_SYNC_VERT_HIGH_ACT) setbits_le32(&hdmi->video_polarity, SUNXI_HDMI_VIDEO_POL_VER); }
static void sunxi_lcdc_tcon0_mode_set(const struct ctfb_res_modes *mode, bool for_ext_vga_dac) { struct sunxi_lcdc_reg * const lcdc = (struct sunxi_lcdc_reg *)SUNXI_LCD0_BASE; struct sunxi_ccm_reg * const ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; int clk_div, clk_double, pin; struct display_timing timing; #if defined CONFIG_MACH_SUN8I && defined CONFIG_VIDEO_LCD_IF_LVDS for (pin = SUNXI_GPD(18); pin <= SUNXI_GPD(27); pin++) { #else for (pin = SUNXI_GPD(0); pin <= SUNXI_GPD(27); pin++) { #endif #ifdef CONFIG_VIDEO_LCD_IF_PARALLEL sunxi_gpio_set_cfgpin(pin, SUNXI_GPD_LCD0); #endif #ifdef CONFIG_VIDEO_LCD_IF_LVDS sunxi_gpio_set_cfgpin(pin, SUNXI_GPD_LVDS0); #endif #ifdef CONFIG_VIDEO_LCD_PANEL_EDP_4_LANE_1620M_VIA_ANX9804 sunxi_gpio_set_drv(pin, 3); #endif } lcdc_pll_set(ccm, 0, mode->pixclock_khz, &clk_div, &clk_double, sunxi_is_composite()); sunxi_ctfb_mode_to_display_timing(mode, &timing); lcdc_tcon0_mode_set(lcdc, &timing, clk_div, for_ext_vga_dac, sunxi_display.depth, CONFIG_VIDEO_LCD_DCLK_PHASE); } #if defined CONFIG_VIDEO_HDMI || defined CONFIG_VIDEO_VGA || defined CONFIG_VIDEO_COMPOSITE static void sunxi_lcdc_tcon1_mode_set(const struct ctfb_res_modes *mode, int *clk_div, int *clk_double, bool use_portd_hvsync) { struct sunxi_lcdc_reg * const lcdc = (struct sunxi_lcdc_reg *)SUNXI_LCD0_BASE; struct sunxi_ccm_reg * const ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; struct display_timing timing; sunxi_ctfb_mode_to_display_timing(mode, &timing); lcdc_tcon1_mode_set(lcdc, &timing, use_portd_hvsync, sunxi_is_composite()); if (use_portd_hvsync) { sunxi_gpio_set_cfgpin(SUNXI_GPD(26), SUNXI_GPD_LCD0); sunxi_gpio_set_cfgpin(SUNXI_GPD(27), SUNXI_GPD_LCD0); } lcdc_pll_set(ccm, 1, mode->pixclock_khz, clk_div, clk_double, sunxi_is_composite()); } #endif /* CONFIG_VIDEO_HDMI || defined CONFIG_VIDEO_VGA || CONFIG_VIDEO_COMPOSITE */ #ifdef CONFIG_VIDEO_HDMI static void sunxi_hdmi_setup_info_frames(const struct ctfb_res_modes *mode) { struct sunxi_hdmi_reg * const hdmi = (struct sunxi_hdmi_reg *)SUNXI_HDMI_BASE; u8 checksum = 0; u8 avi_info_frame[17] = { 0x82, 0x02, 0x0d, 0x00, 0x12, 0x00, 0x88, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }; u8 vendor_info_frame[19] = { 0x81, 0x01, 0x06, 0x29, 0x03, 0x0c, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }; int i; if (mode->pixclock_khz <= 27000) avi_info_frame[5] = 0x40; /* SD-modes, ITU601 colorspace */ else avi_info_frame[5] = 0x80; /* HD-modes, ITU709 colorspace */ if (mode->xres * 100 / mode->yres < 156) avi_info_frame[5] |= 0x18; /* 4 : 3 */ else avi_info_frame[5] |= 0x28; /* 16 : 9 */ for (i = 0; i < ARRAY_SIZE(avi_info_frame); i++) checksum += avi_info_frame[i]; avi_info_frame[3] = 0x100 - checksum; for (i = 0; i < ARRAY_SIZE(avi_info_frame); i++) writeb(avi_info_frame[i], &hdmi->avi_info_frame[i]); writel(SUNXI_HDMI_QCP_PACKET0, &hdmi->qcp_packet0); writel(SUNXI_HDMI_QCP_PACKET1, &hdmi->qcp_packet1); for (i = 0; i < ARRAY_SIZE(vendor_info_frame); i++) writeb(vendor_info_frame[i], &hdmi->vendor_info_frame[i]); writel(SUNXI_HDMI_PKT_CTRL0, &hdmi->pkt_ctrl0); writel(SUNXI_HDMI_PKT_CTRL1, &hdmi->pkt_ctrl1); setbits_le32(&hdmi->video_ctrl, SUNXI_HDMI_VIDEO_CTRL_HDMI); } static void sunxi_hdmi_mode_set(const struct ctfb_res_modes *mode, int clk_div, int clk_double) { struct sunxi_hdmi_reg * const hdmi = (struct sunxi_hdmi_reg *)SUNXI_HDMI_BASE; int x, y; /* Write clear interrupt status bits */ writel(SUNXI_HDMI_IRQ_STATUS_BITS, &hdmi->irq); if (sunxi_display.monitor == sunxi_monitor_hdmi) sunxi_hdmi_setup_info_frames(mode); /* Set input sync enable */ writel(SUNXI_HDMI_UNKNOWN_INPUT_SYNC, &hdmi->unknown); /* Init various registers, select pll3 as clock source */ writel(SUNXI_HDMI_VIDEO_POL_TX_CLK, &hdmi->video_polarity); writel(SUNXI_HDMI_PAD_CTRL0_RUN, &hdmi->pad_ctrl0); writel(SUNXI_HDMI_PAD_CTRL1, &hdmi->pad_ctrl1); writel(SUNXI_HDMI_PLL_CTRL, &hdmi->pll_ctrl); writel(SUNXI_HDMI_PLL_DBG0_PLL3, &hdmi->pll_dbg0); /* Setup clk div and doubler */ clrsetbits_le32(&hdmi->pll_ctrl, SUNXI_HDMI_PLL_CTRL_DIV_MASK, SUNXI_HDMI_PLL_CTRL_DIV(clk_div)); if (!clk_double) setbits_le32(&hdmi->pad_ctrl1, SUNXI_HDMI_PAD_CTRL1_HALVE); /* Setup timing registers */ writel(SUNXI_HDMI_Y(mode->yres) | SUNXI_HDMI_X(mode->xres), &hdmi->video_size); x = mode->hsync_len + mode->left_margin; y = mode->vsync_len + mode->upper_margin; writel(SUNXI_HDMI_Y(y) | SUNXI_HDMI_X(x), &hdmi->video_bp); x = mode->right_margin; y = mode->lower_margin; writel(SUNXI_HDMI_Y(y) | SUNXI_HDMI_X(x), &hdmi->video_fp); x = mode->hsync_len; y = mode->vsync_len; writel(SUNXI_HDMI_Y(y) | SUNXI_HDMI_X(x), &hdmi->video_spw); if (mode->sync & FB_SYNC_HOR_HIGH_ACT) setbits_le32(&hdmi->video_polarity, SUNXI_HDMI_VIDEO_POL_HOR); if (mode->sync & FB_SYNC_VERT_HIGH_ACT) setbits_le32(&hdmi->video_polarity, SUNXI_HDMI_VIDEO_POL_VER); } static void sunxi_hdmi_enable(void) { struct sunxi_hdmi_reg * const hdmi = (struct sunxi_hdmi_reg *)SUNXI_HDMI_BASE; udelay(100); setbits_le32(&hdmi->video_ctrl, SUNXI_HDMI_VIDEO_CTRL_ENABLE); } #endif /* CONFIG_VIDEO_HDMI */ #if defined CONFIG_VIDEO_VGA || defined CONFIG_VIDEO_COMPOSITE static void sunxi_tvencoder_mode_set(void) { struct sunxi_ccm_reg * const ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; struct sunxi_tve_reg * const tve = (struct sunxi_tve_reg *)SUNXI_TVE0_BASE; /* Reset off */ setbits_le32(&ccm->lcd0_ch0_clk_cfg, CCM_LCD_CH0_CTRL_TVE_RST); /* Clock on */ setbits_le32(&ccm->ahb_gate1, 1 << AHB_GATE_OFFSET_TVE0); switch (sunxi_display.monitor) { case sunxi_monitor_vga: tvencoder_mode_set(tve, tve_mode_vga); break; case sunxi_monitor_composite_pal_nc: tvencoder_mode_set(tve, tve_mode_composite_pal_nc); break; case sunxi_monitor_composite_pal: tvencoder_mode_set(tve, tve_mode_composite_pal); break; case sunxi_monitor_composite_pal_m: tvencoder_mode_set(tve, tve_mode_composite_pal_m); break; case sunxi_monitor_composite_ntsc: tvencoder_mode_set(tve, tve_mode_composite_ntsc); break; case sunxi_monitor_none: case sunxi_monitor_dvi: case sunxi_monitor_hdmi: case sunxi_monitor_lcd: break; } } #endif /* CONFIG_VIDEO_VGA || defined CONFIG_VIDEO_COMPOSITE */ static void sunxi_drc_init(void) { #ifdef CONFIG_SUNXI_GEN_SUN6I struct sunxi_ccm_reg * const ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; /* On sun6i the drc must be clocked even when in pass-through mode */ #ifdef CONFIG_MACH_SUN8I_A33 setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_SAT); #endif setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_DRC0); clock_set_de_mod_clock(&ccm->iep_drc0_clk_cfg, 300000000); #endif } #ifdef CONFIG_VIDEO_VGA_VIA_LCD static void sunxi_vga_external_dac_enable(void) { int pin; pin = sunxi_name_to_gpio(CONFIG_VIDEO_VGA_EXTERNAL_DAC_EN); if (pin >= 0) { gpio_request(pin, "vga_enable"); gpio_direction_output(pin, 1); } }
static int sunxi_hdmi_edid_get_mode(struct ctfb_res_modes *mode) { struct edid1_info edid1; struct edid_cea861_info cea681[4]; struct edid_detailed_timing *t = (struct edid_detailed_timing *)edid1.monitor_details.timing; struct sunxi_hdmi_reg * const hdmi = (struct sunxi_hdmi_reg *)SUNXI_HDMI_BASE; struct sunxi_ccm_reg * const ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; int i, r, ext_blocks = 0; /* SUNXI_HDMI_CTRL_ENABLE & PAD_CTRL0 are already set by hpd_detect */ writel(SUNXI_HDMI_PAD_CTRL1 | SUNXI_HDMI_PAD_CTRL1_HALVE, &hdmi->pad_ctrl1); writel(SUNXI_HDMI_PLL_CTRL | SUNXI_HDMI_PLL_CTRL_DIV(15), &hdmi->pll_ctrl); writel(SUNXI_HDMI_PLL_DBG0_PLL3, &hdmi->pll_dbg0); /* Reset i2c controller */ setbits_le32(&ccm->hdmi_clk_cfg, CCM_HDMI_CTRL_DDC_GATE); writel(SUNXI_HMDI_DDC_CTRL_ENABLE | SUNXI_HMDI_DDC_CTRL_SDA_ENABLE | SUNXI_HMDI_DDC_CTRL_SCL_ENABLE | SUNXI_HMDI_DDC_CTRL_RESET, &hdmi->ddc_ctrl); if (await_completion(&hdmi->ddc_ctrl, SUNXI_HMDI_DDC_CTRL_RESET, 0)) return -EIO; writel(SUNXI_HDMI_DDC_CLOCK, &hdmi->ddc_clock); #ifndef CONFIG_MACH_SUN6I writel(SUNXI_HMDI_DDC_LINE_CTRL_SDA_ENABLE | SUNXI_HMDI_DDC_LINE_CTRL_SCL_ENABLE, &hdmi->ddc_line_ctrl); #endif r = sunxi_hdmi_edid_get_block(0, (u8 *)&edid1); if (r == 0) { r = edid_check_info(&edid1); if (r) { printf("EDID: invalid EDID data\n"); r = -EINVAL; } } if (r == 0) { ext_blocks = edid1.extension_flag; if (ext_blocks > 4) ext_blocks = 4; for (i = 0; i < ext_blocks; i++) { if (sunxi_hdmi_edid_get_block(1 + i, (u8 *)&cea681[i]) != 0) { ext_blocks = i; break; } } } /* Disable DDC engine, no longer needed */ clrbits_le32(&hdmi->ddc_ctrl, SUNXI_HMDI_DDC_CTRL_ENABLE); clrbits_le32(&ccm->hdmi_clk_cfg, CCM_HDMI_CTRL_DDC_GATE); if (r) return r; /* We want version 1.3 or 1.2 with detailed timing info */ if (edid1.version != 1 || (edid1.revision < 3 && !EDID1_INFO_FEATURE_PREFERRED_TIMING_MODE(edid1))) { printf("EDID: unsupported version %d.%d\n", edid1.version, edid1.revision); return -EINVAL; } /* Take the first usable detailed timing */ for (i = 0; i < 4; i++, t++) { r = video_edid_dtd_to_ctfb_res_modes(t, mode); if (r == 0) break; } if (i == 4) { printf("EDID: no usable detailed timing found\n"); return -ENOENT; } /* Check for basic audio support, if found enable hdmi output */ sunxi_display.monitor = sunxi_monitor_dvi; for (i = 0; i < ext_blocks; i++) { if (cea681[i].extension_tag != EDID_CEA861_EXTENSION_TAG || cea681[i].revision < 2) continue; if (EDID_CEA861_SUPPORTS_BASIC_AUDIO(cea681[i])) sunxi_display.monitor = sunxi_monitor_hdmi; } return 0; }