int checkcpu(void) { sys_info_t sysinfo; uint pvr, svr; uint ver; uint major, minor; uint lcrr; /* local bus clock ratio register */ uint clkdiv; /* clock divider portion of lcrr */ puts("Freescale PowerPC\n"); pvr = get_pvr(); ver = PVR_VER(pvr); major = PVR_MAJ(pvr); minor = PVR_MIN(pvr); puts("CPU:\n"); puts(" Core: "); switch (ver) { case PVR_VER(PVR_86xx): puts("E600"); break; default: puts("Unknown"); break; } printf(", Version: %d.%d, (0x%08x)\n", major, minor, pvr); svr = get_svr(); ver = SVR_VER(svr); major = SVR_MAJ(svr); minor = SVR_MIN(svr); puts(" System: "); switch (ver) { case SVR_8641: if (SVR_SUBVER(svr) == 1) { puts("8641D"); } else { puts("8641"); } break; default: puts("Unknown"); break; } printf(", Version: %d.%d, (0x%08x)\n", major, minor, svr); get_sys_info(&sysinfo); puts(" Clocks: "); printf("CPU:%4lu MHz, ", sysinfo.freqProcessor / 1000000); printf("MPX:%4lu MHz, ", sysinfo.freqSystemBus / 1000000); printf("DDR:%4lu MHz, ", sysinfo.freqSystemBus / 2000000); #if defined(CFG_LBC_LCRR) lcrr = CFG_LBC_LCRR; #else { volatile immap_t *immap = (immap_t *) CFG_IMMR; volatile ccsr_lbc_t *lbc = &immap->im_lbc; lcrr = lbc->lcrr; } #endif clkdiv = lcrr & 0x0f; if (clkdiv == 2 || clkdiv == 4 || clkdiv == 8) { printf("LBC:%4lu MHz\n", sysinfo.freqSystemBus / 1000000 / clkdiv); } else { printf(" LBC: unknown (lcrr: 0x%08x)\n", lcrr); } puts(" L2: "); if (get_l2cr() & 0x80000000) puts("Enabled\n"); else puts("Disabled\n"); return 0; }
int checkcpu(void) { sys_info_t sysinfo; uint pvr, svr; uint ver; uint major, minor; uint lcrr; /* local bus clock ratio register */ uint clkdiv; /* clock divider portion of lcrr */ volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; volatile ccsr_gur_t *gur = &immap->im_gur; puts("Freescale PowerPC\n"); pvr = get_pvr(); ver = PVR_VER(pvr); major = PVR_MAJ(pvr); minor = PVR_MIN(pvr); puts("CPU:\n"); puts(" Core: "); switch (ver) { case PVR_VER(PVR_86xx): { uint msscr0 = mfspr(MSSCR0); printf("E600 Core %d", (msscr0 & 0x20) ? 1 : 0 ); if (gur->pordevsr & MPC86xx_PORDEVSR_CORE1TE) puts("\n Core1Translation Enabled"); debug(" (MSSCR0=%x, PORDEVSR=%x)", msscr0, gur->pordevsr); } break; default: puts("Unknown"); break; } printf(", Version: %d.%d, (0x%08x)\n", major, minor, pvr); svr = get_svr(); ver = SVR_SOC_VER(svr); major = SVR_MAJ(svr); minor = SVR_MIN(svr); puts(" System: "); switch (ver) { case SVR_8641: if (SVR_SUBVER(svr) == 1) { puts("8641D"); } else { puts("8641"); } break; case SVR_8610: puts("8610"); break; default: puts("Unknown"); break; } printf(", Version: %d.%d, (0x%08x)\n", major, minor, svr); get_sys_info(&sysinfo); puts(" Clocks: "); printf("CPU:%4lu MHz, ", sysinfo.freqProcessor / 1000000); printf("MPX:%4lu MHz, ", sysinfo.freqSystemBus / 1000000); printf("DDR:%4lu MHz, ", sysinfo.freqSystemBus / 2000000); #if defined(CONFIG_SYS_LBC_LCRR) lcrr = CONFIG_SYS_LBC_LCRR; #else { volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; volatile ccsr_lbc_t *lbc = &immap->im_lbc; lcrr = lbc->lcrr; } #endif clkdiv = lcrr & 0x0f; if (clkdiv == 2 || clkdiv == 4 || clkdiv == 8) { printf("LBC:%4lu MHz\n", sysinfo.freqSystemBus / 1000000 / clkdiv); } else { printf(" LBC: unknown (lcrr: 0x%08x)\n", lcrr); } puts(" L2: "); if (get_l2cr() & 0x80000000) puts("Enabled\n"); else puts("Disabled\n"); return 0; }