void SX1272FskSetFdev( uint32_t fdev )
{
FskSettings.Fdev = fdev;
fdev = ( uint16_t )( ( double )fdev / ( double )FREQ_STEP );
SX1272->RegFdevMsb = ( uint8_t )( fdev >> 8 );
SX1272->RegFdevLsb = ( uint8_t )( fdev & 0xFF );
SX1272WriteBuffer( REG_FDEVMSB, &SX1272->RegFdevMsb, 2 );
}
void SX1272FskSetBitrate( uint32_t bitrate )
{
FskSettings.Bitrate = bitrate;
bitrate = ( uint16_t )( ( double )XTAL_FREQ / ( double )bitrate );
SX1272->RegBitrateMsb = ( uint8_t )( bitrate >> 8 );
SX1272->RegBitrateLsb = ( uint8_t )( bitrate & 0xFF );
SX1272WriteBuffer( REG_BITRATEMSB, &SX1272->RegBitrateMsb, 2 );
}
void SX1272FskSetRFFrequency( uint32_t freq )
{
FskSettings.RFFrequency = freq;
freq = ( uint32_t )( ( double )freq / ( double )FREQ_STEP );
SX1272->RegFrfMsb = ( uint8_t )( ( freq >> 16 ) & 0xFF );
SX1272->RegFrfMid = ( uint8_t )( ( freq >> 8 ) & 0xFF );
SX1272->RegFrfLsb = ( uint8_t )( freq & 0xFF );
SX1272WriteBuffer( REG_FRFMSB, &SX1272->RegFrfMsb, 3 );
}
void SX1272LoRaInit( void )
{
RFLRState = RFLR_STATE_IDLE;
SX1272LoRaSetDefaults( );
SX1272ReadBuffer( REG_LR_OPMODE, SX1272Regs + 1, 0x70 - 1 );
#if ( PLATFORM == SX12xxEiger )
SX1272LR->RegPaConfig = ( SX1272LR->RegPaConfig & RFLR_PACONFIG_PASELECT_PABOOST ) |
RFLR_PACONFIG_PASELECT_PABOOST;
#else
SX1272LR->RegPaConfig = ( SX1272LR->RegPaConfig & RFLR_PACONFIG_PASELECT_PABOOST ) |
RFLR_PACONFIG_PASELECT_RFO;
#endif
SX1272LR->RegLna = RFLR_LNA_GAIN_G1 | RFLR_LNA_BOOST_ON;
SX1272WriteBuffer( REG_LR_OPMODE, SX1272Regs + 1, 0x70 - 1 );
// set the RF settings
SX1272LoRaSetRFFrequency( LoRaSettings.RFFrequency );
#if ( PLATFORM == SX12xxEiger )
SX1272LoRaSetPa20dBm( true );
#else
SX1272LoRaSetPa20dBm( false );
#endif
SX1272LoRaSetRFPower( LoRaSettings.Power );
SX1272LoRaSetSpreadingFactor( LoRaSettings.SpreadingFactor ); // SF6 only operates in implicit header mode.
SX1272LoRaSetErrorCoding( LoRaSettings.ErrorCoding );
SX1272LoRaSetPacketCrcOn( LoRaSettings.CrcOn );
SX1272LoRaSetSignalBandwidth( LoRaSettings.SignalBw );
SX1272LoRaSetImplicitHeaderOn( LoRaSettings.ImplicitHeaderOn );
SX1272LoRaSetSymbTimeout( 0x3FF );
SX1272LoRaSetPayloadLength( LoRaSettings.PayloadLength );
SX1272LoRaSetLowDatarateOptimize( true );
SX1272LoRaSetOpMode( RFLR_OPMODE_STANDBY );
}
void SX1272SetLoRaOn( bool enable )
{
if( LoRaOnState == enable )
{
return;
}
LoRaOnState = enable;
LoRaOn = enable;
if( LoRaOn == true )
{
SX1272LoRaSetOpMode( RFLR_OPMODE_SLEEP );
SX1272LR->RegOpMode = ( SX1272LR->RegOpMode & RFLR_OPMODE_LONGRANGEMODE_MASK ) | RFLR_OPMODE_LONGRANGEMODE_ON;
SX1272Write( REG_LR_OPMODE, SX1272LR->RegOpMode );
SX1272LoRaSetOpMode( RFLR_OPMODE_STANDBY );
// RxDone RxTimeout FhssChangeChannel CadDone
SX1272LR->RegDioMapping1 = RFLR_DIOMAPPING1_DIO0_00 | RFLR_DIOMAPPING1_DIO1_00 | RFLR_DIOMAPPING1_DIO2_00 | RFLR_DIOMAPPING1_DIO3_00;
// CadDetected ModeReady
SX1272LR->RegDioMapping2 = RFLR_DIOMAPPING2_DIO4_00 | RFLR_DIOMAPPING2_DIO5_00;
SX1272WriteBuffer( REG_LR_DIOMAPPING1, &SX1272LR->RegDioMapping1, 2 );
SX1272ReadBuffer( REG_LR_OPMODE, SX1272Regs + 1, 0x70 - 1 );
}
else
{
SX1272LoRaSetOpMode( RFLR_OPMODE_SLEEP );
SX1272LR->RegOpMode = ( SX1272LR->RegOpMode & RFLR_OPMODE_LONGRANGEMODE_MASK ) | RFLR_OPMODE_LONGRANGEMODE_OFF;
SX1272Write( REG_LR_OPMODE, SX1272LR->RegOpMode );
SX1272LoRaSetOpMode( RFLR_OPMODE_STANDBY );
SX1272ReadBuffer( REG_OPMODE, SX1272Regs + 1, 0x70 - 1 );
}
}
void SX1272WriteFifo( uint8_t *buffer, uint8_t size )
{
SX1272WriteBuffer( 0, buffer, size );
}
void SX1272Write( uint8_t addr, uint8_t data )
{
SX1272WriteBuffer( addr, &data, 1 );
}
/*!
* \brief Process the LoRa modem Rx and Tx state machines depending on the
* SX1272 operating mode.
*
* \retval rfState Current RF state [RF_IDLE, RF_BUSY,
* RF_RX_DONE, RF_RX_TIMEOUT,
* RF_TX_DONE, RF_TX_TIMEOUT]
*/
uint32_t SX1272LoRaProcess( void )
{
uint32_t result = RF_BUSY;
switch( RFLRState )
{
case RFLR_STATE_IDLE:
break;
case RFLR_STATE_RX_INIT:
SX1272LoRaSetOpMode( RFLR_OPMODE_STANDBY );
SX1272LR->RegIrqFlagsMask = RFLR_IRQFLAGS_RXTIMEOUT |
//RFLR_IRQFLAGS_RXDONE |
//RFLR_IRQFLAGS_PAYLOADCRCERROR |
RFLR_IRQFLAGS_VALIDHEADER |
RFLR_IRQFLAGS_TXDONE |
RFLR_IRQFLAGS_CADDONE |
//RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL |
RFLR_IRQFLAGS_CADDETECTED;
SX1272Write( REG_LR_IRQFLAGSMASK, SX1272LR->RegIrqFlagsMask );
if( LoRaSettings.FreqHopOn == true )
{
SX1272LR->RegHopPeriod = LoRaSettings.HopPeriod;
SX1272Read( REG_LR_HOPCHANNEL, &SX1272LR->RegHopChannel );
SX1272LoRaSetRFFrequency( HoppingFrequencies[SX1272LR->RegHopChannel & RFLR_HOPCHANNEL_CHANNEL_MASK] );
}
else
{
SX1272LR->RegHopPeriod = 255;
}
SX1272Write( REG_LR_HOPPERIOD, SX1272LR->RegHopPeriod );
// RxDone RxTimeout FhssChangeChannel CadDone
SX1272LR->RegDioMapping1 = RFLR_DIOMAPPING1_DIO0_00 | RFLR_DIOMAPPING1_DIO1_00 | RFLR_DIOMAPPING1_DIO2_00 | RFLR_DIOMAPPING1_DIO3_00;
// CadDetected ModeReady
SX1272LR->RegDioMapping2 = RFLR_DIOMAPPING2_DIO4_00 | RFLR_DIOMAPPING2_DIO5_00;
SX1272WriteBuffer( REG_LR_DIOMAPPING1, &SX1272LR->RegDioMapping1, 2 );
if( LoRaSettings.RxSingleOn == true ) // Rx single mode
{
SX1272LoRaSetOpMode( RFLR_OPMODE_RECEIVER_SINGLE );
}
else // Rx continuous mode
{
SX1272LR->RegFifoAddrPtr = SX1272LR->RegFifoRxBaseAddr;
SX1272Write( REG_LR_FIFOADDRPTR, SX1272LR->RegFifoAddrPtr );
SX1272LoRaSetOpMode( RFLR_OPMODE_RECEIVER );
}
memset( RFBuffer, 0, ( size_t )RF_BUFFER_SIZE );
PacketTimeout = LoRaSettings.RxPacketTimeout;
RxTimeoutTimer = GET_TICK_COUNT( );
RFLRState = RFLR_STATE_RX_RUNNING;
break;
case RFLR_STATE_RX_RUNNING:
if( DIO0 == 1 ) // RxDone
{
RxTimeoutTimer = GET_TICK_COUNT( );
if( LoRaSettings.FreqHopOn == true )
{
SX1272Read( REG_LR_HOPCHANNEL, &SX1272LR->RegHopChannel );
SX1272LoRaSetRFFrequency( HoppingFrequencies[SX1272LR->RegHopChannel & RFLR_HOPCHANNEL_CHANNEL_MASK] );
}
// Clear Irq
SX1272Write( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_RXDONE );
RFLRState = RFLR_STATE_RX_DONE;
}
if( DIO2 == 1 ) // FHSS Changed Channel
{
RxTimeoutTimer = GET_TICK_COUNT( );
if( LoRaSettings.FreqHopOn == true )
{
SX1272Read( REG_LR_HOPCHANNEL, &SX1272LR->RegHopChannel );
SX1272LoRaSetRFFrequency( HoppingFrequencies[SX1272LR->RegHopChannel & RFLR_HOPCHANNEL_CHANNEL_MASK] );
}
// Clear Irq
SX1272Write( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL );
// Debug
RxGain = SX1272LoRaReadRxGain( );
}
if( LoRaSettings.RxSingleOn == true ) // Rx single mode
{
if( ( GET_TICK_COUNT( ) - RxTimeoutTimer ) > PacketTimeout )
{
RFLRState = RFLR_STATE_RX_TIMEOUT;
}
}
break;
case RFLR_STATE_RX_DONE:
SX1272Read( REG_LR_IRQFLAGS, &SX1272LR->RegIrqFlags );
if( ( SX1272LR->RegIrqFlags & RFLR_IRQFLAGS_PAYLOADCRCERROR ) == RFLR_IRQFLAGS_PAYLOADCRCERROR )
{
// Clear Irq
SX1272Write( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_PAYLOADCRCERROR );
if( LoRaSettings.RxSingleOn == true ) // Rx single mode
{
RFLRState = RFLR_STATE_RX_INIT;
}
else
{
RFLRState = RFLR_STATE_RX_RUNNING;
}
break;
}
{
uint8_t rxSnrEstimate;
SX1272Read( REG_LR_PKTSNRVALUE, &rxSnrEstimate );
if( rxSnrEstimate & 0x80 ) // The SNR sign bit is 1
{
// Invert and divide by 4
RxPacketSnrEstimate = ( ( ~rxSnrEstimate + 1 ) & 0xFF ) >> 2;
RxPacketSnrEstimate = -RxPacketSnrEstimate;
}
else
{
// Divide by 4
RxPacketSnrEstimate = ( rxSnrEstimate & 0xFF ) >> 2;
}
}
