static int __init stih415_configure_miphy_uport(void)
{
struct sysconf_field *sc_miphy1_ref_clk,
*sc_sata1_hc_reset, *sc_sata_pcie_sel,
*sc_sata0_hc_reset;
sc_pcie_mp_select = sysconf_claim(SYSCONF(335),
0, 0, "pcie-mp");
BUG_ON(!sc_pcie_mp_select);
/* SATA0_SOFT_RST_N_SATA: sata0_soft_rst_n_sata. */
sc_sata0_hc_reset = sysconf_claim(SYSCONF(377), 7, 7, "MiPHY");
BUG_ON(!sc_sata0_hc_reset);
/* SELECT_SATA: select_sata. */
sc_sata_pcie_sel = sysconf_claim(SYSCONF(333), 1, 1, "MiPHY");
BUG_ON(!sc_sata_pcie_sel);
/* SATAPHY1_OSC_FORCE_EXT: SATAphy1_osc_force_ext. */
sc_miphy1_ref_clk = sysconf_claim(SYSCONF(333), 2, 2, "MiPHY");
BUG_ON(!sc_miphy1_ref_clk);
/*SATA1_SOFT_RST_N_SATA: sata1_soft_rst_n_sata */
sc_sata1_hc_reset = sysconf_claim(SYSCONF(377), 3, 3, "SATA");
BUG_ON(!sc_sata1_hc_reset);
/* Deassert Soft Reset to SATA0 */
sysconf_write(sc_sata0_hc_reset, 1);
/* If the 100MHz xtal for PCIe is present, then the microport interface
* will already have a clock, so there is no need to flip to the 30MHz
* clock here. If it isn't then we have to switch miphy lane 1 to use
* the 30MHz clock, as otherwise we will not be able to talk to lane 0
* since the uport interface itself is clocked from lane1
*/
if (stih415_miphy_modes[1] != PCIE_MODE) {
/* Put MiPHY1 in reset - rst_per_n[32] */
sysconf_write(sc_miphy_reset[1], 0);
/* Put SATA1 HC in reset - rst_per_n[30] */
sysconf_write(sc_sata1_hc_reset, 0);
/* Now switch to Phy interface to SATA HC not PCIe HC */
sysconf_write(sc_sata_pcie_sel, 1);
/* Select the Uport to use MiPHY1 */
stih415_pcie_mp_select(1);
/* Take SATA1 HC out of reset - rst_per_n[30] */
sysconf_write(sc_sata1_hc_reset, 1);
/* MiPHY1 needs to be using the MiPHY0 reference clock */
sysconf_write(sc_miphy1_ref_clk, 1);
/* Take MiPHY1 out of reset - rst_per_n[32] */
sysconf_write(sc_miphy_reset[1], 1);
}
return platform_device_register(&stih415_pcie_mp_device);
}
void __init stih415_configure_miphy(struct stih415_miphy_config *config)
{
int err = 0;
memcpy(stih415_miphy_modes, config->modes, sizeof(stih415_miphy_modes));
/*Reset to MIPHY0 */
sc_miphy_reset[0] = sysconf_claim(SYSCONF(376), 18, 18, "SATA");
BUG_ON(!sc_miphy_reset[0]);
/* Reset to MIPHY1 */
sc_miphy_reset[1] = sysconf_claim(SYSCONF(376), 19, 19, "SATA");
BUG_ON(!sc_miphy_reset[1]);
err = stih415_configure_miphy_uport();
}
/* Initialize group of timer blocks */
void prealloc_gt_timers(void)
{ /* On certain boxes SYSCONF in this function might get called earlier than
* the one in set_num_additional_processors(), so unset white_box_enabled
* for this SYSCONF to avoid issues
*/
# ifdef __MVS__
# ifdef DEBUG
boolean_t white_box_enabled = gtm_white_box_test_case_enabled;
if (white_box_enabled)
gtm_white_box_test_case_enabled = FALSE;
# endif
SYSCONF(_SC_CLK_TCK, gtm_zos_HZ); /* get the real value */
# ifdef DEBUG
if (white_box_enabled)
gtm_white_box_test_case_enabled = TRUE;
# endif
# endif
/* Preallocate some timer blocks. This will be all the timer blocks we hope to need.
* Allocate them with 8 bytes of possible data each.
* If more timer blocks are needed, we will allocate them as needed.
*/
gt_timers_alloc(); /* Allocate timers */
/* Now initialize the safe timers. Must be done dynamically to avoid the situation where this module always references all
* possible safe timers thus pulling extra stuff into executables that don't need or want it.
*
* First step, fill in the safe timers contained within this module which are always available.
*/
ADD_SAFE_HNDLR(&hiber_wake); /* Resident in this module */
ADD_SAFE_HNDLR(&wake_alarm); /* Standalone module containing on one global reference */
}
int stih415_gmac1_claim(struct stm_pad_state *state, void *priv)
{
gbit_sc[1] = sysconf_claim(SYSCONF(29), 6, 8, "gmac-1");
if (!gbit_sc[1])
return -1;
sysconf_write(gbit_sc[1], 0);
return 0;
}
int stih415_gmac0_claim(struct stm_pad_state *state, void *priv)
{
gbit_sc[0] = sysconf_claim(SYSCONF(382), 6, 8, "gmac-0");
if (!gbit_sc[0])
return -1;
sysconf_write(gbit_sc[0], 0);
return 0;
}
static int __init stxh205_suspend_setup(void)
{
struct sysconf_field *sc[2];
int i;
sc[0] = sysconf_claim(SYSCONF(169), 2, 2, "PM");
/* ClockGen_D.Pll lock status */
sc[1] = sysconf_claim(SYSCONF(154), 2, 2, "PM");
for (i = 0; i < ARRAY_SIZE(sc); ++i)
if (!sc[i])
goto error;
a0_ic_lp_on_clk = clk_get(NULL, "CLK_A0_IC_REG_LP_ON");
a0_ref_clk = clk_get(NULL, "CLK_A0_REF");
a1_pll0_hs_clk = clk_get(NULL, "CLK_A1_PLL0HS");
a1_ddr_clk = clk_get(NULL, "CLK_A1_IC_DDRCTRL");
a1_pll1_ls_clk = clk_get(NULL, "CLK_A1_PLL1LS");
a1_eth_phy_clk = clk_get(NULL, "CLK_A1_ETH_PHY");
if (a0_ref_clk == ERR_PTR(-ENOENT) ||
a0_ic_lp_on_clk == ERR_PTR(-ENOENT) ||
a1_pll0_hs_clk == ERR_PTR(-ENOENT) ||
a1_pll0_hs_clk == ERR_PTR(-ENOENT) ||
a1_pll1_ls_clk == ERR_PTR(-ENOENT) ||
a1_eth_phy_clk == ERR_PTR(-ENOENT))
goto error;
cga0 = ioremap_nocache(0xfde98000, 0x1000);
cga1 = ioremap_nocache(0xfdab8000, 0x1000);
return stm_suspend_register(&stxh205_suspend);
error:
pr_err("[STM][PM] Error to acquire the sysconf registers\n");
for (i = 0; i < ARRAY_SIZE(sc); ++i)
if (sc[i])
sysconf_release(sc[i]);
return -EBUSY;
}
/* STiH205 has 1 × eSATA or 1 × PCI-express, and can be configured
* to map PCIe, instead of eSATA, on PHY Lane */
void __init stxh205_configure_miphy(struct stxh205_miphy_config *config)
{
struct sysconf_field *sel_sata;
if (config->iface != UPORT_IF) {
printk(KERN_ERR "MiPhy only supported in microport mode\n");
return;
}
sel_sata = sysconf_claim(SYSCONF(445), 1, 1, "sata/pcie");
if (!sel_sata) {
printk(KERN_ERR "Cannot claim SELECT_SATA sysconf\n");
return;
}
stxh205_miphy_modes[0] = config->mode;
stxh205_pcie_mp_platform_data.rx_pol_inv = config->rx_pol_inv;
stxh205_pcie_mp_platform_data.tx_pol_inv = config->tx_pol_inv;
/* Select either PCIE or SATA mode */
sysconf_write(sel_sata, config->mode == SATA_MODE);
if (config->mode == PCIE_MODE) {
struct sysconf_field *miphy_reset, *pcie_reset, *pcie_clk_sel;
/* Change addresses to other port */
stxh205_pcie_mp_device.resource[0].start = PCIE_UPORT_BASE,
stxh205_pcie_mp_device.resource[0].end =
PCIE_UPORT_BASE + UPORT_REG_SIZE;
miphy_reset = sysconf_claim(SYSCONF(460), 18, 18, "miphy");
pcie_reset = sysconf_claim(SYSCONF(461), 0, 0, "pcie");
pcie_clk_sel = sysconf_claim(SYSCONF(468), 0, 0, "pcie");
sysconf_write(miphy_reset, 0); /* Reset miphy */
sysconf_write(pcie_reset, 0); /* Reset PCIe */
sysconf_write(pcie_clk_sel, 1); /* Select 100MHz ext clock */
sysconf_write(miphy_reset, 1); /* Release miphy */
sysconf_write(pcie_reset, 1); /* Release PCIe */
}
platform_device_register(&stxh205_pcie_mp_device);
}
void __init stxh205_configure_pcie(struct stxh205_pcie_config *config)
{
struct sysconf_field *sc;
sc = sysconf_claim(SYSCONF(447), 0, 5, "pcie");
BUG_ON(!sc);
stxh205_plat_pcie_config.ops_handle = sc;
stxh205_plat_pcie_config.reset_gpio = config->reset_gpio;
stxh205_plat_pcie_config.reset = config->reset;
/* There is only one PCIe controller on the stxh205 */
stxh205_plat_pcie_config.miphy_num = 0;
platform_device_register(&stxh205_pcie_device);
}
void __init stih415_configure_sata(int port, struct stih415_sata_config *config)
{
struct stm_plat_sata_data *sata_data;
static int initialized[2];
sata_data = stih415_sata_devices[port].dev.platform_data;
BUG_ON(initialized[port]);
sc_sata_hc_pwr[port] = sysconf_claim(SYSCONF(336),
3 + port, 3 + port, "SATA");
if (!sc_sata_hc_pwr[port]) {
BUG();
return;
}
sata_data->host_restart = stih415_restart_sata;
platform_device_register(&stih415_sata_devices[port]);
}
MDIO(15, 4, 2, RET_BYPASS(3000)),/* MDIO*/
MDC(15, 5, 2, RET_NICLK(0, 1)),/* MDC */
DATA_IN(16, 0, 2, RET_SE_NICLK_IO(0, 0)),/* 5 RXD[0] */
DATA_IN(16, 1, 2, RET_SE_NICLK_IO(0, 0)),/* RXD[1] */
DATA_IN(16, 2, 2, RET_SE_NICLK_IO(0, 0)),/* RXD[2] */
DATA_IN(16, 3, 2, RET_SE_NICLK_IO(0, 0)),/* RXD[3] */
DATA_IN(15, 6, 2, RET_SE_NICLK_IO(0, 0)),/* RXDV */
DATA_IN(15, 7, 2, RET_SE_NICLK_IO(0, 0)),/* RX_ER */
CLOCK_IN(17, 0, 2, RET_NICLK(0, 0)),/* RXCLK */
},
.sysconfs_num = 5,
.sysconfs = (struct stm_pad_sysconf []) {
/* ETH0_GMAC_EN */
STM_PAD_SYSCONF(SYSCONF(166), 0, 0, 1),
/* MIIx_PHY_SEL */
STM_PAD_SYSCONF(SYSCONF(382), 2, 4, 0),
/* ENMIIx */
STM_PAD_SYSCONF(SYSCONF(382), 5, 5, 1),
/* TXCLK_NOT_CLK125 */
STM_PAD_SYSCONF(SYSCONF(382), 6, 6, 1),
/* TX_RETIMING_CLK */
STM_PAD_SYSCONF(SYSCONF(382), 8, 8, 0),
},
},
[1] = {
.gpios_num = 20,
.gpios = (struct stm_pad_gpio []) {
DATA_OUT(0, 0, 1, RET_SE_NICLK_IO(0, 0)),/* TXD[0] */
DATA_OUT(0, 1, 1, RET_SE_NICLK_IO(0, 0)),/* TXD[1] */
#include <sound/stm.h>
#include <asm/irq-ilc.h>
/* Audio subsystem resources ---------------------------------------------- */
/* Internal DAC */
static struct platform_device stih415_conv_dac = {
.name = "snd_conv_dac_sc",
.id = -1,
.dev.platform_data = &(struct snd_stm_conv_dac_sc_info) {
.source_bus_id = "snd_uni_player.2", /* DAC */
.channel_from = 0,
.channel_to = 1,
.nrst = { SYSCONF(329), 0, 0 },
.mode = { SYSCONF(329), 1, 2 },
.nsb = { SYSCONF(329), 3, 3 },
.softmute = { SYSCONF(329), 4, 4 },
.pdana = { SYSCONF(329), 5, 5 },
.pndbg = { SYSCONF(329), 6, 6 },
},
};
/* Bi-phase converter (outputs SPDIF) */
static struct platform_device stih415_conv_biphase = {
.name = "snd_conv_biphase",
.id = -1,
.dev.platform_data = &(struct snd_stm_conv_biphase_info) {
.source_bus_id = "snd_uni_player.3",
CLOCK_OUT(1, 1, 1, RET_NICLK(0)),/* MDC */
DATA_IN(1, 2, 1, RET_BYPASS(0)),/* CRS */
DATA_IN(1, 3, 1, RET_BYPASS(0)),/* MDINT */
DATA_IN(1, 4, 1, RET_BYPASS(0)),/* RXD[0] */
DATA_IN(1, 5, 1, RET_BYPASS(0)),/* RXD[1] */
DATA_IN(1, 6, 1, RET_BYPASS(0)),/* RXD[2] */
DATA_IN(1, 7, 1, RET_BYPASS(0)),/* RXD[3] */
DATA_IN(2, 0, 1, RET_BYPASS(0)),/* RXDV */
DATA_IN(2, 1, 1, RET_BYPASS(0)),/* RX_ER */
CLOCK_IN(2, 2, 1, RET_NICLK(0)),/* RXCLK */
PHY_CLOCK(2, 3, 1, RET_NICLK(0)),/* PHYCLK */
},
.sysconfs_num = 7,
.sysconfs = (struct stm_pad_sysconf []) {
/* ETH_POWERDOWN_REQ */
STM_PAD_SYSCONF(SYSCONF(23), 0, 0, 0),
/* ETH_MII_PHY_SEL */
STM_PAD_SYSCONF(SYSCONF(23), 2, 4, 0),
/* ETH_ENMII */
STM_PAD_SYSCONF(SYSCONF(23), 5, 5, 1),
/* ETH_SEL_TXCLK_NOT_CLK125 */
STM_PAD_SYSCONF(SYSCONF(23), 6, 6, 1),
/* ETH_SEL_INTERNAL_NOTEXT_PHYCLK */
STM_PAD_SYSCONF(SYSCONF(23), 7, 7, 1),
/* ETH_SEL_TX_RETIMING_CLK */
STM_PAD_SYSCONF(SYSCONF(23), 8, 8, 0),
/* ETH_GMAC_EN */
STM_PAD_SYSCONF(SYSCONF(23), 9, 9, 1),
},
};
static int __init snd_stm_stih415_probe(struct platform_device *pdev)
{
int result;
dev_dbg(&pdev->dev, "%s()", __func__);
if (!stm_soc_is_stih415()) {
dev_err(&pdev->dev, "Unsupported (not STiH415) SOC detected!");
return -EINVAL;
}
/* Claim external pcm clock sysconf */
snd_stm_stih415_pcm_clk_sel = sysconf_claim(SYSCONF(331), 8, 11,
"PCM_CLK_SEL");
if (!snd_stm_stih415_pcm_clk_sel) {
dev_err(&pdev->dev, "Failed to claim PCM_CLK_SEL");
return -EBUSY;
}
/* Claim bi-phase idle value sysconf */
snd_stm_stih415_biphase_idle_value = sysconf_claim(SYSCONF(331), 7, 7,
"BIPHASE_IDLE_VALUE");
if (!snd_stm_stih415_biphase_idle_value) {
dev_err(&pdev->dev, "Failed to claim BIPHASE_IDLE_VALUE");
result = -EBUSY;
goto error_sysconf_claim_biphase_idle_value;
}
/* Claim voip sysconf */
snd_stm_stih415_voip = sysconf_claim(SYSCONF(331), 2, 5, "VOIP");
if (!snd_stm_stih415_voip) {
dev_err(&pdev->dev, "Failed to claim VOIP");
result = -EBUSY;
goto error_sysconf_claim_voip;
}
/* Claim pcm player routing sysconf */
snd_stm_stih415_pcmp_valid_sel = sysconf_claim(SYSCONF(331), 0, 1,
"PCMP_VALID_SEL");
if (!snd_stm_stih415_pcmp_valid_sel) {
dev_err(&pdev->dev, "Failed to claim PCMP_VALID_SEL");
result = -EBUSY;
goto error_sysconf_claim_pcmp_valid_sel;
}
/* Set the sysconf values */
snd_stm_stih415_setup();
/* Register the sound card */
result = snd_stm_card_register();
if (result) {
dev_err(&pdev->dev, "Failed to register ALSA cards!");
goto error_card_register;
}
/* Register a procfs file */
result = snd_stm_info_register(&snd_stm_stih415_proc_entry,
dev_name(&pdev->dev), snd_stm_stih415_procfs, NULL);
if (result) {
dev_err(&pdev->dev, "Failed to register with procfs");
goto error_info_register;
}
return 0;
error_info_register:
error_card_register:
sysconf_release(snd_stm_stih415_pcmp_valid_sel);
error_sysconf_claim_pcmp_valid_sel:
sysconf_release(snd_stm_stih415_voip);
error_sysconf_claim_voip:
sysconf_release(snd_stm_stih415_biphase_idle_value);
error_sysconf_claim_biphase_idle_value:
sysconf_release(snd_stm_stih415_pcm_clk_sel);
return result;
}
*/
static unsigned long stx5206_standby_table[] __cacheline_aligned = {
END_MARKER,
END_MARKER
};
/* *********************
* MEM INSTRUCTION TABLE
* *********************
*/
static unsigned long stx5206_mem_table[] __cacheline_aligned = {
/* 1. Enables the DDR self refresh mode */
OR32(SYSCONF(38), (1 << 20)),
/* waits until the ack bit is zero */
WHILE_NE32(SYSSTA(4), 1, 1),
/* Disable the clock output */
UPDATE32(SYSCONF(4), ~(1 << 2), 0),
/* Disable the analogue input buffers of the pads */
OR32(SYSCONF(12), (1 << 10)),
/* 1.1 Turn-off the ClockGenD */
OR32(SYSCONF(11), (1 << 12)),
/* wait clock gen lock */
WHILE_NE32(SYSSTA(3), 1, 1),
END_MARKER,
UPDATE32(SYSCONF(12), ~(1 << 10), 0),
/* STBus Convertor config */
static struct stm_amba_bridge_config stih415_amba_usb_config = {
STM_DEFAULT_USB_AMBA_PLUG_CONFIG(128),
.type2.sd_config_missing = 1,
};
static struct stm_plat_usb_data stih415_usb_platform_data[] = {
[0] = {
.flags = STM_PLAT_USB_FLAGS_STRAP_8BIT,
.amba_config = &stih415_amba_usb_config,
.device_config = &(struct stm_device_config){
.init = stih415_usb_init,
.power = stih415_usb_power,
.sysconfs_num = 4,
.sysconfs = (struct stm_device_sysconf []) {
STM_DEVICE_SYSCONF(SYSCONF(336), 0, 0,
USB_HOST_PWR),
STM_DEVICE_SYSCONF(SYSCONF(384), 0, 0,
USB_PWR_ACK),
STM_DEVICE_SYSCONF(SYSCONF(332), 0, 0,
USB_IN_DC_SHIFT),
STM_DEVICE_SYSCONF(SYSCONF(332), 3, 3,
USB_IN_EDGE_CTRL),
},
.pad_config = &(struct stm_pad_config) {
.gpios_num = 2,
.gpios = (struct stm_pad_gpio []) {
/* Overcurrent detection */
STM_PAD_PIO_IN(9, 4, 1),
/* USB power enable */
// STM_PAD_PIO_OUT(9, 5, 1),