void lp_ticker_init(void)
{
if (lp_ticker_inited) {
return;
}
lp_ticker_inited = 1;
counter_major = 0;
cd_major_minor_clks = 0;
cd_minor_clks = 0;
wakeup_tick = (uint32_t) -1;
// Reset module
SYS_ResetModule(timer2_modinit.rsetidx);
SYS_ResetModule(timer3_modinit.rsetidx);
// Select IP clock source
CLK_SetModuleClock(timer2_modinit.clkidx, timer2_modinit.clksrc, timer2_modinit.clkdiv);
CLK_SetModuleClock(timer3_modinit.clkidx, timer3_modinit.clksrc, timer3_modinit.clkdiv);
// Enable IP clock
CLK_EnableModuleClock(timer2_modinit.clkidx);
CLK_EnableModuleClock(timer3_modinit.clkidx);
// Configure clock
uint32_t clk_timer2 = TIMER_GetModuleClock((TIMER_T *) NU_MODBASE(timer2_modinit.modname));
uint32_t prescale_timer2 = clk_timer2 / TMR2_CLK_PER_SEC - 1;
MBED_ASSERT((prescale_timer2 != (uint32_t) -1) && prescale_timer2 <= 127);
MBED_ASSERT((clk_timer2 % TMR2_CLK_PER_SEC) == 0);
uint32_t cmp_timer2 = TMR2_CLK_PER_TMR2_INT;
MBED_ASSERT(cmp_timer2 >= TMR_CMP_MIN && cmp_timer2 <= TMR_CMP_MAX);
// Continuous mode
// NOTE: TIMER_CTL_CNTDATEN_Msk exists in NUC472, but not in M451/M480. In M451/M480, TIMER_CNT is updated continuously by default.
((TIMER_T *) NU_MODBASE(timer2_modinit.modname))->CTL = TIMER_PERIODIC_MODE | prescale_timer2/* | TIMER_CTL_CNTDATEN_Msk*/;
((TIMER_T *) NU_MODBASE(timer2_modinit.modname))->CMP = cmp_timer2;
// Set vector
NVIC_SetVector(timer2_modinit.irq_n, (uint32_t) timer2_modinit.var);
NVIC_SetVector(timer3_modinit.irq_n, (uint32_t) timer3_modinit.var);
NVIC_EnableIRQ(timer2_modinit.irq_n);
NVIC_EnableIRQ(timer3_modinit.irq_n);
TIMER_EnableInt((TIMER_T *) NU_MODBASE(timer2_modinit.modname));
TIMER_EnableWakeup((TIMER_T *) NU_MODBASE(timer2_modinit.modname));
// NOTE: TIMER_Start() first and then lp_ticker_set_interrupt(); otherwise, we may get stuck in lp_ticker_read() because
// timer is not running.
// Start timer
TIMER_Start((TIMER_T *) NU_MODBASE(timer2_modinit.modname));
// Schedule wakeup to match semantics of lp_ticker_get_compare_match()
lp_ticker_set_interrupt(wakeup_tick);
}
void lp_ticker_init(void)
{
if (lp_ticker_inited) {
return;
}
lp_ticker_inited = 1;
counter_major = 0;
cd_major_minor_ms = 0;
cd_minor_ms = 0;
wakeup_tick = TMR_CMP_MAX * MS_PER_TMR2_CLK / MS_PER_TICK;
// Reset module
SYS_ResetModule(timer2_modinit.rsetidx);
SYS_ResetModule(timer3_modinit.rsetidx);
// Select IP clock source
CLK_SetModuleClock(timer2_modinit.clkidx, timer2_modinit.clksrc, timer2_modinit.clkdiv);
CLK_SetModuleClock(timer3_modinit.clkidx, timer3_modinit.clksrc, timer3_modinit.clkdiv);
// Enable IP clock
CLK_EnableModuleClock(timer2_modinit.clkidx);
CLK_EnableModuleClock(timer3_modinit.clkidx);
// Configure clock
uint32_t clk_timer2 = TIMER_GetModuleClock((TIMER_T *) NU_MODBASE(timer2_modinit.modname));
uint32_t prescale_timer2 = clk_timer2 / TMR2_CLK_FREQ - 1;
MBED_ASSERT((prescale_timer2 != (uint32_t) -1) && prescale_timer2 <= 127);
uint32_t cmp_timer2 = MS_PER_TMR2_INT / MS_PER_TMR2_CLK;
MBED_ASSERT(cmp_timer2 >= TMR_CMP_MIN && cmp_timer2 <= TMR_CMP_MAX);
// Continuous mode
((TIMER_T *) NU_MODBASE(timer2_modinit.modname))->CTL = TIMER_PERIODIC_MODE | prescale_timer2 | TIMER_CTL_CNTDATEN_Msk;
((TIMER_T *) NU_MODBASE(timer2_modinit.modname))->CMP = cmp_timer2;
// Set vector
NVIC_SetVector(timer2_modinit.irq_n, (uint32_t) timer2_modinit.var);
NVIC_SetVector(timer3_modinit.irq_n, (uint32_t) timer3_modinit.var);
NVIC_EnableIRQ(timer2_modinit.irq_n);
NVIC_EnableIRQ(timer3_modinit.irq_n);
TIMER_EnableInt((TIMER_T *) NU_MODBASE(timer2_modinit.modname));
TIMER_EnableWakeup((TIMER_T *) NU_MODBASE(timer2_modinit.modname));
// Schedule wakeup to match semantics of lp_ticker_get_compare_match()
lp_ticker_set_interrupt(lp_ticker_read(), wakeup_tick);
// Start timer
TIMER_Start((TIMER_T *) NU_MODBASE(timer2_modinit.modname));
}
void can_init(can_t *obj, PinName rd, PinName td)
{
uint32_t can_td = (CANName)pinmap_peripheral(td, PinMap_CAN_TD);
uint32_t can_rd = (CANName)pinmap_peripheral(rd, PinMap_CAN_RD);
obj->can = (CANName)pinmap_merge(can_td, can_rd);
MBED_ASSERT((int)obj->can != NC);
const struct nu_modinit_s *modinit = get_modinit(obj->can, can_modinit_tab);
MBED_ASSERT(modinit != NULL);
MBED_ASSERT(modinit->modname == obj->can);
// Reset this module
SYS_ResetModule(modinit->rsetidx);
// Enable IP clock
CLK_EnableModuleClock(modinit->clkidx);
obj->index = 0;
pinmap_pinout(td, PinMap_CAN_TD);
pinmap_pinout(rd, PinMap_CAN_RD);
/* For M453 mbed Board Transmitter Setting (RS Pin) */
GPIO_SetMode(PA, BIT0| BIT1, GPIO_MODE_OUTPUT);
PA0 = 0x00;
PA1 = 0x00;
CAN_Open((CAN_T *)NU_MODBASE(obj->can), 500000, CAN_NORMAL_MODE);
can_filter(obj, 0, 0, CANStandard, 0);
}
void us_ticker_init(void)
{
if (ticker_inited) {
return;
}
ticker_inited = 1;
// Reset IP
SYS_ResetModule(TIMER_MODINIT.rsetidx);
// Select IP clock source
CLK_SetModuleClock(TIMER_MODINIT.clkidx, TIMER_MODINIT.clksrc, TIMER_MODINIT.clkdiv);
// Enable IP clock
CLK_EnableModuleClock(TIMER_MODINIT.clkidx);
// Timer for normal counter
uint32_t clk_timer = TIMER_GetModuleClock((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname));
uint32_t prescale_timer = clk_timer / NU_TMRCLK_PER_SEC - 1;
MBED_ASSERT((prescale_timer != (uint32_t) -1) && prescale_timer <= 127);
MBED_ASSERT((clk_timer % NU_TMRCLK_PER_SEC) == 0);
uint32_t cmp_timer = TMR_CMP_MAX;
MBED_ASSERT(cmp_timer >= TMR_CMP_MIN && cmp_timer <= TMR_CMP_MAX);
// NOTE: TIMER_CTL_CNTDATEN_Msk exists in NUC472, but not in M451. In M451, TIMER_CNT is updated continuously by default.
((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname))->CTL = TIMER_CONTINUOUS_MODE | prescale_timer/* | TIMER_CTL_CNTDATEN_Msk*/;
((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname))->CMP = cmp_timer;
NVIC_SetVector(TIMER_MODINIT.irq_n, (uint32_t) TIMER_MODINIT.var);
NVIC_EnableIRQ(TIMER_MODINIT.irq_n);
TIMER_EnableInt((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname));
TIMER_Start((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname));
}
void UART0_Init(void)
{
/* Reset IP */
SYS_ResetModule(UART0_RST);
UART0->BAUD = 0x67; /* Baud Rate:115200 OSC:12MHz */
UART0->TLCTL = 0x03; /* Character len is 8 bits */
}
//=========================================================================
__myevic__ void SetPWMClock()
{
uint32_t clk;
if ( gFlags.pwm_pll )
{
clk = CLK_CLKSEL2_PWM0SEL_PLL;
PWMCycles = CLK_GetPLLClockFreq() / BBC_PWM_FREQ;
}
else
{
clk = CLK_CLKSEL2_PWM0SEL_PCLK0;
PWMCycles = CLK_GetPCLK0Freq() / BBC_PWM_FREQ;
}
MaxDuty = PWMCycles - 1;
MinBuck = PWMCycles / 48;
MaxBoost = PWMCycles / 12;
ProbeDuty = PWMCycles / 8;
BoostWindow = PWMCycles / 19;
#define MaxBuck MaxDuty
#define MinBoost MaxDuty
if ( ISCUBO200 || ISRX200S || ISRX23 || ISRX300 )
{
MaxDuty = 95 * PWMCycles / 100;
}
CLK_EnableModuleClock( PWM0_MODULE );
CLK_SetModuleClock( PWM0_MODULE, clk, 0 );
SYS_ResetModule( PWM0_RST );
}
void UART0_Init(void)
{
/* Reset IP */
SYS_ResetModule(UART0_RST);
/* Configure UART0 and set UART0 Baudrate */
UART_Open(UART0, 115200);
}
//=========================================================================
//----- (00007EF4) --------------------------------------------------------
__myevic__ void InitUART0()
{
SYS_ResetModule( UART0_RST );
UART_Open( UART0, 115200 );
myputc = (FPUTC_FUNC*)&UART0_Putc;
}
void SYS_Init(void)
{
/*---------------------------------------------------------------------------------------------------------*/
/* Init System Clock */
/*---------------------------------------------------------------------------------------------------------*/
/* Enable Internal RC clock */
CLK_EnableXtalRC(CLK_PWRCON_OSC22M_EN_Msk);
/* Waiting for IRC22M clock ready */
CLK_WaitClockReady(CLK_CLKSTATUS_OSC22M_STB_Msk);
/* Switch HCLK clock source to Internal RC and HCLK source divide 1 */
CLK_SetHCLK(CLK_CLKSEL0_HCLK_S_HIRC, CLK_CLKDIV_HCLK(1));
/* Enable external 12MHz XTAL, internal 22.1184MHz */
CLK_EnableXtalRC(CLK_PWRCON_XTL12M_EN_Msk | CLK_PWRCON_OSC22M_EN_Msk);
/* Enable PLL and Set PLL frequency */
CLK_SetCoreClock(PLLCON_SETTING);
/* Waiting for clock ready */
CLK_WaitClockReady(CLK_CLKSTATUS_PLL_STB_Msk | CLK_CLKSTATUS_XTL12M_STB_Msk | CLK_CLKSTATUS_OSC22M_STB_Msk);
/* Switch HCLK clock source to PLL, STCLK to HCLK/2 */
CLK_SetHCLK(CLK_CLKSEL0_HCLK_S_PLL, CLK_CLKDIV_HCLK(2));
/* Enable UART module clock */
CLK_EnableModuleClock(UART0_MODULE);
/* Enable PWM module clock */
CLK_EnableModuleClock(PWM01_MODULE);
CLK_EnableModuleClock(PWM23_MODULE);
/* Select UART module clock source */
CLK_SetModuleClock(UART0_MODULE, CLK_CLKSEL1_UART_S_HXT, CLK_CLKDIV_UART(1));
/* Select PWM module clock source */
CLK_SetModuleClock(PWM01_MODULE, CLK_CLKSEL1_PWM01_S_HXT, 0);
CLK_SetModuleClock(PWM23_MODULE, CLK_CLKSEL1_PWM23_S_HXT, 0);
/* Reset PWMA channel0~channel3 */
SYS_ResetModule(PWM03_RST);
/* Update System Core Clock */
/* User can use SystemCoreClockUpdate() to calculate PllClock, SystemCoreClock and CycylesPerUs automatically. */
//SystemCoreClockUpdate();
PllClock = PLL_CLOCK; // PLL
SystemCoreClock = PLL_CLOCK / 1; // HCLK
CyclesPerUs = PLL_CLOCK / 1000000; // For SYS_SysTickDelay()
/*---------------------------------------------------------------------------------------------------------*/
/* Init I/O Multi-function */
/*---------------------------------------------------------------------------------------------------------*/
/* Set P3 multi-function pins for UART0 RXD and TXD */
SYS->P3_MFP = SYS_MFP_P30_RXD0 | SYS_MFP_P31_TXD0;
/* Set P2 multi-function pins for PWMA Channel0~3 */
SYS->P2_MFP = SYS_MFP_P20_PWM0 | SYS_MFP_P21_PWM1 | SYS_MFP_P22_PWM2 | SYS_MFP_P23_PWM3;
}
void i2c_Init(void) //ericyang 20151120 add for oled i2c driver
{
CLK_EnableModuleClock(I2C0_MODULE);//ericyang 20151120
SYS_ResetModule(I2C0_RST);
SYS->GPB_MFP = (SYS->GPB_MFP & (~SYS_GPB_MFP_PB2MFP_Msk) ) | SYS_GPB_MFP_PB2MFP_I2C_SCL;
SYS->GPB_MFP = (SYS->GPB_MFP & (~SYS_GPB_MFP_PB3MFP_Msk) ) | SYS_GPB_MFP_PB3MFP_I2C_SDA;
I2C_Open(I2C0, 400000);
}
void UART0_Init(void)
{
/* Reset IP */
SYS_ResetModule(UART0_RST);
UART0->BAUD = 0x67; /* Baud Rate:115200 OSC:12MHz */
UART0->TLCTL = 0x03; /* Character len is 8 bits */
/* Enable Interrupt and install the call back function */
UART_ENABLE_INT(UART0, (UART_IER_RDA_IE_Msk | UART_IER_THRE_IE_Msk | UART_IER_RTO_IE_Msk));
}
void us_ticker_init(void)
{
if (us_ticker_inited) {
return;
}
counter_major = 0;
cd_major_minor_us = 0;
cd_minor_us = 0;
us_ticker_inited = 1;
// Reset IP
SYS_ResetModule(timer0hires_modinit.rsetidx);
SYS_ResetModule(timer1hires_modinit.rsetidx);
// Select IP clock source
CLK_SetModuleClock(timer0hires_modinit.clkidx, timer0hires_modinit.clksrc, timer0hires_modinit.clkdiv);
CLK_SetModuleClock(timer1hires_modinit.clkidx, timer1hires_modinit.clksrc, timer1hires_modinit.clkdiv);
// Enable IP clock
CLK_EnableModuleClock(timer0hires_modinit.clkidx);
CLK_EnableModuleClock(timer1hires_modinit.clkidx);
// Timer for normal counter
uint32_t clk_timer0 = TIMER_GetModuleClock((TIMER_T *) NU_MODBASE(timer0hires_modinit.modname));
uint32_t prescale_timer0 = clk_timer0 / TMR0HIRES_CLK_PER_SEC - 1;
MBED_ASSERT((prescale_timer0 != (uint32_t) -1) && prescale_timer0 <= 127);
MBED_ASSERT((clk_timer0 % TMR0HIRES_CLK_PER_SEC) == 0);
uint32_t cmp_timer0 = TMR0HIRES_CLK_PER_TMR0HIRES_INT;
MBED_ASSERT(cmp_timer0 >= TMR_CMP_MIN && cmp_timer0 <= TMR_CMP_MAX);
// NOTE: TIMER_CTL_CNTDATEN_Msk exists in NUC472, but not in M451. In M451, TIMER_CNT is updated continuously by default.
((TIMER_T *) NU_MODBASE(timer0hires_modinit.modname))->CTL = TIMER_PERIODIC_MODE | prescale_timer0/* | TIMER_CTL_CNTDATEN_Msk*/;
((TIMER_T *) NU_MODBASE(timer0hires_modinit.modname))->CMP = cmp_timer0;
NVIC_SetVector(timer0hires_modinit.irq_n, (uint32_t) timer0hires_modinit.var);
NVIC_SetVector(timer1hires_modinit.irq_n, (uint32_t) timer1hires_modinit.var);
NVIC_EnableIRQ(timer0hires_modinit.irq_n);
NVIC_EnableIRQ(timer1hires_modinit.irq_n);
TIMER_EnableInt((TIMER_T *) NU_MODBASE(timer0hires_modinit.modname));
TIMER_Start((TIMER_T *) NU_MODBASE(timer0hires_modinit.modname));
}
void UART_Init(void)
{
/*---------------------------------------------------------------------------------------------------------*/
/* Init UART */
/*---------------------------------------------------------------------------------------------------------*/
/* Reset IP */
SYS_ResetModule(UART_RST);
/* Configure UART and set UART Baudrate */
UART_Open(UART, 115200);
}
void UART0_Init()
{
/*---------------------------------------------------------------------------------------------------------*/
/* Init UART */
/*---------------------------------------------------------------------------------------------------------*/
/* Reset UART module */
SYS_ResetModule(UART0_RST);
/* Configure UART0 and set UART0 baud rate */
UART_Open(UART0, 115200);
}
void UART0_Init()
{
/*---------------------------------------------------------------------------------------------------------*/
/* Init UART */
/*---------------------------------------------------------------------------------------------------------*/
/* Reset UART0 module */
SYS_ResetModule(UART0_RST);
/* Init UART0 to 115200-8n1 for print message */
UART_Open(UART0, 115200);
}
void UART1_Init()
{
/*---------------------------------------------------------------------------------------------------------*/
/* Init UART */
/*---------------------------------------------------------------------------------------------------------*/
/* Reset UART1 module */
SYS_ResetModule(UART1_RST);
/* Configure UART1 and set UART1 Baudrate */
UART_Open(UART1, 115200);
}
void can_reset(can_t *obj)
{
const struct nu_modinit_s *modinit = get_modinit(obj->can, can_modinit_tab);
MBED_ASSERT(modinit != NULL);
MBED_ASSERT(modinit->modname == obj->can);
// Reset this module
SYS_ResetModule(modinit->rsetidx);
}
void UART0_Init(void)
{
/*---------------------------------------------------------------------------------------------------------*/
/* Init UART */
/*---------------------------------------------------------------------------------------------------------*/
/* Reset IP */
SYS_ResetModule(UART0_RST);
/* Configure UART0 and set UART0 Baudrate */
UART0->LCR |=0x07;
UART0->BAUD = 0x30000066; /* 12MHz reference clock input, for 115200 */
}
void can_free(can_t *obj)
{
const struct nu_modinit_s *modinit = get_modinit(obj->can, can_modinit_tab);
MBED_ASSERT(modinit != NULL);
MBED_ASSERT(modinit->modname == obj->can);
// Reset this module
SYS_ResetModule(modinit->rsetidx);
CLK_DisableModuleClock(modinit->clkidx);
}
void setupCommandUART()
{
/* Enable peripheral clock */
CLK_EnableModuleClock(UART0_MODULE);
/* Peripheral clock source */
CLK_SetModuleClock(UART0_MODULE, CLK_CLKSEL1_UARTSEL_HIRC, CLK_CLKDIV0_UART(1));
/* Set PD multi-function pins for UART0 RXD, TXD */
SYS->GPD_MFPL = SYS_GPD_MFPL_PD0MFP_UART0_RXD | SYS_GPD_MFPL_PD1MFP_UART0_TXD;
/* Reset UART module */
SYS_ResetModule(UART0_RST);
/* Configure UART0 and set UART0 Baudrate */
UART_Open(UART0, 115200);
}
void UART0_Init(void)
{
/*---------------------------------------------------------------------------------------------------------*/
/* Init UART */
/*---------------------------------------------------------------------------------------------------------*/
/* Reset IP */
SYS_ResetModule(UART0_RST);
/* Configure UART0 and set UART0 Baudrate */
UART0->LCR |=0x07;
UART0->BAUD = 0x30000067; /* 12MHz reference clock input, for 115200 */
//UART0->BAUD = UART_BAUD_MODE2 | UART_BAUD_DIV_MODE2(__XTAL, 115200);
//_UART_SET_DATA_FORMAT(UART0, UART_WORD_LEN_8 | UART_PARITY_NONE | UART_STOP_BIT_1);
}
void UART1_Init(void)
{
/*---------------------------------------------------------------------------------------------------------*/
/* Init UART */
/*---------------------------------------------------------------------------------------------------------*/
/* Reset IP */
SYS_ResetModule(UART1_RST);
/* Configure UART1 and set UART1 Baudrate */
UART_Open(UART1, 115200);
/* Enable UART1 RX Time-Out Interrupt and RX Data Available Interrupt */
UART_EnableInt(UART1, UART_INTEN_RXTOIEN_Msk | UART_INTEN_THREIEN_Msk | UART_INTEN_RDAIEN_Msk);
}
void setupGpsUART()
{
#ifdef GPS_UART
/* Enable peripheral clock */
CLK_EnableModuleClock(UART1_MODULE);
/* Peripheral clock source */
CLK_SetModuleClock(UART1_MODULE, CLK_CLKSEL1_UARTSEL_HIRC, CLK_CLKDIV0_UART(1));
/* Set PE multi-function pins for UART0 RXD, TXD */
SYS->GPE_MFPH = SYS_GPE_MFPH_PE13MFP_UART1_RXD | SYS_GPE_MFPH_PE12MFP_UART1_TXD;
/* Reset UART module */
SYS_ResetModule(UART1_RST);
/* Configure UART0 and set UART0 Baudrate */
UART_Open(UART1, GPS_BAUD);
UART_EnableInt(UART1, UART_INTEN_RDAIEN_Msk);
#endif
}
// ---------------------------------------------------------------------------------------
// PWM initialize setting
// Set PC9~PC11 as PWM output
// Select PCLK as PWM module clock source
// ---------------------------------------------------------------------------------------
void Buzzer_Init()
{
/* Enable PWM module clock */
CLK_EnableModuleClock(PWM0_MODULE);
/* Select PWM module clock source */
CLK_SetModuleClock(PWM0_MODULE, CLK_CLKSEL2_PWM0SEL_PCLK0, 0);
/* Reset PWM1 channel 0~5 */
SYS_ResetModule(PWM0_RST);
/* Set PC9~PC11 multi-function pins for PWM1 Channel0~2 */
SYS->GPC_MFPL &= ~(SYS_GPC_MFPL_PC0MFP_Msk);
SYS->GPC_MFPL |= SYS_GPC_MFPL_PC0MFP_PWM0_CH0;
}
void setupUART()
{
/* Enable peripheral clock */
CLK_EnableModuleClock(UART_MODULE);
/* Peripheral clock source */
CLK_SetModuleClock(UART_MODULE, CLK_CLKSEL1_UART_S_HIRC, CLK_CLKDIV_UART(1));
/* Set PD multi-function pins for UART0 RXD, TXD */
SYS->P1_MFP &= ~(SYS_MFP_P12_Msk | SYS_MFP_P13_Msk);
SYS->P1_MFP |= (SYS_MFP_P12_RXD | SYS_MFP_P13_TXD);
//SYS->P0_MFP = SYS_MFP_P00_TXD | SYS_MFP_P01_RXD;
/* Reset UART module */
SYS_ResetModule(UART_RST);
/* Configure UART0 and set UART0 Baudrate */
UART_Open(UART0, 115200);
}
void UART0_Init(void)
{
/*---------------------------------------------------------------------------------------------------------*/
/* Init UART */
/*---------------------------------------------------------------------------------------------------------*/
/* Reset IP */
SYS_ResetModule(UART0_RST);
/* Configure UART0 and set UART0 Baudrate */
//UART_Open(UART0, 115200);
#if 1
CLK->CLKSEL1 = (CLK->CLKSEL1 & ~CLK_CLKSEL1_UART_S_Msk) | CLK_CLKSEL1_UART_S_HXT; /* Select 12 Mhz XTAL */
UART0->BAUD = 0x67; /* Baud Rate:115200 OSC:12MHz */
UART0->TLCTL = 0x03; /* Character len is 8 bits */
#endif
}
void us_ticker_init(void)
{
if (ticker_inited) {
/* By HAL spec, ticker_init allows the ticker to keep counting and disables the
* ticker interrupt. */
us_ticker_disable_interrupt();
return;
}
ticker_inited = 1;
// Reset IP
SYS_ResetModule(TIMER_MODINIT.rsetidx);
// Select IP clock source
CLK_SetModuleClock(TIMER_MODINIT.clkidx, TIMER_MODINIT.clksrc, TIMER_MODINIT.clkdiv);
// Enable IP clock
CLK_EnableModuleClock(TIMER_MODINIT.clkidx);
TIMER_T *timer_base = (TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname);
// Timer for normal counter
uint32_t clk_timer = TIMER_GetModuleClock(timer_base);
uint32_t prescale_timer = clk_timer / NU_TMRCLK_PER_SEC - 1;
MBED_ASSERT((prescale_timer != (uint32_t) -1) && prescale_timer <= 127);
MBED_ASSERT((clk_timer % NU_TMRCLK_PER_SEC) == 0);
uint32_t cmp_timer = TMR_CMP_MAX;
MBED_ASSERT(cmp_timer >= TMR_CMP_MIN && cmp_timer <= TMR_CMP_MAX);
// NOTE: TIMER_CTL_CNTDATEN_Msk exists in NUC472, but not in M451. In M451, TIMER_CNT is updated continuously by default.
timer_base->CTL = TIMER_CONTINUOUS_MODE | prescale_timer/* | TIMER_CTL_CNTDATEN_Msk*/;
timer_base->CMP = cmp_timer;
NVIC_SetVector(TIMER_MODINIT.irq_n, (uint32_t) TIMER_MODINIT.var);
NVIC_DisableIRQ(TIMER_MODINIT.irq_n);
TIMER_EnableInt(timer_base);
TIMER_Start(timer_base);
/* Wait for timer to start counting and raise active flag */
while(! (timer_base->CTL & TIMER_CTL_ACTSTS_Msk));
}
UINT8 SPIFlash_Initiate(void)
{
UINT16 ui16Temp;
UINT32 ui32Temp;
UINT32 u32Count;
// SPI0: GPA1=SSB00, GPA2=SCLK0, GPA3=MISO0, GPA4=MOSI0
SYS->GPA_MFP =
(SYS->GPA_MFP & (~(SYS_GPA_MFP_PA0MFP_Msk|SYS_GPA_MFP_PA1MFP_Msk|SYS_GPA_MFP_PA2MFP_Msk|SYS_GPA_MFP_PA3MFP_Msk)) )
| (SYS_GPA_MFP_PA0MFP_SPI_MOSI0|SYS_GPA_MFP_PA1MFP_SPI_SCLK|SYS_GPA_MFP_PA2MFP_SPI_SSB0|SYS_GPA_MFP_PA3MFP_SPI_MISO0);
// Reset IP module
CLK_EnableModuleClock(SPI0_MODULE);
SYS_ResetModule(SPI0_RST);
SPIFlash_Open(SPI0, SPI_SS0, SPI0_CLOCK, &g_sSpiFlash );
// Make SPI flash leave power down mode if some where or some time had made it entring power down mode
SPIFlash_PowerDown(&g_sSpiFlash, FALSE);
// Check SPI flash is ready for accessing
u32Count = ui32Temp = 0;
while(u32Count!=100)
{
SPIFlash_Read(&g_sSpiFlash, 0, (PUINT8) &ui16Temp, 2);
if ( ui32Temp != (UINT32)ui16Temp )
{
ui32Temp = (UINT32)ui16Temp;
u32Count = 0;
}
else
u32Count++;
}
// The following code can be remove to save code if the flash size is not necessary for this application
SPIFlash_GetChipInfo(&g_sSpiFlash);
if (g_sSpiFlash.u32FlashSize == 0)
return 0;
// The above code can be remove to save code if the flash size is not necessary for this application
return 1;
}
void dma_init(void)
{
if (dma_inited) {
return;
}
dma_inited = 1;
dma_chn_mask = 0;
memset(dma_chn_arr, 0x00, sizeof (dma_chn_arr));
// Reset this module
SYS_ResetModule(dma_modinit.rsetidx);
// Enable IP clock
CLK_EnableModuleClock(dma_modinit.clkidx);
PDMA_Open(0);
NVIC_SetVector(dma_modinit.irq_n, (uint32_t) dma_modinit.var);
NVIC_EnableIRQ(dma_modinit.irq_n);
}
/*---------------------------------------------------------------------------------------------------------*/
int32_t main(void)
{
/* Unlock protected registers */
SYS_UnlockReg();
/* Init System, IP clock and multi-function I/O */
SYS_Init();
/* Lock protected registers */
SYS_LockReg();
/* Init UART0 for printf */
UART0_Init();
/*---------------------------------------------------------------------------------------------------------*/
/* SAMPLE CODE */
/*---------------------------------------------------------------------------------------------------------*/
printf("\nSystem clock rate: %d Hz", SystemCoreClock);
/* EADC function test */
EADC_FunctionTest();
/* Reset EADC module */
SYS_ResetModule(EADC_RST);
/* Disable EADC IP clock */
CLK_DisableModuleClock(EADC_MODULE);
/* Disable External Interrupt */
NVIC_DisableIRQ(ADC00_IRQn);
printf("Exit EADC sample code\n");
while(1);
}
