/**
* FchInitEnvProgramSataPciRegs - Sata Pci Configuration Space
* register setting
*
*
* @param[in] FchDataPtr Fch configuration structure pointer.
*
*/
VOID
FchInitEnvProgramSataPciRegs (
IN VOID *FchDataPtr
)
{
UINT8 *PortRegByte;
UINT16 *PortRegWord;
FCH_DATA_BLOCK *LocalCfgPtr;
AMD_CONFIG_PARAMS *StdHeader;
LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr;
StdHeader = LocalCfgPtr->StdHeader;
//
//Caculate SataPortReg for SATA_ESP_PORT
//
PortRegByte = &(LocalCfgPtr->Sata.SataEspPort.SataPortReg);
FchSataCombineControlDataByte (PortRegByte);
PortRegByte = &(LocalCfgPtr->Sata.SataPortPower.SataPortReg);
FchSataCombineControlDataByte (PortRegByte);
PortRegWord = &(LocalCfgPtr->Sata.SataPortMd.SataPortMode);
FchSataCombineControlDataWord (PortRegWord);
PortRegByte = &(LocalCfgPtr->Sata.SataHotRemovalEnhPort.SataPortReg);
FchSataCombineControlDataByte (PortRegByte);
//
// Set Sata PCI Configuration Space Write enable
//
SataEnableWriteAccess (StdHeader);
// *
// Enables the SATA watchdog timer register prior to the SATA BIOS post
//
RwPci (((SATA_BUS_DEV_FUN << 16) + 0x44), AccessWidth8, 0xff, BIT0, StdHeader);
// *
// SATA PCI Watchdog timer setting
// Set timer out to 0x20 to fix IDE to SATA Bridge dropping drive issue.
//
RwPci (((SATA_BUS_DEV_FUN << 16) + 0x44 + 2), AccessWidth8, 0, 0x20, StdHeader);
//
// BIT4: Enable fast boot (SpeedupXPBoot)
//
RwPci (((SATA_BUS_DEV_FUN << 16) + 0x040), AccessWidth8, 0xef, 0, StdHeader);
RwPci (((SATA_BUS_DEV_FUN << 16) + 0x48 + 3), AccessWidth8, 0xff, BIT7, StdHeader);
//
// Unused SATA Ports Disabled
//
RwPci (((SATA_BUS_DEV_FUN << 16) + 0x040 + 2), AccessWidth8, 0, LocalCfgPtr->Sata.SataPortPower.SataPortReg, StdHeader);
RwPci (((SATA_BUS_DEV_FUN << 16) + 0x084), AccessWidth32, (UINT32) (~ (0x01 << 31)), (UINT32) (0x00 << 31), StdHeader);
}
/**
* FchInitLateSata - Prepare SATA controller to boot to OS.
*
*
* @param[in] FchDataPtr Fch configuration structure pointer.
*
*/
VOID
FchInitLateSata (
IN VOID *FchDataPtr
)
{
UINT8 SataPciCommandByte;
FCH_DATA_BLOCK *LocalCfgPtr;
AMD_CONFIG_PARAMS *StdHeader;
LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr;
StdHeader = LocalCfgPtr->StdHeader;
//
//Return immediately is sata controller is not enabled
//
if ( LocalCfgPtr->Sata.SataMode.SataEnable == 0 ) {
return;
}
//
// Set Sata PCI Configuration Space Write enable
//
SataEnableWriteAccess (StdHeader);
//
// Set Sata Controller Memory & IO access enable
//
ReadPci (((SATA_BUS_DEV_FUN << 16) + 0x04), AccessWidth8, &SataPciCommandByte, StdHeader);
RwPci (((SATA_BUS_DEV_FUN << 16) + 0x04), AccessWidth8, 0xFF, 0x03, StdHeader);
//
// Call Sub-function for each Sata mode
//
if (( LocalCfgPtr->Sata.SataClass == SataAhci7804) || (LocalCfgPtr->Sata.SataClass == SataAhci )) {
FchInitLateSataAhci ( LocalCfgPtr );
}
if (( LocalCfgPtr->Sata.SataClass == SataIde2Ahci) || (LocalCfgPtr->Sata.SataClass == SataIde2Ahci7804 )) {
FchInitLateSataIde2Ahci ( LocalCfgPtr );
}
if (( LocalCfgPtr->Sata.SataClass == SataNativeIde) || (LocalCfgPtr->Sata.SataClass == SataLegacyIde )) {
FchInitLateSataIde ( LocalCfgPtr );
}
if ( LocalCfgPtr->Sata.SataClass == SataRaid) {
FchInitLateSataRaid ( LocalCfgPtr );
}
FchInitLateProgramSataRegs ( LocalCfgPtr );
//
// Restore Sata Controller Memory & IO access status
//
WritePci (((SATA_BUS_DEV_FUN << 16) + 0x04), AccessWidth8, &SataPciCommandByte, StdHeader);
//
// Set Sata PCI Configuration Space Write disable
//
SataDisableWriteAccess (StdHeader);
}
/**
* FchInitEnvProgramSataPciRegs - Sata Pci Configuration Space
* register setting
*
*
* @param[in] FchDataPtr Fch configuration structure pointer.
*
*/
VOID
FchInitEnvProgramSataPciRegs (
IN VOID *FchDataPtr
)
{
UINT8 *PortRegByte;
UINT16 *PortRegWord;
FCH_DATA_BLOCK *LocalCfgPtr;
AMD_CONFIG_PARAMS *StdHeader;
LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr;
StdHeader = LocalCfgPtr->StdHeader;
//
//Caculate SataPortReg for SATA_ESP_PORT
//
PortRegByte = &(LocalCfgPtr->Sata.SataEspPort.SataPortReg);
FchSataCombineControlDataByte (PortRegByte);
PortRegByte = &(LocalCfgPtr->Sata.SataPortPower.SataPortReg);
FchSataCombineControlDataByte (PortRegByte);
PortRegWord = &(LocalCfgPtr->Sata.SataPortMd.SataPortMode);
FchSataCombineControlDataWord (PortRegWord);
PortRegByte = &(LocalCfgPtr->Sata.SataHotRemovalEnhPort.SataPortReg);
FchSataCombineControlDataByte (PortRegByte);
//
// Reset DevSlp S5 Pin here
//
if (LocalCfgPtr->Sata.SataDevSlpPort0) {
if (LocalCfgPtr->FchRunTime.SataDevSlpPort0S5Pin) {
ACPIMMIO32 (ACPI_MMIO_BASE + GPIO_BANK0_BASE + (LocalCfgPtr->FchRunTime.SataDevSlpPort0S5Pin << 2)) |= BIT22 + BIT23;
}
ACPIMMIO32 (ACPI_MMIO_BASE + GPIO_BANK0_BASE + FCH_GPIO_10C_GPIO55_AGPI067) &= ~ BIT22;
ACPIMMIO32 (ACPI_MMIO_BASE + GPIO_BANK0_BASE + FCH_GPIO_10C_GPIO55_AGPI067) |= BIT23;
}
if (LocalCfgPtr->Sata.SataDevSlpPort1) {
if (LocalCfgPtr->FchRunTime.SataDevSlpPort1S5Pin) {
ACPIMMIO32 (ACPI_MMIO_BASE + GPIO_BANK0_BASE + (LocalCfgPtr->FchRunTime.SataDevSlpPort1S5Pin << 2)) |= BIT22 + BIT23;
}
ACPIMMIO32 (ACPI_MMIO_BASE + GPIO_BANK0_BASE + FCH_GPIO_118_GPIO59_AGPI070) &= ~ BIT22;
ACPIMMIO32 (ACPI_MMIO_BASE + GPIO_BANK0_BASE + FCH_GPIO_118_GPIO59_AGPI070) |= BIT23;
}
//
// Set Sata PCI Configuration Space Write enable
//
SataEnableWriteAccess (StdHeader);
// *
// Enables the SATA watchdog timer register prior to the SATA BIOS post
//
RwPci (((SATA_BUS_DEV_FUN << 16) + FCH_SATA_REG44), AccessWidth8, 0xff, BIT0, StdHeader);
// *
// SATA PCI Watchdog timer setting
// Set timer out to 0x20 to fix IDE to SATA Bridge dropping drive issue.
//
RwPci (((SATA_BUS_DEV_FUN << 16) + FCH_SATA_REG44 + 2), AccessWidth8, 0, 0x20, StdHeader);
//
// BIT4: Enable fast boot (SpeedupXPBoot)
//
RwPci (((SATA_BUS_DEV_FUN << 16) + FCH_SATA_REG40), AccessWidth8, 0xef, 0, StdHeader);
//
// HBA Initialization setting
//
RwPci (((SATA_BUS_DEV_FUN << 16) + FCH_SATA_REG48 + 3), AccessWidth8, 0xff, BIT7, StdHeader);
//
// Unused SATA Ports Disabled
//
RwPci (((SATA_BUS_DEV_FUN << 16) + FCH_SATA_REG40 + 2), AccessWidth8, 0, LocalCfgPtr->Sata.SataPortPower.SataPortReg, StdHeader);
//
// Disable Prefetch In Ahci Mode
//
RwPci (((SATA_BUS_DEV_FUN << 16) + FCH_SATA_REG40 + 1), AccessWidth8, 0xDF, BIT5, StdHeader);
RwPci (((SATA_BUS_DEV_FUN << 16) + FCH_SATA_REG84), AccessWidth32, (UINT32) (~ (0x01 << 31)), (UINT32) (0x00 << 31), StdHeader);
RwPci (((SATA_BUS_DEV_FUN << 16) + FCH_SATA_REG40), AccessWidth32, (UINT32) (~ (0x3 << 1)), (UINT32) (0x01 << 1), StdHeader);
RwPci (((SATA_BUS_DEV_FUN << 16) + FCH_SATA_REG48), AccessWidth32, (UINT32) (~ (0x1 << 3)), (UINT32) (0x01 << 3), StdHeader);
}
