示例#1
0
/**
 *  @brief  Main program entry point
 *  @return Will never return
 *  @note   This routine contains the overall program flow, including initial
 *  setup of all components and the main program loop.
 */
int main(void)
{
	SetupHardware();
	iap_init();

#ifdef WITH_USB	

	xprintf("\nLet's see some usb stuff");
	
	int i;
	// initially expect USB connection
	for (i = 0; ; i++) {
		#if !defined(USB_DEVICE_ROM_DRIVER)
		MS_Device_USBTask(&Disk_MS_Interface);
		USB_USBTask(Disk_MS_Interface.Config.PortNumber, USB_MODE_Device);
		#endif
		//if (i > 350000 && !USBConnected) break;
		if (i > 600000 && !USBConnected) break;
	}
#endif
	// if USB is unplugged, serve the vectrex bus
	PrepareLoader(DataRam_GetScratchRAM());

	xprintf("\nLOADER.BIN ROMBase=%x\n", ROMBase);
	void *loader = ROMBase;
	SelectROM(DataRam_GetScratchRAM(), 1); 
	xprintf("1 ROMBase=%x\nServing...", ROMBase);
	ROMBase = loader;

    NVIC_DisableIRQ(UART0_IRQn);
	UART0_UnInit();		
	VectrexBusInit();


	//SelectROM(DataRam_GetScratchRAM(), 1); -- this works
	int romIndex = VectrexBusSlave();	
	//VectrexBusHold();

	SelectROM(DataRam_GetScratchRAM(), romIndex); 

	//VectrexBusUnhold();
	//VectrexNMI();
	for(;;)
		VectrexBusSlave();
}
示例#2
0
文件: Clio.cpp 项目: fixelsan/freedo
int __fastcall _clio_Poke(unsigned int addr, unsigned int val)
{
	int base;
	int i;

        //if(addr==0x200 || addr==0x204 || addr==0x208 || addr==0x20c || (addr>=0x100 && addr<=0x17c) || addr==0x220)io_interface(EXT_DEBUG_PRINT,(void*)str.print("CLIO Write[0x%X] = 0x%8.8X",addr,val).CStr());
        //if(addr==0x34 || addr==0x30)io_interface(EXT_DEBUG_PRINT,(void*)str.print("CLIO Write[0x%X] = 0x%8.8X",addr,val).CStr());
	if( (addr& ~0x2C) == 0x40 ) // 0x40..0x4C, 0x60..0x6C case
	{
		if(addr==0x40)
		{
			cregs[0x40]|=val;
			if(cregs[0x60]) cregs[0x40]|=0x80000000;
			//if(cregs[0x40]&cregs[0x48]) _arm_SetFIQ();
			return 0;
		}
		else if(addr==0x44)
		{
			cregs[0x40]&=~val;
			if(!cregs[0x60]) cregs[0x40]&=~0x80000000;
			return 0;
		}
		else if(addr==0x48)
		{
			cregs[0x48]|=val;
			//if(cregs[0x40]&cregs[0x48]) _arm_SetFIQ();
			return 0;
		}
		else if(addr==0x4c)
		{
			cregs[0x48]&=~val;
			cregs[0x48]|=0x80000000; // always one for irq31
			return 0;
		}
                /*else if(addr==0x50)
		{
			cregs[0x50]|=val&0x3fff0000;
			return 0;
		}
		else if(addr==0x54)
		{
			cregs[0x50]&=~val;
			return 0;
		} */
		else if(addr==0x60)
		{
			cregs[0x60]|=val;
			if(cregs[0x60]) cregs[0x40]|=0x80000000;
			//if(cregs[0x60]&cregs[0x68])	_arm_SetFIQ();
			return 0;
		}
		else if(addr==0x64)
		{
			cregs[0x60]&=~val;
			if(!cregs[0x60]) cregs[0x40]&=~0x80000000;
			return 0;
		}
		else if(addr==0x68)
		{
			cregs[0x68]|=val;
			//if(cregs[0x60]&cregs[0x68]) _arm_SetFIQ();
			return 0;
		}
		else if(addr==0x6c)
		{
			cregs[0x68]&=~val;
			return 0;
		}
	}
	else if(addr==0x84)
	{
		//temp=val&0xf0;
		//temp=temp>>4;
		//val&=0x0f;

		//cregs[0x84]&=~temp;
		//cregs[0x84]|=val;
		cregs[0x84]=val&0xf;
		SelectROM((val&4)? 1:0 );
		return 0;
	}else if(addr==0x300)
	{	//clear down the fifos and stop them
		base=0;
		cregs[0x304]&=~val;

		for(i=0;i<13;i++)
		{
			if(val&(1<<i))
			{
				base=0x400+(i<<4);
				RLDADR=CURADR=0;
				RLDLEN=CURLEN=0;
				_clio_SetFIFO(base,0);
				_clio_SetFIFO(base+4,0);
				_clio_SetFIFO(base+8,0);
				_clio_SetFIFO(base+0xc,0);
				val&=~(1<<i);
				PTRI[i]=0;
			}

		}
		{
			for(i=0;i<4;i++)
			{
				if(val&(1<<(i+16)))
				{
					base=0x500+(i<<4);
					RLDADR=CURADR=0;
					RLDLEN=CURLEN=0;
					_clio_SetFIFO(base,0);
					_clio_SetFIFO(base+4,0);
					_clio_SetFIFO(base+8,0);
					_clio_SetFIFO(base+0xc,0);

					val&=~(1<<(i+16));
					PTRO[i]=0;

				}

			}

		}

		return 0;

	}
	else if(addr==0x304) // Dma Starter!!!!! P/A !!!! need to create Handler.
	{

		//if(val&0x00100000)
		//{
			HandleDMA(val);
		//	cregs[0x304]&=~0x00100000;
		//}
		return 0;
	}
	else if(addr==0x308) //Dma Stopper!!!!
	{
		cregs[0x304]&=~val;
		return 0;
	}
	else if(addr==0x400) //XBUS direction
	{
		if(val&0x800)
			return 0;
		else
		{
			cregs[0x400]=val;
			return 0;
		}
	}
	else if((addr>=0x500) && (addr<0x540))
	{
		_xbus_SetSEL(val);

		return 0;
	}
	else if((addr>=0x540) && (addr<0x580))
	{
#ifdef DBGXBUS
		sprintf(str,"XBPC : 0x%8.8x :",RegRead(15));
		CDebug::DPrint(str);
#endif
		_xbus_SetPoll(val);
		return 0;
	}
	else if((addr>=0x580) && (addr<0x5c0))
	{
		_xbus_SetCommandFIFO(val); // on FIFO Filled execute the command
		return 0;
	}
        else if((addr>=0x5c0) && (addr<0x600))
	{
		_xbus_SetDataFIFO(val); // on FIFO Filled execute the command
		return 0;
	}
	else if(addr==0x28)
	{
		cregs[addr]=val;
		if(val==0x30)
			return 1;
		else
			return 0;
	}else if((addr>=0x1800)&&(addr<=0x1fff))//0x0340 1800 … 0x0340 1BFF && 0x0340 1C00 … 0x0340 1FFF
	{
		addr&=~0x400; //mirrors
		DSPW1=val>>16;
		DSPW2=val&0xffff;
		DSPA=(addr-0x1800)>>1;
		//sprintf(str,"0x%8.8X : 2x1NWRITE 0x%3.3X 0x%4.4X\n",GetPC(),DSPA,DSPW1);
		//CDebug::DPrint(str);
		//sprintf(str,"0x%8.8X : 2x2NWRITE 0x%3.3X 0x%4.4X\n",GetPC(),DSPA+1,DSPW2);
		//CDebug::DPrint(str);


		_dsp_WriteMemory(DSPA,DSPW1);
		_dsp_WriteMemory(DSPA+1,DSPW2);
		return 0;
		//DSPNRAMWrite 2 DSPW per 1ARMW
	}else if((addr>=0x2000)&&(addr<=0x2fff))