void SetCRAM_4K_Bank( BYTE page, INT bank )
{
SetCRAM_1K_Bank( page+0, bank*4+0 );
SetCRAM_1K_Bank( page+1, bank*4+1 );
SetCRAM_1K_Bank( page+2, bank*4+2 );
SetCRAM_1K_Bank( page+3, bank*4+3 );
}
void Mapper074::SetBank_PPUSUB( int bank, int page )
{
if( !patch && (page == 8 || page == 9) ) {
SetCRAM_1K_Bank( bank, page & 7 );
} else if( patch == 1 && page >= 128 ) {
SetCRAM_1K_Bank( bank, page & 7 );
} else {
SetVROM_1K_Bank( bank, page );
}
}
void Mapper004::SetBank_PPU()
{
if( VROM_1K_SIZE ) {
if( reg[0] & 0x80 ) {
SetVROM_8K_Bank( chr4, chr5, chr6, chr7,
chr01, chr01+1, chr23, chr23+1 );
} else {
SetVROM_8K_Bank( chr01, chr01+1, chr23, chr23+1,
chr4, chr5, chr6, chr7 );
}
} else {
if( reg[0] & 0x80 ) {
SetCRAM_1K_Bank( 4, (chr01+0)&0x07 );
SetCRAM_1K_Bank( 5, (chr01+1)&0x07 );
SetCRAM_1K_Bank( 6, (chr23+0)&0x07 );
SetCRAM_1K_Bank( 7, (chr23+1)&0x07 );
SetCRAM_1K_Bank( 0, chr4&0x07 );
SetCRAM_1K_Bank( 1, chr5&0x07 );
SetCRAM_1K_Bank( 2, chr6&0x07 );
SetCRAM_1K_Bank( 3, chr7&0x07 );
} else {
SetCRAM_1K_Bank( 0, (chr01+0)&0x07 );
SetCRAM_1K_Bank( 1, (chr01+1)&0x07 );
SetCRAM_1K_Bank( 2, (chr23+0)&0x07 );
SetCRAM_1K_Bank( 3, (chr23+1)&0x07 );
SetCRAM_1K_Bank( 4, chr4&0x07 );
SetCRAM_1K_Bank( 5, chr5&0x07 );
SetCRAM_1K_Bank( 6, chr6&0x07 );
SetCRAM_1K_Bank( 7, chr7&0x07 );
}
}
}
void Mapper119::SetBank_PPU()
{
if( reg[0]&0x80 ) {
if( chr4&0x40 ) SetCRAM_1K_Bank( 0, chr4&0x07 );
else SetVROM_1K_Bank( 0, chr4 );
if( chr5&0x40 ) SetCRAM_1K_Bank( 1, chr5&0x07 );
else SetVROM_1K_Bank( 1, chr5 );
if( chr6&0x40 ) SetCRAM_1K_Bank( 2, chr6&0x07 );
else SetVROM_1K_Bank( 2, chr6 );
if( chr7&0x40 ) SetCRAM_1K_Bank( 3, chr7&0x07 );
else SetVROM_1K_Bank( 3, chr7 );
if( (chr01+0)&0x40 ) SetCRAM_1K_Bank( 4, (chr01+0)&0x07 );
else SetVROM_1K_Bank( 4, (chr01+0) );
if( (chr01+1)&0x40 ) SetCRAM_1K_Bank( 5, (chr01+1)&0x07 );
else SetVROM_1K_Bank( 5, (chr01+1) );
if( (chr23+0)&0x40 ) SetCRAM_1K_Bank( 6, (chr23+0)&0x07 );
else SetVROM_1K_Bank( 6, (chr23+0) );
if( (chr23+1)&0x40 ) SetCRAM_1K_Bank( 7, (chr23+1)&0x07 );
else SetVROM_1K_Bank( 7, (chr23+1) );
} else {
if( (chr01+0)&0x40 ) SetCRAM_1K_Bank( 0, (chr01+0)&0x07 );
else SetVROM_1K_Bank( 0, (chr01+0) );
if( (chr01+1)&0x40 ) SetCRAM_1K_Bank( 1, (chr01+1)&0x07 );
else SetVROM_1K_Bank( 1, (chr01+1) );
if( (chr23+0)&0x40 ) SetCRAM_1K_Bank( 2, (chr23+0)&0x07 );
else SetVROM_1K_Bank( 2, (chr23+0) );
if( (chr23+1)&0x40 ) SetCRAM_1K_Bank( 3, (chr23+1)&0x07 );
else SetVROM_1K_Bank( 3, (chr23+1) );
if( chr4&0x40 ) SetCRAM_1K_Bank( 4, chr4&0x07 );
else SetVROM_1K_Bank( 4, chr4 );
if( chr5&0x40 ) SetCRAM_1K_Bank( 5, chr5&0x07 );
else SetVROM_1K_Bank( 5, chr5 );
if( chr6&0x40 ) SetCRAM_1K_Bank( 6, chr6&0x07 );
else SetVROM_1K_Bank( 6, chr6 );
if( chr7&0x40 ) SetCRAM_1K_Bank( 7, chr7&0x07 );
else SetVROM_1K_Bank( 7, chr7 );
}
}
void Mapper019::Write( WORD addr, BYTE data )
{
//if( addr >= 0xC000 ) {
//DEBUGOUT( "W %04X %02X L:%3d\n", addr, data, nes->GetScanline() );
//}
switch( addr & 0xF800 ) {
case 0x8000:
if( (data < 0xE0) || (reg[0] != 0) ) {
SetVROM_1K_Bank( 0, data );
} else {
SetCRAM_1K_Bank( 0, data&0x1F );
}
break;
case 0x8800:
if( (data < 0xE0) || (reg[0] != 0) ) {
SetVROM_1K_Bank( 1, data );
} else {
SetCRAM_1K_Bank( 1, data&0x1F );
}
break;
case 0x9000:
if( (data < 0xE0) || (reg[0] != 0) ) {
SetVROM_1K_Bank( 2, data );
} else {
SetCRAM_1K_Bank( 2, data&0x1F );
}
break;
case 0x9800:
if( (data < 0xE0) || (reg[0] != 0) ) {
SetVROM_1K_Bank( 3, data );
} else {
SetCRAM_1K_Bank( 3, data&0x1F );
}
break;
case 0xA000:
if( (data < 0xE0) || (reg[1] != 0) ) {
SetVROM_1K_Bank( 4, data );
} else {
SetCRAM_1K_Bank( 4, data&0x1F );
}
break;
case 0xA800:
if( (data < 0xE0) || (reg[1] != 0) ) {
SetVROM_1K_Bank( 5, data );
} else {
SetCRAM_1K_Bank( 5, data&0x1F );
}
break;
case 0xB000:
if( (data < 0xE0) || (reg[1] != 0) ) {
SetVROM_1K_Bank( 6, data );
} else {
SetCRAM_1K_Bank( 6, data&0x1F );
}
break;
case 0xB800:
if( (data < 0xE0) || (reg[1] != 0) ) {
SetVROM_1K_Bank( 7, data );
} else {
SetCRAM_1K_Bank( 7, data&0x1F );
}
break;
case 0xC000:
if( !patch ) {
if( data <= 0xDF ) {
SetVROM_1K_Bank( 8, data );
} else {
SetVRAM_1K_Bank( 8, data & 0x01 );
}
}
break;
case 0xC800:
if( !patch ) {
if( data <= 0xDF ) {
SetVROM_1K_Bank( 9, data );
} else {
SetVRAM_1K_Bank( 9, data & 0x01 );
}
}
break;
case 0xD000:
if( !patch ) {
if( data <= 0xDF ) {
SetVROM_1K_Bank( 10, data );
} else {
SetVRAM_1K_Bank( 10, data & 0x01 );
}
}
break;
case 0xD800:
if( !patch ) {
if( data <= 0xDF ) {
SetVROM_1K_Bank( 11, data );
} else {
SetVRAM_1K_Bank( 11, data & 0x01 );
}
}
break;
case 0xE000:
SetPROM_8K_Bank( 4, data & 0x3F );
if( patch == 2 ) {
if( data & 0x40 ) SetVRAM_Mirror( VRAM_VMIRROR );
else SetVRAM_Mirror( VRAM_MIRROR4L );
}
if( patch == 3 ) {
if( data & 0x80 ) SetVRAM_Mirror( VRAM_HMIRROR );
else SetVRAM_Mirror( VRAM_VMIRROR );
}
break;
case 0xE800:
reg[0] = data & 0x40;
reg[1] = data & 0x80;
SetPROM_8K_Bank( 5, data & 0x3F );
break;
case 0xF000:
SetPROM_8K_Bank( 6, data & 0x3F );
break;
case 0xF800:
if( addr == 0xF800 ) {
if( exsound_enable ) {
nes->apu->ExWrite( addr, data );
}
reg[2] = data;
}
break;
}
}
void SetCRAM_8K_Bank( INT bank )
{
for( INT i = 0; i < 8; i++ ) {
SetCRAM_1K_Bank( i, bank*8+i ); // fix
}
}
void SetCRAM_2K_Bank( BYTE page, INT bank )
{
SetCRAM_1K_Bank( page+0, bank*2+0 );
SetCRAM_1K_Bank( page+1, bank*2+1 );
}
