static void StartAudioCaptureHardware(struct snd_pcm_substream *substream)
{
printk("StartAudioCaptureHardware \n");
ConfigAdcI2S(substream);
SetI2SAdcIn(mAudioDigitalI2S);
//EnableSideGenHw(Soc_Aud_InterConnectionOutput_O09,Soc_Aud_MemIF_Direction_DIRECTION_OUTPUT,true);
SetMemIfFetchFormatPerSample(Soc_Aud_Digital_Block_MEM_VUL, AFE_WLEN_16_BIT);
SetMemIfFetchFormatPerSample(Soc_Aud_Digital_Block_MEM_VUL, AFE_WLEN_16_BIT);
SetoutputConnectionFormat(OUTPUT_DATA_FORMAT_16BIT, Soc_Aud_InterConnectionOutput_O09);
SetoutputConnectionFormat(OUTPUT_DATA_FORMAT_16BIT, Soc_Aud_InterConnectionOutput_O10);
SetI2SAdcEnable(true);
// here to set interrupt
SetIrqMcuCounter(Soc_Aud_IRQ_MCU_MODE_IRQ2_MCU_MODE, substream->runtime->period_size);
SetIrqMcuSampleRate(Soc_Aud_IRQ_MCU_MODE_IRQ2_MCU_MODE, substream->runtime->rate);
SetIrqEnable(Soc_Aud_IRQ_MCU_MODE_IRQ2_MCU_MODE, true);
SetSampleRate(Soc_Aud_Digital_Block_MEM_VUL, substream->runtime->rate);
SetMemoryPathEnable(Soc_Aud_Digital_Block_MEM_VUL, true);
SetConnection(Soc_Aud_InterCon_Connection, Soc_Aud_InterConnectionInput_I03, Soc_Aud_InterConnectionOutput_O09);
SetConnection(Soc_Aud_InterCon_Connection, Soc_Aud_InterConnectionInput_I04, Soc_Aud_InterConnectionOutput_O10);
SetConnection(Soc_Aud_InterCon_Connection, Soc_Aud_InterConnectionInput_I05, Soc_Aud_InterConnectionOutput_O09);
SetConnection(Soc_Aud_InterCon_Connection, Soc_Aud_InterConnectionInput_I06, Soc_Aud_InterConnectionOutput_O10);
EnableAfe(true);
}
static int mtk_voice1_extint_prepare(struct snd_pcm_substream *substream)
{
struct snd_pcm_runtime *runtimeStream = substream->runtime;
printk("%s rate = %d channels = %d period_size = %lu\n", __func__,
runtimeStream->rate, runtimeStream->channels, runtimeStream->period_size);
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
{
SetConnection(Soc_Aud_InterCon_Connection, Soc_Aud_InterConnectionInput_I14, Soc_Aud_InterConnectionOutput_O03);
SetConnection(Soc_Aud_InterCon_Connection, Soc_Aud_InterConnectionInput_I14, Soc_Aud_InterConnectionOutput_O04);
// start I2S DAC out
SetI2SDacOut(substream->runtime->rate);
SetMemoryPathEnable(Soc_Aud_Digital_Block_I2S_OUT_DAC, true);
SetI2SDacEnable(true);
EnableAfe(true);
printk("%s with SNDRV_PCM_STREAM_PLAYBACK \n",__func__);
}
else if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
{
SetConnection(Soc_Aud_InterCon_Connection, Soc_Aud_InterConnectionInput_I03, Soc_Aud_InterConnectionOutput_O17);
SetConnection(Soc_Aud_InterCon_Connection, Soc_Aud_InterConnectionInput_I04, Soc_Aud_InterConnectionOutput_O18);
ConfigAdcI2S(substream);
SetI2SAdcIn(&mAudioDigitalI2S);
SetMemoryPathEnable(Soc_Aud_Digital_Block_I2S_IN_ADC, true);
SetI2SAdcEnable(true);
EnableAfe(true);
printk("%s with SNDRV_PCM_STREAM_CAPTURE \n",__func__);
}
// here start digital part
if(Voice_ExtInt_Status == 0)
{
SetConnection(Soc_Aud_InterCon_Connection, Soc_Aud_InterConnectionInput_I21, Soc_Aud_InterConnectionOutput_O07);
SetConnection(Soc_Aud_InterCon_Connection, Soc_Aud_InterConnectionInput_I21, Soc_Aud_InterConnectionOutput_O08);
SetConnection(Soc_Aud_InterCon_Connection, Soc_Aud_InterConnectionInput_I09, Soc_Aud_InterConnectionOutput_O25);
VoiceExtIntPcm_Ext.mPcmModeWidebandSel = (runtimeStream->rate == 8000) ? Soc_Aud_PCM_MODE_PCM_MODE_8K : Soc_Aud_PCM_MODE_PCM_MODE_16K;
VoiceExtIntPcm_Int.mPcmModeWidebandSel = (runtimeStream->rate == 8000) ? Soc_Aud_PCM_MODE_PCM_MODE_8K : Soc_Aud_PCM_MODE_PCM_MODE_16K;
//VoiceExtPcm.mAsyncFifoSel = Soc_Aud_BYPASS_SRC_SLAVE_USE_ASYNC_FIFO;
SetModemPcmConfig(MODEM_EXTERNAL, VoiceExtIntPcm_Ext);
SetModemPcmEnable(MODEM_EXTERNAL, true);
SetModemPcmConfig(MODEM_1, VoiceExtIntPcm_Int);
SetModemPcmEnable(MODEM_1, true);
}
if(substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
{
Voice_ExtInt_Status |= VOICE_DL_ON;
}
else if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
{
Voice_ExtInt_Status |= VOICE_UL_ON;
}
SetExternalModemStatus(true);
return 0;
}
static int mtk_voice1_prepare(struct snd_pcm_substream *substream)
{
struct snd_pcm_runtime *runtimeStream = substream->runtime;
pr_warn("mtk_voice1_prepare rate = %d channels = %d period_size = %lu\n",
runtimeStream->rate, runtimeStream->channels, runtimeStream->period_size);
if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
pr_warn("%s with SNDRV_PCM_STREAM_CAPTURE\n", __func__);
return 0;
}
/* here start digital part */
SetConnection(Soc_Aud_InterCon_Connection, Soc_Aud_InterConnectionInput_I03,
Soc_Aud_InterConnectionOutput_O17);
SetConnection(Soc_Aud_InterCon_Connection, Soc_Aud_InterConnectionInput_I04,
Soc_Aud_InterConnectionOutput_O18);
SetConnection(Soc_Aud_InterCon_Connection, Soc_Aud_InterConnectionInput_I14,
Soc_Aud_InterConnectionOutput_O03);
SetConnection(Soc_Aud_InterCon_Connection, Soc_Aud_InterConnectionInput_I14,
Soc_Aud_InterConnectionOutput_O04);
/* start I2S DAC out */
SetI2SDacOut(substream->runtime->rate, false, Soc_Aud_I2S_WLEN_WLEN_16BITS);
SetMemoryPathEnable(Soc_Aud_Digital_Block_I2S_OUT_DAC, true);
ConfigAdcI2S(substream);
SetI2SAdcIn(&mAudioDigitalI2S);
SetI2SDacEnable(true);
#ifdef PMIC_RESET_WORKAROUND
pr_warn("%s ,PMIC_RESET_WORKAROUND reset ABB_AFE_CON2/ABB_AFE_CON4\n", __func__);
Ana_Set_Reg(ABB_AFE_CON2, 0x0, 0xffff); /* reset to default value */
Ana_Set_Reg(ABB_AFE_CON4, 0x0, 0xffff); /* reset to default value */
#endif
SetMemoryPathEnable(Soc_Aud_Digital_Block_I2S_IN_ADC, true);
SetI2SAdcEnable(true);
EnableAfe(true);
Voice1Pcm.mPcmModeWidebandSel = (runtimeStream->rate == 8000) ?
Soc_Aud_PCM_MODE_PCM_MODE_8K : Soc_Aud_PCM_MODE_PCM_MODE_16K;
Voice1Pcm.mAsyncFifoSel = Soc_Aud_BYPASS_SRC_SLAVE_USE_ASYNC_FIFO;
SetModemPcmConfig(MODEM_1, Voice1Pcm);
SetModemPcmEnable(MODEM_1, true);
Voice_Status = true;
return 0;
}
static void StartAudioCaptureHardware(struct snd_pcm_substream *substream)
{
printk("StartAudioCaptureHardware \n");
ConfigAdcI2S(substream);
SetI2SAdcIn(mAudioDigitalI2S);
SetMemIfFetchFormatPerSample(Soc_Aud_Digital_Block_MEM_VUL, AFE_WLEN_16_BIT);
SetMemIfFetchFormatPerSample(Soc_Aud_Digital_Block_MEM_VUL, AFE_WLEN_16_BIT);
SetoutputConnectionFormat(OUTPUT_DATA_FORMAT_16BIT, Soc_Aud_InterConnectionOutput_O09);
SetoutputConnectionFormat(OUTPUT_DATA_FORMAT_16BIT, Soc_Aud_InterConnectionOutput_O10);
if (GetMemoryPathEnable(Soc_Aud_Digital_Block_I2S_IN_ADC) == false)
{
SetMemoryPathEnable(Soc_Aud_Digital_Block_I2S_IN_ADC, true);
SetI2SAdcEnable(true);
}
else
{
SetMemoryPathEnable(Soc_Aud_Digital_Block_I2S_IN_ADC, true);
}
SetConnection(Soc_Aud_InterCon_Connection, Soc_Aud_InterConnectionInput_I03, Soc_Aud_InterConnectionOutput_O09);
SetConnection(Soc_Aud_InterCon_Connection, Soc_Aud_InterConnectionInput_I04, Soc_Aud_InterConnectionOutput_O10);
if (substream->runtime->format == SNDRV_PCM_FORMAT_S32_LE || substream->runtime->format == SNDRV_PCM_FORMAT_U32_LE)
{
#if 0 //Rainier no 24bit
SetMemIfFetchFormatPerSample(Soc_Aud_Digital_Block_MEM_VUL, AFE_WLEN_32_BIT_ALIGN_8BIT_0_24BIT_DATA);
SetoutputConnectionFormat(OUTPUT_DATA_FORMAT_24BIT, Soc_Aud_InterConnectionOutput_O09);
SetoutputConnectionFormat(OUTPUT_DATA_FORMAT_24BIT, Soc_Aud_InterConnectionOutput_O10);
#endif
}
// here to set interrupt
SetIrqMcuCounter(Soc_Aud_IRQ_MCU_MODE_IRQ2_MCU_MODE, substream->runtime->period_size);
SetIrqMcuSampleRate(Soc_Aud_IRQ_MCU_MODE_IRQ2_MCU_MODE, substream->runtime->rate);
SetIrqEnable(Soc_Aud_IRQ_MCU_MODE_IRQ2_MCU_MODE, true);
SetSampleRate(Soc_Aud_Digital_Block_MEM_VUL, substream->runtime->rate);
SetMemoryPathEnable(Soc_Aud_Digital_Block_MEM_VUL, true);
EnableAfe(true);
}
static int mtk_voice1_prepare(struct snd_pcm_substream *substream)
{
struct snd_pcm_runtime *runtimeStream = substream->runtime;
printk("mtk_alsa_prepare rate = %d channels = %d period_size = %lu\n",
runtimeStream->rate, runtimeStream->channels, runtimeStream->period_size);
if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
{
printk("%s with SNDRV_PCM_STREAM_CAPTURE \n", __func__);
return 0;
}
// here start digital part
SetConnection(Soc_Aud_InterCon_Connection, Soc_Aud_InterConnectionInput_I03, Soc_Aud_InterConnectionOutput_O17);
SetConnection(Soc_Aud_InterCon_Connection, Soc_Aud_InterConnectionInput_I04, Soc_Aud_InterConnectionOutput_O18);
SetConnection(Soc_Aud_InterCon_Connection, Soc_Aud_InterConnectionInput_I14, Soc_Aud_InterConnectionOutput_O03);
SetConnection(Soc_Aud_InterCon_Connection, Soc_Aud_InterConnectionInput_I14, Soc_Aud_InterConnectionOutput_O04);
// start I2S DAC out
SetI2SDacOut(substream->runtime->rate, false, Soc_Aud_I2S_WLEN_WLEN_16BITS);
SetMemoryPathEnable(Soc_Aud_Digital_Block_I2S_OUT_DAC, true);
ConfigAdcI2S(substream);
SetI2SAdcIn(&mAudioDigitalI2S);
SetI2SDacEnable(true);
SetMemoryPathEnable(Soc_Aud_Digital_Block_I2S_IN_ADC, true);
SetI2SAdcEnable(true);
EnableAfe(true);
Voice1Pcm.mPcmModeWidebandSel = (runtimeStream->rate == 8000) ? Soc_Aud_PCM_MODE_PCM_MODE_8K : Soc_Aud_PCM_MODE_PCM_MODE_16K;
Voice1Pcm.mAsyncFifoSel = Soc_Aud_BYPASS_SRC_SLAVE_USE_ASYNC_FIFO;
SetModemPcmConfig(MODEM_1, Voice1Pcm);
SetModemPcmEnable(MODEM_1, true);
Voice_Status = true;
return 0;
}
static int mtk_uldlloopback_pcm_prepare(struct snd_pcm_substream *substream)
{
struct snd_pcm_runtime *runtime = substream->runtime;
//uint32 eSamplingRate = SampleRateTransform(runtime->rate);
//uint32 dVoiceModeSelect = 0;
//uint32 Audio_I2S_Dac = 0;
uint32 u32AudioI2S = 0;
if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
{
printk("%s with mtk_uldlloopback_pcm_prepare \n", __func__);
return 0;
}
printk("%s rate = %d\n", __func__, runtime->rate);
Afe_Set_Reg(AFE_TOP_CON0, 0x00000000, 0xffffffff);
if (runtime->format == SNDRV_PCM_FORMAT_S32_LE || runtime->format == SNDRV_PCM_FORMAT_U32_LE)
{
SetMemIfFetchFormatPerSample(Soc_Aud_Digital_Block_MEM_DL1, AFE_WLEN_32_BIT_ALIGN_8BIT_0_24BIT_DATA);
SetMemIfFetchFormatPerSample(Soc_Aud_Digital_Block_MEM_DL2, AFE_WLEN_32_BIT_ALIGN_8BIT_0_24BIT_DATA);
SetoutputConnectionFormat(OUTPUT_DATA_FORMAT_24BIT, Soc_Aud_InterConnectionOutput_O03);
SetoutputConnectionFormat(OUTPUT_DATA_FORMAT_24BIT, Soc_Aud_InterConnectionOutput_O04);
}
else
{
SetMemIfFetchFormatPerSample(Soc_Aud_Digital_Block_MEM_DL1, AFE_WLEN_16_BIT);
SetMemIfFetchFormatPerSample(Soc_Aud_Digital_Block_MEM_DL2, AFE_WLEN_16_BIT);
SetoutputConnectionFormat(OUTPUT_DATA_FORMAT_16BIT, Soc_Aud_InterConnectionOutput_O03);
SetoutputConnectionFormat(OUTPUT_DATA_FORMAT_16BIT, Soc_Aud_InterConnectionOutput_O04);
}
// interconnection setting
SetConnection(Soc_Aud_InterCon_Connection, Soc_Aud_InterConnectionInput_I03, Soc_Aud_InterConnectionOutput_O00);
SetConnection(Soc_Aud_InterCon_Connection, Soc_Aud_InterConnectionInput_I04, Soc_Aud_InterConnectionOutput_O01);
SetConnection(Soc_Aud_InterCon_Connection, Soc_Aud_InterConnectionInput_I03, Soc_Aud_InterConnectionOutput_O03);
SetConnection(Soc_Aud_InterCon_Connection, Soc_Aud_InterConnectionInput_I04, Soc_Aud_InterConnectionOutput_O04);
Afe_Set_Reg(AFE_ADDA_TOP_CON0, 0, 0x1); //Using Internal ADC
u32AudioI2S |= Soc_Aud_LOW_JITTER_CLOCK << 12 ; //Low jitter mode
u32AudioI2S |= SampleRateTransform(runtime->rate) << 8;
u32AudioI2S |= Soc_Aud_I2S_FORMAT_I2S << 3; // us3 I2s format
u32AudioI2S |= Soc_Aud_I2S_WLEN_WLEN_32BITS << 1; // 32 BITS
printk("u32AudioI2S= 0x%x\n", u32AudioI2S);
Afe_Set_Reg(AFE_I2S_CON3, u32AudioI2S | 1, AFE_MASK_ALL);
// start I2S DAC out
if (GetMemoryPathEnable(Soc_Aud_Digital_Block_I2S_OUT_DAC) == false)
{
SetMemoryPathEnable(Soc_Aud_Digital_Block_I2S_OUT_DAC, true);
SetI2SDacOut(substream->runtime->rate, false, Soc_Aud_I2S_WLEN_WLEN_32BITS);
SetI2SDacEnable(true);
}
else
{
SetMemoryPathEnable(Soc_Aud_Digital_Block_I2S_OUT_DAC, true);
}
if (GetMemoryPathEnable(Soc_Aud_Digital_Block_I2S_IN_ADC) == false)
{
ConfigAdcI2S(substream);
SetI2SAdcIn(&mAudioDigitalI2S);
SetMemoryPathEnable(Soc_Aud_Digital_Block_I2S_IN_ADC, true);
SetI2SAdcEnable(true);
}
else
{
SetMemoryPathEnable(Soc_Aud_Digital_Block_I2S_IN_ADC, true);
}
EnableAfe(true);
return 0;
}
static void StartAudioCaptureHardware(struct snd_pcm_substream *substream)
{
printk("StartAudioCaptureHardware \n");
ConfigAdcI2S(substream);
SetI2SAdcIn(mAudioDigitalI2S);
SetMemIfFetchFormatPerSample(Soc_Aud_Digital_Block_MEM_VUL, AFE_WLEN_16_BIT);
SetMemIfFetchFormatPerSample(Soc_Aud_Digital_Block_MEM_VUL, AFE_WLEN_16_BIT);
SetoutputConnectionFormat(OUTPUT_DATA_FORMAT_16BIT, Soc_Aud_InterConnectionOutput_O09);
SetoutputConnectionFormat(OUTPUT_DATA_FORMAT_16BIT, Soc_Aud_InterConnectionOutput_O10);
if (GetMemoryPathEnable(Soc_Aud_Digital_Block_I2S_IN_ADC) == false)
{
SetMemoryPathEnable(Soc_Aud_Digital_Block_I2S_IN_ADC, true);
SetI2SAdcEnable(true);
}
else
{
SetMemoryPathEnable(Soc_Aud_Digital_Block_I2S_IN_ADC, true);
}
SetConnection(Soc_Aud_InterCon_Connection, Soc_Aud_InterConnectionInput_I03, Soc_Aud_InterConnectionOutput_O09);
SetConnection(Soc_Aud_InterCon_Connection, Soc_Aud_InterConnectionInput_I04, Soc_Aud_InterConnectionOutput_O10);
if (substream->runtime->format == SNDRV_PCM_FORMAT_S32_LE || substream->runtime->format == SNDRV_PCM_FORMAT_U32_LE)
{
SetMemIfFetchFormatPerSample(Soc_Aud_Digital_Block_MEM_VUL, AFE_WLEN_32_BIT_ALIGN_8BIT_0_24BIT_DATA);
SetoutputConnectionFormat(OUTPUT_DATA_FORMAT_24BIT, Soc_Aud_InterConnectionOutput_O09);
SetoutputConnectionFormat(OUTPUT_DATA_FORMAT_24BIT, Soc_Aud_InterConnectionOutput_O10);
}
// here to set interrupt
SetIrqMcuCounter(Soc_Aud_IRQ_MCU_MODE_IRQ2_MCU_MODE, substream->runtime->period_size);
SetIrqMcuSampleRate(Soc_Aud_IRQ_MCU_MODE_IRQ2_MCU_MODE, substream->runtime->rate);
SetIrqEnable(Soc_Aud_IRQ_MCU_MODE_IRQ2_MCU_MODE, true);
SetSampleRate(Soc_Aud_Digital_Block_MEM_VUL, substream->runtime->rate);
SetMemoryPathEnable(Soc_Aud_Digital_Block_MEM_VUL, true);
EnableAfe(true);
#ifdef DENALI_FPGA_EARLYPORTING //ccc early porting test, copy from TurnOnADcPowerACC()
//here to set digital part
//Topck_Enable(true);
//AdcClockEnable(true);
//Ana_Set_Reg(AFE_ADDA2_UL_SRC_CON1_L, 0x0000, 0xffff); //power on ADC clk //early porting 6752 remove
Ana_Set_Reg(AFE_AUDIO_TOP_CON0, 0x0000, 0xffff); //power on clock
//Ana_Set_Reg(AFE_ADDA2_UL_SRC_CON1_L, 0x0000, 0xffff); //power on ADC clk //early porting 6752 remove
Ana_Set_Reg(PMIC_AFE_TOP_CON0, 0x0000, 0xffff); //configure ADC setting
Ana_Set_Reg(AFE_UL_DL_CON0, 0x0001, 0xffff); //turn on afe
Ana_Set_Reg(AFE_PMIC_NEWIF_CFG2, 0x302F, 0xffff); // config UL up8x_rxif adc voice mode, 8k sample rate
Ana_Set_Reg(AFE_UL_SRC0_CON0_H, (0 << 3 | 0 << 1) , 0x001f);// ULsampling rate, 8k sample rate
//Ana_Set_Reg(AFE_ADDA2_UL_SRC_CON0_H, (ULSampleRateTransform(SampleRate_VUL2) << 3 | ULSampleRateTransform(SampleRate_VUL2) << 1) , 0x001f); // ULsampling rate
//Ana_Set_Reg(AFE_ADDA2_UL_SRC_CON0_L, 0x0041, 0xffff);
Ana_Set_Reg(AFE_UL_SRC0_CON0_L, 0x0005, 0xffff); //power on uplink, and loopback to DL
Afe_Set_Reg(FPGA_CFG1, 0x1, 0xffff); // must set in FPGA platform for PMIC digital loopback
#endif
}
