CY_CFG_SECTION static void ClockSetup(void) { /* Enable HALF_EN before trimming for the flash accelerator. */ CY_SET_REG32((void CYXDATA *)(CYREG_CLK_SELECT), (CY_GET_REG32((void *)CYREG_CLK_SELECT) | 0x00040000u)); /* Trim IMO BG based on desired frequency. */ SetIMOBGTrims(24u); /* Going less than or equal to 24MHz, so update the clock speed then adjust trim value. */ CY_SET_REG32((void CYXDATA *)(CYREG_CLK_IMO_TRIM2), (25u)); CyDelayCycles(5u); CY_SET_REG32((void CYXDATA *)(CYREG_CLK_IMO_TRIM1), (CY_GET_REG8((void *)CYREG_SFLASH_IMO_TRIM21))); CyDelayUs(5u); /* Disable HALF_EN since it is not required at this IMO frequency. */ CY_SET_REG32((void CYXDATA *)(CYREG_CLK_SELECT), (CY_GET_REG32((void *)CYREG_CLK_SELECT) & 0xFFFBFFFFu)); /* CYDEV_CLK_ILO_CONFIG Starting address: CYDEV_CLK_ILO_CONFIG */ CY_SET_XTND_REG32((void CYFAR *)(CYREG_CLK_ILO_CONFIG), 0x80000006u); /* CYDEV_CLK_SELECT00 Starting address: CYDEV_CLK_SELECT00 */ CY_SET_XTND_REG32((void CYFAR *)(CYREG_CLK_SELECT12), 0x00000010u); /* CYDEV_CLK_IMO_CONFIG Starting address: CYDEV_CLK_IMO_CONFIG */ CY_SET_XTND_REG32((void CYFAR *)(CYREG_CLK_IMO_CONFIG), 0x80000000u); /* CYDEV_CLK_DIVIDER_A00 Starting address: CYDEV_CLK_DIVIDER_A00 */ CY_SET_XTND_REG32((void CYFAR *)(CYREG_CLK_DIVIDER_A00), 0x80000033u); }
CY_CFG_SECTION static void ClockSetup(void) { /* Enable HALF_EN before trimming for the flash accelerator. */ CY_SET_REG32((void CYXDATA *)(CYREG_CLK_SELECT), (CY_GET_REG32((void *)CYREG_CLK_SELECT) | 0x00040000u)); /* Trim IMO BG based on desired frequency. */ SetIMOBGTrims(48u); /* Going faster than 24MHz, so update trim value then adjust to new clock speed. */ CY_SET_REG32((void CYXDATA *)(CYREG_CLK_IMO_TRIM1), (CY_GET_REG8((void *)CYREG_SFLASH_IMO_TRIM45))); CyDelayUs(5u); CY_SET_REG32((void CYXDATA *)(CYREG_CLK_IMO_TRIM2), (53u)); /* CYDEV_CLK_SELECT00 Starting address: CYDEV_CLK_SELECT00 */ CY_SET_XTND_REG32((void CYFAR *)(CYREG_CLK_SELECT02), 0x00000010u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_CLK_SELECT03), 0x00000010u); /* CYDEV_CLK_IMO_CONFIG Starting address: CYDEV_CLK_IMO_CONFIG */ CY_SET_XTND_REG32((void CYFAR *)(CYREG_CLK_IMO_CONFIG), 0x80000000u); /* CYDEV_CLK_ILO_CONFIG Starting address: CYDEV_CLK_ILO_CONFIG */ CY_SET_XTND_REG32((void CYFAR *)(CYREG_CLK_ILO_CONFIG), 0x80000000u); /* CYDEV_CLK_SELECT Starting address: CYDEV_CLK_SELECT */ CY_SET_XTND_REG32((void CYFAR *)(CYREG_CLK_SELECT), 0x00040000u); /* CYDEV_CLK_DIVIDER_A00 Starting address: CYDEV_CLK_DIVIDER_A00 */ CY_SET_XTND_REG32((void CYFAR *)(CYREG_CLK_DIVIDER_A00), 0x80000000u); }
CY_CFG_SECTION static void ClockSetup(void) { /* Set Flash Cycles based on max possible frequency in case a glitch occurs during ClockSetup(). */ CY_SET_REG32((void CYXDATA *)(CYREG_CPUSS_FLASH_CTL), (0x0012u)); /* Trim IMO BG based on desired frequency. */ SetIMOBGTrims(12u); /* Going less than or equal to 24MHz, so update the clock speed then adjust trim value. */ CY_SET_REG32((void CYXDATA *)(CYREG_CLK_IMO_TRIM2), (12u)); CyDelayCycles(5u); CY_SET_REG32((void CYXDATA *)(CYREG_CLK_IMO_TRIM1), (CY_GET_REG8((void *)CYREG_SFLASH_IMO_TRIM09))); CyDelayUs(5u); /* Start the WCO */ CySysClkWcoStart(); CyDelay(500u); /* WCO may take up to 500ms to start */ (void)CySysClkWcoSetPowerMode(CY_SYS_CLK_WCO_LPM); /* Switch to the low power mode */ /* CYDEV_WDT_CONFIG Starting address: CYDEV_WDT_CONFIG */ CY_SET_XTND_REG32((void CYFAR *)(CYREG_WDT_CONFIG), 0x40000000u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_BLE_BLERD_BB_XO_CAPTRIM), 0x00002D6Au); /* Disable Crystal Stable Interrupt before enabling ECO */ CY_SET_REG32((void*)CYREG_BLE_BLESS_LL_DSM_CTRL, CY_GET_REG32((void*)CYREG_BLE_BLESS_LL_DSM_CTRL) & (~(uint32)0x08u)); /* Start the ECO and do not check status since it is not needed for HFCLK */ (void)CySysClkEcoStart(2000u); CyDelayUs(1500u); /* Wait to stabalize */ /* Setup phase aligned clocks */ CY_SET_REG32((void *)CYREG_PERI_DIV_16_CTL02, 0x00000B00u); CY_SET_REG32((void *)CYREG_PERI_DIV_CMD, 0x8000FF42u); CY_SET_REG32((void *)CYREG_PERI_DIV_16_CTL00, 0x0000FE00u); CY_SET_REG32((void *)CYREG_PERI_DIV_CMD, 0x8000FF40u); CY_SET_REG32((void *)CYREG_PERI_DIV_16_CTL01, 0x0000FE00u); CY_SET_REG32((void *)CYREG_PERI_DIV_CMD, 0x8000FF41u); /* CYDEV_CLK_IMO_CONFIG Starting address: CYDEV_CLK_IMO_CONFIG */ CY_SET_XTND_REG32((void CYFAR *)(CYREG_CLK_IMO_CONFIG), 0x80000000u); /* CYDEV_PERI_PCLK_CTL11 Starting address: CYDEV_PERI_PCLK_CTL11 */ CY_SET_XTND_REG32((void CYFAR *)(CYREG_PERI_PCLK_CTL11), 0x00000042u); /* CYDEV_PERI_PCLK_CTL05 Starting address: CYDEV_PERI_PCLK_CTL05 */ CY_SET_XTND_REG32((void CYFAR *)(CYREG_PERI_PCLK_CTL05), 0x00000040u); /* CYDEV_PERI_PCLK_CTL04 Starting address: CYDEV_PERI_PCLK_CTL04 */ CY_SET_XTND_REG32((void CYFAR *)(CYREG_PERI_PCLK_CTL04), 0x00000041u); /* Set Flash Cycles based on newly configured 12.00MHz HFCLK. */ CY_SET_REG32((void CYXDATA *)(CYREG_CPUSS_FLASH_CTL), (0x0000u)); }