static int mtk_fm_i2s_awb_alsa_start(struct snd_pcm_substream *substream) { pr_warn("mtk_fm_i2s_awb_alsa_start\n"); SetMemifSubStream(Soc_Aud_Digital_Block_MEM_AWB, substream); StartAudioFMI2SAWBHardware(substream); return 0; }
static int mtk_bt_dai_alsa_start(struct snd_pcm_substream *substream) { printk("mtk_bt_dai_alsa_start \n"); SetMemifSubStream(Soc_Aud_Digital_Block_MEM_DAI, substream); StartAudioBtDaiHardware(substream); return 0; }
static int mtk_mrgrx_awb_alsa_start(struct snd_pcm_substream *substream) { printk("mtk_mrgrx_awb_alsa_start \n"); SetMemifSubStream(Soc_Aud_Digital_Block_MEM_AWB,substream); StartAudioMrgrxAWBHardware(substream); return 0; }
static int mtk_capture_alsa_start(struct snd_pcm_substream *substream) { printk("mtk_capture_alsa_start \n"); SetMemifSubStream(Soc_Aud_Digital_Block_MEM_VUL, substream); StartAudioCaptureHardware(substream); return 0; }
static int mtk_pcm_dl1bt_start(struct snd_pcm_substream *substream) { struct snd_pcm_runtime *runtime = substream->runtime; AudDrv_Clk_On(); SetMemifSubStream(Soc_Aud_Digital_Block_MEM_DL1, substream); if (runtime->format == SNDRV_PCM_FORMAT_S32_LE || runtime->format == SNDRV_PCM_FORMAT_U32_LE) { SetMemIfFetchFormatPerSample(Soc_Aud_Digital_Block_MEM_DL1, AFE_WLEN_32_BIT_ALIGN_8BIT_0_24BIT_DATA); SetMemIfFetchFormatPerSample(Soc_Aud_Digital_Block_MEM_DL2, AFE_WLEN_32_BIT_ALIGN_8BIT_0_24BIT_DATA); /* BT SCO only support 16 bit */ SetoutputConnectionFormat(OUTPUT_DATA_FORMAT_16BIT, Soc_Aud_InterConnectionOutput_O02); } else { SetMemIfFetchFormatPerSample(Soc_Aud_Digital_Block_MEM_DL1, AFE_WLEN_16_BIT); SetMemIfFetchFormatPerSample(Soc_Aud_Digital_Block_MEM_DL2, AFE_WLEN_16_BIT); SetoutputConnectionFormat(OUTPUT_DATA_FORMAT_16BIT, Soc_Aud_InterConnectionOutput_O02); } /* here start digital part */ SetConnection(Soc_Aud_InterCon_Connection, Soc_Aud_InterConnectionInput_I05, Soc_Aud_InterConnectionOutput_O02); SetConnection(Soc_Aud_InterCon_Connection, Soc_Aud_InterConnectionInput_I06, Soc_Aud_InterConnectionOutput_O02); SetConnection(Soc_Aud_InterCon_ConnectionShift, Soc_Aud_InterConnectionInput_I05, Soc_Aud_InterConnectionOutput_O02); SetConnection(Soc_Aud_InterCon_ConnectionShift, Soc_Aud_InterConnectionInput_I06, Soc_Aud_InterConnectionOutput_O02); /* set dl1 sample ratelimit_state */ SetSampleRate(Soc_Aud_Digital_Block_MEM_DL1, runtime->rate); SetChannels(Soc_Aud_Digital_Block_MEM_DL1, runtime->channels); SetMemoryPathEnable(Soc_Aud_Digital_Block_MEM_DL1, true); /* here to set interrupt */ SetIrqMcuCounter(Soc_Aud_IRQ_MCU_MODE_IRQ1_MCU_MODE, runtime->period_size >> 1); SetIrqMcuSampleRate(Soc_Aud_IRQ_MCU_MODE_IRQ1_MCU_MODE, runtime->rate); SetIrqEnable(Soc_Aud_IRQ_MCU_MODE_IRQ1_MCU_MODE, true); if (GetMemoryPathEnable(Soc_Aud_Digital_Block_DAI_BT) == false) { /* set merge interface */ SetMemoryPathEnable(Soc_Aud_Digital_Block_DAI_BT, true); } else { SetMemoryPathEnable(Soc_Aud_Digital_Block_DAI_BT, true); } SetVoipDAIBTAttribute(runtime->rate); SetDaiBtEnable(true); EnableAfe(true); return 0; }
static int mtk_pcm_dl2_prepare(struct snd_pcm_substream *substream) { bool mI2SWLen = Soc_Aud_I2S_WLEN_WLEN_16BITS; struct snd_pcm_runtime *runtime = substream->runtime; if (mPrepareDone == false) { pr_warn ("%s format = %d SNDRV_PCM_FORMAT_S32_LE = %d SNDRV_PCM_FORMAT_U32_LE = %d\n", __func__, runtime->format, SNDRV_PCM_FORMAT_S32_LE, SNDRV_PCM_FORMAT_U32_LE); SetMemifSubStream(Soc_Aud_Digital_Block_MEM_DL2, substream); if (runtime->format == SNDRV_PCM_FORMAT_S32_LE || runtime->format == SNDRV_PCM_FORMAT_U32_LE) { /* not support 24bit +++ */ SetMemIfFetchFormatPerSample(Soc_Aud_Digital_Block_MEM_DL2, AFE_WLEN_32_BIT_ALIGN_8BIT_0_24BIT_DATA); SetoutputConnectionFormat(OUTPUT_DATA_FORMAT_24BIT, Soc_Aud_InterConnectionOutput_O03); SetoutputConnectionFormat(OUTPUT_DATA_FORMAT_24BIT, Soc_Aud_InterConnectionOutput_O04); /* not support 24bit --- */ mI2SWLen = Soc_Aud_I2S_WLEN_WLEN_32BITS; } else { /* not support 24bit +++ */ SetMemIfFetchFormatPerSample(Soc_Aud_Digital_Block_MEM_DL2, AFE_WLEN_16_BIT); SetoutputConnectionFormat(OUTPUT_DATA_FORMAT_16BIT, Soc_Aud_InterConnectionOutput_O03); SetoutputConnectionFormat(OUTPUT_DATA_FORMAT_16BIT, Soc_Aud_InterConnectionOutput_O04); /* not support 24bit --- */ mI2SWLen = Soc_Aud_I2S_WLEN_WLEN_16BITS; } SetSampleRate(Soc_Aud_Digital_Block_MEM_I2S, runtime->rate); /* start I2S DAC out */ if (GetMemoryPathEnable(Soc_Aud_Digital_Block_I2S_OUT_DAC) == false) { SetMemoryPathEnable(Soc_Aud_Digital_Block_I2S_OUT_DAC, true); SetI2SDacOut(substream->runtime->rate, false, mI2SWLen); SetI2SDacEnable(true); } else { SetMemoryPathEnable(Soc_Aud_Digital_Block_I2S_OUT_DAC, true); } /* here to set interrupt_distributor */ SetIrqMcuCounter(Soc_Aud_IRQ_MCU_MODE_IRQ1_MCU_MODE, runtime->period_size); SetIrqMcuSampleRate(Soc_Aud_IRQ_MCU_MODE_IRQ1_MCU_MODE, runtime->rate); EnableAfe(true); mPrepareDone = true; } return 0; }
static int mtk_pcm_fmtx_start(struct snd_pcm_substream *substream) { struct snd_pcm_runtime *runtime = substream->runtime; AudDrv_Clk_On(); // mtk_wcn_cmb_stub_audio_ctrl((CMB_STUB_AIF_X)CMB_STUB_AIF_2); SetMemifSubStream(Soc_Aud_Digital_Block_MEM_DL1, substream); if (runtime->format == SNDRV_PCM_FORMAT_S32_LE || runtime->format == SNDRV_PCM_FORMAT_U32_LE) { SetMemIfFetchFormatPerSample(Soc_Aud_Digital_Block_MEM_DL1, AFE_WLEN_32_BIT_ALIGN_8BIT_0_24BIT_DATA); SetMemIfFetchFormatPerSample(Soc_Aud_Digital_Block_MEM_DL2, AFE_WLEN_32_BIT_ALIGN_8BIT_0_24BIT_DATA); SetoutputConnectionFormat(OUTPUT_DATA_FORMAT_16BIT, Soc_Aud_InterConnectionOutput_O00); // FM Tx only support 16 bit SetoutputConnectionFormat(OUTPUT_DATA_FORMAT_16BIT, Soc_Aud_InterConnectionOutput_O01); // FM Tx only support 16 bit } else { SetMemIfFetchFormatPerSample(Soc_Aud_Digital_Block_MEM_DL1, AFE_WLEN_16_BIT); SetMemIfFetchFormatPerSample(Soc_Aud_Digital_Block_MEM_DL2, AFE_WLEN_16_BIT); SetoutputConnectionFormat(OUTPUT_DATA_FORMAT_16BIT, Soc_Aud_InterConnectionOutput_O00); SetoutputConnectionFormat(OUTPUT_DATA_FORMAT_16BIT, Soc_Aud_InterConnectionOutput_O01); } // here start digital part SetConnection(Soc_Aud_InterCon_Connection, Soc_Aud_InterConnectionInput_I05, Soc_Aud_InterConnectionOutput_O00); SetConnection(Soc_Aud_InterCon_Connection, Soc_Aud_InterConnectionInput_I06, Soc_Aud_InterConnectionOutput_O01); // set dl1 sample ratelimit_state SetSampleRate(Soc_Aud_Digital_Block_MEM_DL1, runtime->rate); SetChannels(Soc_Aud_Digital_Block_MEM_DL1, runtime->channels); // start MRG I2S Out SetMemoryPathEnable(Soc_Aud_Digital_Block_MRG_I2S_OUT, true); SetMrgI2SEnable(true, runtime->rate) ; // start 2nd I2S Out Set2ndI2SOutAttribute(runtime->rate) ; Set2ndI2SOutEnable(true); SetMemoryPathEnable(Soc_Aud_Digital_Block_MEM_DL1, true); // here to set interrupt SetIrqMcuCounter(Soc_Aud_IRQ_MCU_MODE_IRQ1_MCU_MODE, (runtime->period_size * 2 / 3)); SetIrqMcuSampleRate(Soc_Aud_IRQ_MCU_MODE_IRQ1_MCU_MODE, runtime->rate); SetIrqEnable(Soc_Aud_IRQ_MCU_MODE_IRQ1_MCU_MODE, true); EnableAfe(true); return 0; }
static int mtk_pcm_i2s0_start(struct snd_pcm_substream *substream) { struct snd_pcm_runtime *runtime = substream->runtime; uint32 u32AudioI2S = 0; AudDrv_Clk_On(); SetMemifSubStream(Soc_Aud_Digital_Block_MEM_DL1, substream); if (runtime->format == SNDRV_PCM_FORMAT_S32_LE || runtime->format == SNDRV_PCM_FORMAT_S32_LE) { SetMemIfFetchFormatPerSample(Soc_Aud_Digital_Block_MEM_DL1, AFE_WLEN_32_BIT_ALIGN_8BIT_0_24BIT_DATA); SetMemIfFetchFormatPerSample(Soc_Aud_Digital_Block_MEM_DL2, AFE_WLEN_32_BIT_ALIGN_8BIT_0_24BIT_DATA); } else { SetMemIfFetchFormatPerSample(Soc_Aud_Digital_Block_MEM_DL1, AFE_WLEN_16_BIT); SetMemIfFetchFormatPerSample(Soc_Aud_Digital_Block_MEM_DL2, AFE_WLEN_16_BIT); } SetoutputConnectionFormat(OUTPUT_DATA_FORMAT_16BIT, Soc_Aud_InterConnectionOutput_O00); SetoutputConnectionFormat(OUTPUT_DATA_FORMAT_16BIT, Soc_Aud_InterConnectionOutput_O01); // here start digital part SetConnection(Soc_Aud_InterCon_Connection, Soc_Aud_InterConnectionInput_I05, Soc_Aud_InterConnectionOutput_O00); SetConnection(Soc_Aud_InterCon_Connection, Soc_Aud_InterConnectionInput_I06, Soc_Aud_InterConnectionOutput_O01); u32AudioI2S = SampleRateTransform(runtime->rate) << 8; u32AudioI2S |= Soc_Aud_I2S_FORMAT_I2S << 3; // us3 I2s format u32AudioI2S |= Soc_Aud_I2S_WLEN_WLEN_32BITS << 1; // 32 BITS if (mi2s0_hdoutput_control == true) { u32AudioI2S |= Soc_Aud_LOW_JITTER_CLOCK << 12 ; //Low jitter mode } printk(" u32AudioI2S= 0x%x\n", u32AudioI2S); Afe_Set_Reg(AFE_I2S_CON3, u32AudioI2S | 1, AFE_MASK_ALL); SetSampleRate(Soc_Aud_Digital_Block_MEM_DL1, runtime->rate); SetChannels(Soc_Aud_Digital_Block_MEM_DL1, runtime->channels); SetMemoryPathEnable(Soc_Aud_Digital_Block_MEM_DL1, true); // here to set interrupt SetIrqMcuCounter(Soc_Aud_IRQ_MCU_MODE_IRQ1_MCU_MODE, runtime->period_size); SetIrqMcuSampleRate(Soc_Aud_IRQ_MCU_MODE_IRQ1_MCU_MODE, runtime->rate); SetIrqEnable(Soc_Aud_IRQ_MCU_MODE_IRQ1_MCU_MODE, true); EnableAfe(true); return 0; }
static int mtk_capture_alsa_start(struct snd_pcm_substream *substream) { printk("mtk_capture_alsa_start \n"); SetMemifSubStream(Soc_Aud_Digital_Block_MEM_VUL, substream); StartAudioCaptureHardware(substream); #ifdef DENALI_FPGA_EARLYPORTING //ccc early porting, copy from TurnOnDacPower() and ADC_LOOP_DAC_Func() // Afe_Set_Reg(AFE_SGEN_CON0, 0x24862862, 0xffffffff); // Ana_Set_Reg(PMIC_AFE_TOP_CON0, 0x0002, 0x0002); //UL from sinetable // Ana_Set_Reg(PMIC_AFE_TOP_CON0, 0x0001, 0x0001); //DL from sinetable // Ana_Set_Reg(AFE_SGEN_CFG0 , 0x0080 , 0xffff); // Ana_Set_Reg(AFE_SGEN_CFG1 , 0x0101 , 0xffff); Ana_Get_Reg(AFE_AUDIO_TOP_CON0); //power on clock Ana_Get_Reg(AFUNC_AUD_CON2); Ana_Get_Reg(AFUNC_AUD_CON0); //sdm audio fifo clock power on Ana_Get_Reg(AFUNC_AUD_CON2); //sdm power on Ana_Get_Reg(AFUNC_AUD_CON2); //sdm fifo enable Ana_Get_Reg(AFE_DL_SDM_CON1); //set attenuation gain Ana_Get_Reg(AFE_UL_DL_CON0); //[0] afe enable Ana_Get_Reg(AFE_PMIC_NEWIF_CFG0); //8k sample rate Ana_Get_Reg(AFE_DL_SRC2_CON0_H);//8k sample rate Ana_Get_Reg(AFE_DL_SRC2_CON0_L); //turn off mute function and turn on dl Ana_Get_Reg(PMIC_AFE_TOP_CON0); //set DL in normal path, not from sine gen table Ana_Get_Reg(AFE_SGEN_CFG0); //set DL in normal path, not from sine gen table Ana_Get_Reg(AFE_SGEN_CFG1); //set DL in normal path, not from sine gen table Ana_Get_Reg(TOP_CLKSQ); //Enable CLKSQ 26MHz Ana_Get_Reg(TOP_CLKSQ_SET); //Turn on 26MHz source clock Ana_Get_Reg(AFE_AUDIO_TOP_CON0); //power on clock Ana_Get_Reg(FPGA_CFG1); // must set in FPGA platform for PMIC digital loopback #endif return 0; }
static int mtk_pcm_hdmi_start(struct snd_pcm_substream *substream) { struct snd_pcm_runtime *runtime = substream->runtime; uint32 mclkDiv; pr_debug("[%s] runtime->rate = %d, runtime->channels = %d, runtime->period_size = %d\n", __func__, runtime->rate, runtime->channels, (unsigned int)runtime->period_size); SetMemifSubStream(Soc_Aud_Digital_Block_MEM_HDMI, substream); /* HDMI I2S clock setting */ mclkDiv = SetCLkMclk(Soc_Aud_HDMI_MCK, runtime->rate); SetCLkHdmiBclk(mclkDiv, runtime->rate, 2, 32); /* enable mclk divider */ EnableSpdifDivPower(AUDIO_APLL_SPDIF_DIV, true); /* enable bck divider */ EnableHDMIDivPower(AUDIO_APLL_HDMI_BCK_DIV, true); /* turn on hdmi clk */ SetHdmiClkOn(); /* config hdmi irq */ SetIrqMcuCounter(Soc_Aud_IRQ_MCU_MODE_IRQ5_MCU_MODE, runtime->period_size); /* config hdmi interface */ if (runtime->format == SNDRV_PCM_FORMAT_S32_LE || runtime->format == SNDRV_PCM_FORMAT_U32_LE) { SetMemIfFetchFormatPerSample(Soc_Aud_Digital_Block_MEM_HDMI, AFE_WLEN_32_BIT_ALIGN_24BIT_DATA_8BIT_0); Afe_Set_Reg(AFE_HDMI_OUT_CON0, 0x2, 0x2); } else SetMemIfFetchFormatPerSample(Soc_Aud_Digital_Block_MEM_HDMI, AFE_WLEN_16_BIT); SetHdmiTdm1Config(runtime->channels, AFE_DATA_WLEN_32BIT); SetHdmiTdm2Config(runtime->channels); SetHDMIChannels(runtime->channels); /* config hdmi connection */ SetHdmiPcmInterConnection(Soc_Aud_InterCon_Connection, runtime->channels); /* Enable hdmi Memory Path */ SetMemoryPathEnable(Soc_Aud_Digital_Block_MEM_HDMI, true); /* enable irq */ SetIrqEnable(Soc_Aud_IRQ_MCU_MODE_IRQ5_MCU_MODE, true); /* enable hdmi out */ SetHDMIEnable(true); /* enable afe */ EnableAfe(true); /* enable TDM */ SetTDMEnable(runtime->channels); pr_debug ("[%s] AFE_IRQ_MCU_STATUS = 0x%x AFE_IRQ_MCU_EN = 0x%x AFE_IRQ_CNT5=0x%x AFE_IRQ_DEBUG =0x%x\n", __func__, Afe_Get_Reg(AFE_IRQ_MCU_STATUS), Afe_Get_Reg(AFE_IRQ_MCU_EN), Afe_Get_Reg(AFE_IRQ_CNT5), Afe_Get_Reg(AFE_IRQ_DEBUG)); return 0; }
static int mtk_pcm_I2S0dl1_prepare(struct snd_pcm_substream *substream) { struct snd_pcm_runtime *runtime = substream->runtime; uint32 Audio_I2S_Dac = 0, MclkDiv0, MclkDiv3; uint32 u32AudioI2S = 0; if (mPrepareDone == false) { pr_debug("%s format = %d SNDRV_PCM_FORMAT_S32_LE = %d SNDRV_PCM_FORMAT_U32_LE = %d \n", __func__, runtime->format, SNDRV_PCM_FORMAT_S32_LE, SNDRV_PCM_FORMAT_U32_LE); SetMemifSubStream(Soc_Aud_Digital_Block_MEM_DL1, substream); if (runtime->format == SNDRV_PCM_FORMAT_S32_LE || runtime->format == SNDRV_PCM_FORMAT_U32_LE) { SetMemIfFetchFormatPerSample(Soc_Aud_Digital_Block_MEM_DL1, AFE_WLEN_32_BIT_ALIGN_8BIT_0_24BIT_DATA); SetMemIfFetchFormatPerSample(Soc_Aud_Digital_Block_MEM_DL2, AFE_WLEN_32_BIT_ALIGN_8BIT_0_24BIT_DATA); SetoutputConnectionFormat(OUTPUT_DATA_FORMAT_24BIT, Soc_Aud_InterConnectionOutput_O03); SetoutputConnectionFormat(OUTPUT_DATA_FORMAT_24BIT, Soc_Aud_InterConnectionOutput_O04); SetoutputConnectionFormat(OUTPUT_DATA_FORMAT_24BIT, Soc_Aud_InterConnectionOutput_O00); SetoutputConnectionFormat(OUTPUT_DATA_FORMAT_24BIT, Soc_Aud_InterConnectionOutput_O01); } else { SetMemIfFetchFormatPerSample(Soc_Aud_Digital_Block_MEM_DL1, AFE_WLEN_16_BIT); SetMemIfFetchFormatPerSample(Soc_Aud_Digital_Block_MEM_DL2, AFE_WLEN_16_BIT); SetoutputConnectionFormat(OUTPUT_DATA_FORMAT_16BIT, Soc_Aud_InterConnectionOutput_O03); SetoutputConnectionFormat(OUTPUT_DATA_FORMAT_16BIT, Soc_Aud_InterConnectionOutput_O04); SetoutputConnectionFormat(OUTPUT_DATA_FORMAT_16BIT, Soc_Aud_InterConnectionOutput_O00); SetoutputConnectionFormat(OUTPUT_DATA_FORMAT_16BIT, Soc_Aud_InterConnectionOutput_O01); } SetoutputConnectionFormat(OUTPUT_DATA_FORMAT_16BIT, Soc_Aud_InterConnectionOutput_O00); SetoutputConnectionFormat(OUTPUT_DATA_FORMAT_16BIT, Soc_Aud_InterConnectionOutput_O01); SetSampleRate(Soc_Aud_Digital_Block_MEM_I2S, runtime->rate); Audio_I2S_Dac |= (Soc_Aud_LR_SWAP_NO_SWAP << 31); if (mI2S0dl1_hdoutput_control == true) { MclkDiv0 = SetCLkMclk(Soc_Aud_I2S0, runtime->rate); //select I2S SetCLkBclk(MclkDiv0, runtime->rate, runtime->channels, Soc_Aud_I2S_WLEN_WLEN_32BITS); Audio_I2S_Dac |= Soc_Aud_LOW_JITTER_CLOCK << 12 ; //Low jitter mode } else { Audio_I2S_Dac &= ~(Soc_Aud_LOW_JITTER_CLOCK << 12) ; } Audio_I2S_Dac |= (Soc_Aud_I2S_IN_PAD_SEL_I2S_IN_FROM_IO_MUX << 28);//I2S in from io_mux Audio_I2S_Dac |= (Soc_Aud_INV_LRCK_NO_INVERSE << 5); Audio_I2S_Dac |= (Soc_Aud_I2S_FORMAT_I2S << 3); Audio_I2S_Dac |= (Soc_Aud_I2S_WLEN_WLEN_32BITS << 1); // I2S out Setting u32AudioI2S = SampleRateTransform(runtime->rate) << 8; u32AudioI2S |= Soc_Aud_I2S_FORMAT_I2S << 3; // us3 I2s format u32AudioI2S |= Soc_Aud_I2S_WLEN_WLEN_32BITS << 1; // 32 BITS if (mI2S0dl1_hdoutput_control == true) { MclkDiv3 = SetCLkMclk(Soc_Aud_I2S3, runtime->rate); //select I2S SetCLkBclk(MclkDiv3, runtime->rate, runtime->channels, Soc_Aud_I2S_WLEN_WLEN_32BITS); u32AudioI2S |= Soc_Aud_LOW_JITTER_CLOCK << 12 ; //Low jitter mode } else { u32AudioI2S &= ~(Soc_Aud_LOW_JITTER_CLOCK << 12) ; } if (GetMemoryPathEnable(Soc_Aud_Digital_Block_I2S_OUT_2) == false) { SetMemoryPathEnable(Soc_Aud_Digital_Block_I2S_OUT_2, true); Afe_Set_Reg(AFE_I2S_CON, Audio_I2S_Dac | 0x1, MASK_ALL); Afe_Set_Reg(AFE_I2S_CON3, u32AudioI2S | 1, AFE_MASK_ALL); } else { SetMemoryPathEnable(Soc_Aud_Digital_Block_I2S_OUT_2, true); } // start I2S DAC out if (GetMemoryPathEnable(Soc_Aud_Digital_Block_I2S_OUT_DAC) == false) { SetMemoryPathEnable(Soc_Aud_Digital_Block_I2S_OUT_DAC, true); SetI2SDacOut(substream->runtime->rate); SetI2SDacEnable(true); } else { SetMemoryPathEnable(Soc_Aud_Digital_Block_I2S_OUT_DAC, true); } // here to set interrupt_distributor SetIrqMcuCounter(Soc_Aud_IRQ_MCU_MODE_IRQ1_MCU_MODE, runtime->period_size); SetIrqMcuSampleRate(Soc_Aud_IRQ_MCU_MODE_IRQ1_MCU_MODE, runtime->rate); EnableAfe(true); mPrepareDone = true; } return 0; }
static int mtk_pcm_I2S0dl1_prepare(struct snd_pcm_substream *substream) { struct snd_pcm_runtime *runtime = substream->runtime; uint32 MclkDiv3; uint32 u32AudioI2S = 0; bool mI2SWLen; if (mPrepareDone == false) { printk("%s format = %d SNDRV_PCM_FORMAT_S32_LE = %d SNDRV_PCM_FORMAT_U32_LE = %d \n", __func__, runtime->format, SNDRV_PCM_FORMAT_S32_LE, SNDRV_PCM_FORMAT_U32_LE); SetMemifSubStream(Soc_Aud_Digital_Block_MEM_DL1, substream); if (runtime->format == SNDRV_PCM_FORMAT_S32_LE || runtime->format == SNDRV_PCM_FORMAT_U32_LE) { SetMemIfFetchFormatPerSample(Soc_Aud_Digital_Block_MEM_DL1, AFE_WLEN_32_BIT_ALIGN_8BIT_0_24BIT_DATA); SetMemIfFetchFormatPerSample(Soc_Aud_Digital_Block_MEM_DL2, AFE_WLEN_32_BIT_ALIGN_8BIT_0_24BIT_DATA); SetoutputConnectionFormat(OUTPUT_DATA_FORMAT_24BIT, Soc_Aud_InterConnectionOutput_O03); SetoutputConnectionFormat(OUTPUT_DATA_FORMAT_24BIT, Soc_Aud_InterConnectionOutput_O04); SetoutputConnectionFormat(OUTPUT_DATA_FORMAT_24BIT, Soc_Aud_InterConnectionOutput_O00); SetoutputConnectionFormat(OUTPUT_DATA_FORMAT_24BIT, Soc_Aud_InterConnectionOutput_O01); mI2SWLen = Soc_Aud_I2S_WLEN_WLEN_32BITS; } else { SetMemIfFetchFormatPerSample(Soc_Aud_Digital_Block_MEM_DL1, AFE_WLEN_16_BIT); SetMemIfFetchFormatPerSample(Soc_Aud_Digital_Block_MEM_DL2, AFE_WLEN_16_BIT); SetoutputConnectionFormat(OUTPUT_DATA_FORMAT_16BIT, Soc_Aud_InterConnectionOutput_O03); SetoutputConnectionFormat(OUTPUT_DATA_FORMAT_16BIT, Soc_Aud_InterConnectionOutput_O04); SetoutputConnectionFormat(OUTPUT_DATA_FORMAT_16BIT, Soc_Aud_InterConnectionOutput_O00); SetoutputConnectionFormat(OUTPUT_DATA_FORMAT_16BIT, Soc_Aud_InterConnectionOutput_O01); mI2SWLen = Soc_Aud_I2S_WLEN_WLEN_16BITS; } SetSampleRate(Soc_Aud_Digital_Block_MEM_I2S, runtime->rate); // I2S out Setting u32AudioI2S = SampleRateTransform(runtime->rate) << 8; u32AudioI2S |= Soc_Aud_I2S_FORMAT_I2S << 3; // us3 I2s format u32AudioI2S |= Soc_Aud_I2S_WLEN_WLEN_32BITS << 1; //32bit if (mI2S0dl1_hdoutput_control == true) { printk("%s mI2S0dl1_hdoutput_control == %d\n", __func__, mI2S0dl1_hdoutput_control); // open apll EnableApll(runtime->rate, true); EnableApllTuner(runtime->rate, true); MclkDiv3 = SetCLkMclk(Soc_Aud_I2S1, runtime->rate); //select I2S MclkDiv3 = SetCLkMclk(Soc_Aud_I2S3, runtime->rate); //Todo do we need open I2S3? //Following wil not affect hw. because I2S0-I2S3 BCK is generated by APLL1 DIV0 APLL2 Div0 SetCLkBclk(MclkDiv3, runtime->rate, runtime->channels, Soc_Aud_I2S_WLEN_WLEN_32BITS); EnableI2SDivPower(AUDIO_APLL12_DIV2, true); EnableI2SDivPower(AUDIO_APLL12_DIV4, true); //Todo do we need open I2S3? u32AudioI2S |= Soc_Aud_LOW_JITTER_CLOCK << 12 ; //Low jitter mode } else { u32AudioI2S &= ~(Soc_Aud_LOW_JITTER_CLOCK << 12) ; } if (GetMemoryPathEnable(Soc_Aud_Digital_Block_I2S_OUT_2) == false) { SetMemoryPathEnable(Soc_Aud_Digital_Block_I2S_OUT_2, true); //Afe_Set_Reg(AFE_I2S_CON, Audio_I2S_Dac | 0x1, MASK_ALL); //K2 TODO: fix fm playback then mp3, i2s_con is misconfigured... Afe_Set_Reg(AFE_I2S_CON3, u32AudioI2S | 1, AFE_MASK_ALL); } else { SetMemoryPathEnable(Soc_Aud_Digital_Block_I2S_OUT_2, true); } // start I2S DAC out if (GetMemoryPathEnable(Soc_Aud_Digital_Block_I2S_OUT_DAC) == false) { SetMemoryPathEnable(Soc_Aud_Digital_Block_I2S_OUT_DAC, true); SetI2SDacOut(substream->runtime->rate, mI2S0dl1_hdoutput_control, mI2SWLen); SetI2SDacEnable(true); } else { SetMemoryPathEnable(Soc_Aud_Digital_Block_I2S_OUT_DAC, true); } // here to set interrupt_distributor SetIrqMcuCounter(Soc_Aud_IRQ_MCU_MODE_IRQ1_MCU_MODE, runtime->period_size); SetIrqMcuSampleRate(Soc_Aud_IRQ_MCU_MODE_IRQ1_MCU_MODE, runtime->rate); EnableAfe(true); mPrepareDone = true; } return 0; }