void SetVRAM_Mirror( INT bank0, INT bank1, INT bank2, INT bank3 )
{
SetVRAM_1K_Bank( 8, bank0 );
SetVRAM_1K_Bank( 9, bank1 );
SetVRAM_1K_Bank( 10, bank2 );
SetVRAM_1K_Bank( 11, bank3 );
}
void Mapper185::Write( WORD addr, BYTE data )
{
if( (!patch && (data&0x03)) || (patch && data == 0x21) ) {
SetVROM_8K_Bank( 0 );
} else {
SetVRAM_1K_Bank( 0, 2 ); // use vram bank 2
SetVRAM_1K_Bank( 1, 2 );
SetVRAM_1K_Bank( 2, 2 );
SetVRAM_1K_Bank( 3, 2 );
SetVRAM_1K_Bank( 4, 2 );
SetVRAM_1K_Bank( 5, 2 );
SetVRAM_1K_Bank( 6, 2 );
SetVRAM_1K_Bank( 7, 2 );
}
}
void Mapper019::Write( WORD addr, BYTE data )
{
//if( addr >= 0xC000 ) {
//DEBUGOUT( "W %04X %02X L:%3d\n", addr, data, nes->GetScanline() );
//}
switch( addr & 0xF800 ) {
case 0x8000:
if( (data < 0xE0) || (reg[0] != 0) ) {
SetVROM_1K_Bank( 0, data );
} else {
SetCRAM_1K_Bank( 0, data&0x1F );
}
break;
case 0x8800:
if( (data < 0xE0) || (reg[0] != 0) ) {
SetVROM_1K_Bank( 1, data );
} else {
SetCRAM_1K_Bank( 1, data&0x1F );
}
break;
case 0x9000:
if( (data < 0xE0) || (reg[0] != 0) ) {
SetVROM_1K_Bank( 2, data );
} else {
SetCRAM_1K_Bank( 2, data&0x1F );
}
break;
case 0x9800:
if( (data < 0xE0) || (reg[0] != 0) ) {
SetVROM_1K_Bank( 3, data );
} else {
SetCRAM_1K_Bank( 3, data&0x1F );
}
break;
case 0xA000:
if( (data < 0xE0) || (reg[1] != 0) ) {
SetVROM_1K_Bank( 4, data );
} else {
SetCRAM_1K_Bank( 4, data&0x1F );
}
break;
case 0xA800:
if( (data < 0xE0) || (reg[1] != 0) ) {
SetVROM_1K_Bank( 5, data );
} else {
SetCRAM_1K_Bank( 5, data&0x1F );
}
break;
case 0xB000:
if( (data < 0xE0) || (reg[1] != 0) ) {
SetVROM_1K_Bank( 6, data );
} else {
SetCRAM_1K_Bank( 6, data&0x1F );
}
break;
case 0xB800:
if( (data < 0xE0) || (reg[1] != 0) ) {
SetVROM_1K_Bank( 7, data );
} else {
SetCRAM_1K_Bank( 7, data&0x1F );
}
break;
case 0xC000:
if( !patch ) {
if( data <= 0xDF ) {
SetVROM_1K_Bank( 8, data );
} else {
SetVRAM_1K_Bank( 8, data & 0x01 );
}
}
break;
case 0xC800:
if( !patch ) {
if( data <= 0xDF ) {
SetVROM_1K_Bank( 9, data );
} else {
SetVRAM_1K_Bank( 9, data & 0x01 );
}
}
break;
case 0xD000:
if( !patch ) {
if( data <= 0xDF ) {
SetVROM_1K_Bank( 10, data );
} else {
SetVRAM_1K_Bank( 10, data & 0x01 );
}
}
break;
case 0xD800:
if( !patch ) {
if( data <= 0xDF ) {
SetVROM_1K_Bank( 11, data );
} else {
SetVRAM_1K_Bank( 11, data & 0x01 );
}
}
break;
case 0xE000:
SetPROM_8K_Bank( 4, data & 0x3F );
if( patch == 2 ) {
if( data & 0x40 ) SetVRAM_Mirror( VRAM_VMIRROR );
else SetVRAM_Mirror( VRAM_MIRROR4L );
}
if( patch == 3 ) {
if( data & 0x80 ) SetVRAM_Mirror( VRAM_HMIRROR );
else SetVRAM_Mirror( VRAM_VMIRROR );
}
break;
case 0xE800:
reg[0] = data & 0x40;
reg[1] = data & 0x80;
SetPROM_8K_Bank( 5, data & 0x3F );
break;
case 0xF000:
SetPROM_8K_Bank( 6, data & 0x3F );
break;
case 0xF800:
if( addr == 0xF800 ) {
if( exsound_enable ) {
nes->apu->ExWrite( addr, data );
}
reg[2] = data;
}
break;
}
}
