/**Function*************************************************************
Synopsis [Interface with the FPGA mapping package.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
Abc_Ntk_t * Abc_NtkFpga( Abc_Ntk_t * pNtk, float DelayTarget, int fRecovery, int fSwitching, int fLatchPaths, int fVerbose )
{
int fShowSwitching = 1;
Abc_Ntk_t * pNtkNew;
Fpga_Man_t * pMan;
Vec_Int_t * vSwitching;
float * pSwitching = NULL;
assert( Abc_NtkIsStrash(pNtk) );
// print a warning about choice nodes
if ( Abc_NtkGetChoiceNum( pNtk ) )
printf( "Performing FPGA mapping with choices.\n" );
// compute switching activity
fShowSwitching |= fSwitching;
if ( fShowSwitching )
{
extern Vec_Int_t * Sim_NtkComputeSwitching( Abc_Ntk_t * pNtk, int nPatterns );
vSwitching = Sim_NtkComputeSwitching( pNtk, 4096 );
pSwitching = (float *)vSwitching->pArray;
}
// perform FPGA mapping
pMan = Abc_NtkToFpga( pNtk, fRecovery, pSwitching, fLatchPaths, fVerbose );
if ( pSwitching ) Vec_IntFree( vSwitching );
if ( pMan == NULL )
return NULL;
Fpga_ManSetSwitching( pMan, fSwitching );
Fpga_ManSetLatchPaths( pMan, fLatchPaths );
Fpga_ManSetLatchNum( pMan, Abc_NtkLatchNum(pNtk) );
Fpga_ManSetDelayTarget( pMan, DelayTarget );
if ( !Fpga_Mapping( pMan ) )
{
Fpga_ManFree( pMan );
return NULL;
}
// transform the result of mapping into a BDD network
pNtkNew = Abc_NtkFromFpga( pMan, pNtk );
if ( pNtkNew == NULL )
return NULL;
Fpga_ManFree( pMan );
// make the network minimum base
Abc_NtkMinimumBase( pNtkNew );
if ( pNtk->pExdc )
pNtkNew->pExdc = Abc_NtkDup( pNtk->pExdc );
// make sure that everything is okay
if ( !Abc_NtkCheck( pNtkNew ) )
{
printf( "Abc_NtkFpga: The network check has failed.\n" );
Abc_NtkDelete( pNtkNew );
return NULL;
}
return pNtkNew;
}
/**Function*************************************************************
Synopsis [Interface with the mapping package.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
Abc_Ntk_t * Abc_NtkMap( Abc_Ntk_t * pNtk, double DelayTarget, double AreaMulti, double DelayMulti, float LogFan, float Slew, float Gain, int nGatesMin, int fRecovery, int fSwitching, int fSkipFanout, int fVerbose )
{
static int fUseMulti = 0;
int fShowSwitching = 1;
Abc_Ntk_t * pNtkNew;
Map_Man_t * pMan;
Vec_Int_t * vSwitching = NULL;
float * pSwitching = NULL;
abctime clk, clkTotal = Abc_Clock();
Mio_Library_t * pLib = (Mio_Library_t *)Abc_FrameReadLibGen();
assert( Abc_NtkIsStrash(pNtk) );
// derive library from SCL
// if the library is created here, it will be deleted when pSuperLib is deleted in Map_SuperLibFree()
if ( Abc_FrameReadLibScl() && Abc_SclHasDelayInfo( Abc_FrameReadLibScl() ) )
{
pLib = Abc_SclDeriveGenlib( Abc_FrameReadLibScl(), Slew, Gain, nGatesMin, fVerbose );
if ( Abc_FrameReadLibGen() )
Mio_LibraryTransferDelays( (Mio_Library_t *)Abc_FrameReadLibGen(), pLib );
// remove supergate library
Map_SuperLibFree( (Map_SuperLib_t *)Abc_FrameReadLibSuper() );
Abc_FrameSetLibSuper( NULL );
}
// quit if there is no library
if ( pLib == NULL )
{
printf( "The current library is not available.\n" );
return 0;
}
if ( AreaMulti != 0.0 )
fUseMulti = 1, printf( "The cell areas are multiplied by the factor: <num_fanins> ^ (%.2f).\n", AreaMulti );
if ( DelayMulti != 0.0 )
fUseMulti = 1, printf( "The cell delays are multiplied by the factor: <num_fanins> ^ (%.2f).\n", DelayMulti );
// penalize large gates by increasing their area
if ( AreaMulti != 0.0 )
Mio_LibraryMultiArea( pLib, AreaMulti );
if ( DelayMulti != 0.0 )
Mio_LibraryMultiDelay( pLib, DelayMulti );
// derive the supergate library
if ( fUseMulti || Abc_FrameReadLibSuper() == NULL )
{
if ( fVerbose )
printf( "Converting \"%s\" into supergate library \"%s\".\n",
Mio_LibraryReadName(pLib), Extra_FileNameGenericAppend(Mio_LibraryReadName(pLib), ".super") );
// compute supergate library to be used for mapping
Map_SuperLibDeriveFromGenlib( pLib, fVerbose );
}
// return the library to normal
if ( AreaMulti != 0.0 )
Mio_LibraryMultiArea( (Mio_Library_t *)Abc_FrameReadLibGen(), -AreaMulti );
if ( DelayMulti != 0.0 )
Mio_LibraryMultiDelay( (Mio_Library_t *)Abc_FrameReadLibGen(), -DelayMulti );
// print a warning about choice nodes
if ( fVerbose && Abc_NtkGetChoiceNum( pNtk ) )
printf( "Performing mapping with choices.\n" );
// compute switching activity
fShowSwitching |= fSwitching;
if ( fShowSwitching )
{
extern Vec_Int_t * Sim_NtkComputeSwitching( Abc_Ntk_t * pNtk, int nPatterns );
vSwitching = Sim_NtkComputeSwitching( pNtk, 4096 );
pSwitching = (float *)vSwitching->pArray;
}
// perform the mapping
pMan = Abc_NtkToMap( pNtk, DelayTarget, fRecovery, pSwitching, fVerbose );
if ( pSwitching ) Vec_IntFree( vSwitching );
if ( pMan == NULL )
return NULL;
clk = Abc_Clock();
Map_ManSetSwitching( pMan, fSwitching );
Map_ManSetSkipFanout( pMan, fSkipFanout );
if ( LogFan != 0 )
Map_ManCreateNodeDelays( pMan, LogFan );
if ( !Map_Mapping( pMan ) )
{
Map_ManFree( pMan );
return NULL;
}
// Map_ManPrintStatsToFile( pNtk->pSpec, Map_ManReadAreaFinal(pMan), Map_ManReadRequiredGlo(pMan), Abc_Clock()-clk );
// reconstruct the network after mapping
pNtkNew = Abc_NtkFromMap( pMan, pNtk );
Map_ManFree( pMan );
if ( pNtkNew == NULL )
return NULL;
if ( pNtk->pExdc )
pNtkNew->pExdc = Abc_NtkDup( pNtk->pExdc );
if ( fVerbose )
{
ABC_PRT( "Total runtime", Abc_Clock() - clkTotal );
}
// make sure that everything is okay
if ( !Abc_NtkCheck( pNtkNew ) )
{
printf( "Abc_NtkMap: The network check has failed.\n" );
Abc_NtkDelete( pNtkNew );
return NULL;
}
return pNtkNew;
}
