void spi_transmit(spi_package* package) {
int temp;
unsigned cpsr;
temp = (spi_package_buffer_insert_idx + 1) % SPI_PACKAGE_BUFFER_SIZE; // calculate the next queue position
if (temp == spi_package_buffer_extract_idx) { // check if there is free space in the send queue
return; // no room
}
cpsr = disableIRQ(); // disable global interrupts
SpiDisableRti(); // disable RTI interrupts
restoreIRQ(cpsr); // restore global interrupts
spi_package_buffer[spi_package_buffer_insert_idx] = *package; // add data to queue
spi_package_buffer_insert_idx = temp; // increase insert pointer
if (spi_transmit_running==0) // check if in process of sending data
{
spi_transmit_running = 1; // set running flag
spi_transmit_single_package(&spi_package_buffer[spi_package_buffer_extract_idx]);
spi_package_buffer_extract_idx++;
spi_package_buffer_extract_idx %= SPI_PACKAGE_BUFFER_SIZE;
}
cpsr = disableIRQ(); // disable global interrupts
SpiEnableRti(); // enable RTI interrupts
restoreIRQ(cpsr); // restore global interrupts
}
void SPI1_ISR(void) {
ISR_ENTRY();
if (bit_is_set(SSPMIS, TXMIS)) { /* Tx half empty */
SpiTransmit();
SpiReceive();
SpiEnableRti();
}
if ( bit_is_set(SSPMIS, RTMIS)) { /* Rx timeout */
SpiReceive();
SpiClearRti(); /* clear interrupt */
SpiDisableRti();
SpiDisable();
spi_message_received = TRUE;
}
VICVectAddr = 0x00000000; /* clear this interrupt from the VIC */
ISR_EXIT();
}
void SPI1_ISR(void) {
ISR_ENTRY();
if (bit_is_set(SSPMIS, TXMIS)) { /* Tx fifo is half empty */
SpiTransmit();
SpiReceive();
SpiEnableRti();
}
if (bit_is_set(SSPMIS, RTMIS)) { /* Rx fifo is not empty and no receive took place in the last 32 bits period */
SpiUnselectCurrentSlave();
SpiReceive();
SpiDisableRti();
SpiClearRti(); /* clear interrupt */
SpiDisable();
spi_message_received = TRUE;
}
VICVectAddr = 0x00000000; /* clear this interrupt from the VIC */
ISR_EXIT();
}
static void SSP_ISR(void) {
ISR_ENTRY();
//start the device interrupt handler
(*spi_current_package).spi_interrupt_handler();
//unselect device, disable spi
(*spi_current_package).slave_unselect();
SpiClearRti();
SpiDisableRti();
SpiDisable();
// check if more data to send
if (spi_package_buffer_insert_idx != spi_package_buffer_extract_idx) {
spi_transmit_single_package(&spi_package_buffer[spi_package_buffer_extract_idx]);
spi_package_buffer_extract_idx++;
spi_package_buffer_extract_idx %= SPI_PACKAGE_BUFFER_SIZE;
} else {
spi_transmit_running = 0; // clear running flag
}
VICVectAddr = 0x00000000; /* clear this interrupt from the VIC */
ISR_EXIT();
}
void SPI1_ISR(void) {
ISR_ENTRY();
while (bit_is_set(SSPSR, RNE)) {
uint16_t data = SSPDR;
if (bit_is_set(data, MAX3100_R_BIT)) { /* Data available */
max3100_rx_buf[max3100_rx_insert_idx] = data & 0xff;
max3100_rx_insert_idx++; // automatic overflow because len=256
read_bytes = true;
}
if (bit_is_set(data, MAX3100_T_BIT) && (max3100_status == MAX3100_STATUS_READING)) { /* transmit buffer empty */
max3100_transmit_buffer_empty = true;
}
}
SpiClearRti(); /* clear interrupt */
SpiDisableRti();
SpiDisable ();
Max3100Unselect();
max3100_status = MAX3100_STATUS_IDLE;
VICVectAddr = 0x00000000; /* clear this interrupt from the VIC */
ISR_EXIT();
}
