/************************************************************************************************** * @fn SysCtrlDeepSleepSetting * * @brief Setup which peripherals are enabled/disabled in Deep Sleep * * input parameters * * @param None. * * output parameters * * None. * * @return None. ************************************************************************************************** */ void SysCtrlDeepSleepSetting(void) { /* Disable General Purpose Timers 0, 1, 2, 3 during deep sleep */ SysCtrlPeripheralDeepSleepDisable(SYS_CTRL_PERIPH_GPT0); SysCtrlPeripheralDeepSleepDisable(SYS_CTRL_PERIPH_GPT1); SysCtrlPeripheralDeepSleepDisable(SYS_CTRL_PERIPH_GPT2); SysCtrlPeripheralDeepSleepDisable(SYS_CTRL_PERIPH_GPT3); /* Disable SSI 0, 1 during deep sleep */ SysCtrlPeripheralDeepSleepEnable(SYS_CTRL_PERIPH_SSI0); SysCtrlPeripheralDeepSleepDisable(SYS_CTRL_PERIPH_SSI1); /* Disable UART 0, 1 during deep sleep */ SysCtrlPeripheralDeepSleepDisable(SYS_CTRL_PERIPH_UART0); SysCtrlPeripheralDeepSleepEnable(SYS_CTRL_PERIPH_UART1); /* Disable I2C, PKA, AES during deep sleep */ SysCtrlPeripheralDeepSleepDisable(SYS_CTRL_PERIPH_I2C); SysCtrlPeripheralDeepSleepDisable(SYS_CTRL_PERIPH_PKA); SysCtrlPeripheralDeepSleepDisable(SYS_CTRL_PERIPH_AES); /* * Disable RFC during deep sleep. Please note that this setting is * only valid for PG2.0. For PG1.0 this is just a dummy instruction. */ SysCtrlPeripheralDeepSleepDisable(SYS_CTRL_PERIPH_RFC); }
/* * Public API */ void ws_radio_init(void) { WS_DEBUG("init\n"); /* Reset state */ memset(&radio_state, 0, sizeof(radio_state)); /* Enable the clock */ /* TODO: Power saving. We're basically leaving the radio on all the time */ SysCtrlPeripheralReset(SYS_CTRL_PERIPH_RFC); SysCtrlPeripheralEnable(SYS_CTRL_PERIPH_RFC); SysCtrlPeripheralSleepEnable(SYS_CTRL_PERIPH_RFC); SysCtrlPeripheralDeepSleepEnable(SYS_CTRL_PERIPH_RFC); /* Configure CCA */ HWREG(RFCORE_XREG_CCACTRL0) = CC2538_RFCORE_CCA_THRES; /* User Manual 23.15 - TX and RX settings */ HWREG(RFCORE_XREG_AGCCTRL1) = CC2538_RFCORE_AGC_TARGET; HWREG(RFCORE_XREG_TXFILTCFG) = CC2538_RFCORE_TX_AA_FILTER; HWREG(ANA_REGS_BASE + ANA_REGS_O_IVCTRL) = CC2538_RFCORE_BIAS_CURRENT; HWREG(RFCORE_XREG_FSCAL1) = CC2538_RFCORE_FREQ_CAL; /* Enable auto CRC calculation (hardware) */ HWREG(RFCORE_XREG_FRMCTRL0) = RFCORE_XREG_FRMCTRL0_AUTOCRC; /* Enable auto ACK */ HWREG(RFCORE_XREG_FRMCTRL0) |= RFCORE_XREG_FRMCTRL0_AUTOACK; /* Configure the FIFOP signal to trigger when there are one or more * complete frames in the RX FIFO */ HWREG(RFCORE_XREG_FIFOPCTRL) = WS_RADIO_MAX_PACKET_LEN; /* Set the TX output power */ HWREG(RFCORE_XREG_TXPOWER) = CC2538_RFCORE_TX_POWER; /* Interrupt wth FIFOP signal */ HWREG(RFCORE_XREG_RFIRQM0) = 0x04; IntRegister(INT_RFCORERTX, &rf_isr); IntEnable(INT_RFCORERTX); /* Interrupt with all RF ERROR signals */ HWREG(RFCORE_XREG_RFERRM) = 0x7f; IntRegister(INT_RFCOREERR, &rf_err_isr); IntEnable(INT_RFCOREERR); /* Configure the frame filtering */ HWREG(RFCORE_XREG_FRMFILT0) &= ~RFCORE_XREG_FRMFILT0_MAX_FRAME_VERSION_M; HWREG(RFCORE_XREG_FRMFILT0) |= WS_MAC_MAX_FRAME_VERSION << RFCORE_XREG_FRMFILT0_MAX_FRAME_VERSION_S; /* Don't bother filtering out the source addresses */ HWREG(RFCORE_XREG_SRCMATCH) &= ~RFCORE_XREG_SRCMATCH_SRC_MATCH_EN; }