int timer_init(tim_t dev, unsigned int ticks_per_us, void (*callback)(int))
{
TIM_TimeBaseInitTypeDef tim_init;
NVIC_InitTypeDef nvic_init;
/* init generic timer options */
tim_init.TIM_ClockDivision = TIM_CKD_DIV1;
tim_init.TIM_CounterMode = TIM_CounterMode_Up;
/* setup the interrupt controller */
nvic_init.NVIC_IRQChannelCmd = ENABLE;
nvic_init.NVIC_IRQChannelSubPriority = 0;
/* set callback routine */
config[dev].cb = callback;
switch (dev) {
case TIMER_0:
/* enable clocks */
TIMER_0_CLKEN();
/* timer init */
tim_init.TIM_Period = TIMER_0_MAX_VALUE;
tim_init.TIM_Prescaler = TIMER_0_PRESCALER * ticks_per_us;
TIM_TimeBaseInit(TIMER_0_DEV, &tim_init);
/* irq setup */
nvic_init.NVIC_IRQChannel = TIMER_0_IRQCHAN;
nvic_init.NVIC_IRQChannelPreemptionPriority = TIMER_0_IRQ_PRIO;
NVIC_Init(&nvic_init);
/* enable timer */
TIM_Cmd(TIMER_0_DEV, ENABLE);
/* clear the compare IT bits else first hwtimer_set for each channel fires instantly*/
TIM_ClearITPendingBit(TIMER_0_DEV, TIM_IT_CC1);
TIM_ClearITPendingBit(TIMER_0_DEV, TIM_IT_CC2);
TIM_ClearITPendingBit(TIMER_0_DEV, TIM_IT_CC3);
TIM_ClearITPendingBit(TIMER_0_DEV, TIM_IT_CC4);
break;
case TIMER_1:
/* enable clocks */
TIMER_1_CLKEN();
/* timer init */
tim_init.TIM_Period = TIMER_1_MAX_VALUE;
tim_init.TIM_Prescaler = TIMER_1_PRESCALER * ticks_per_us;
TIM_TimeBaseInit(TIMER_1_DEV, &tim_init);
/* irq setup */
nvic_init.NVIC_IRQChannel = TIMER_1_IRQCHAN;
nvic_init.NVIC_IRQChannelPreemptionPriority = TIMER_1_IRQ_PRIO;
NVIC_Init(&nvic_init);
/* enable timer */
TIM_Cmd(TIMER_1_DEV, ENABLE);
/* clear the compare IT bits else first hwtimer_set for each channel fires instantly*/
TIM_ClearITPendingBit(TIMER_1_DEV, TIM_IT_CC1);
TIM_ClearITPendingBit(TIMER_1_DEV, TIM_IT_CC2);
TIM_ClearITPendingBit(TIMER_1_DEV, TIM_IT_CC3);
TIM_ClearITPendingBit(TIMER_1_DEV, TIM_IT_CC4);
break;
default:
return -1;
}
return 0;
}
int timer_init(tim_t dev, unsigned long freq, timer_cb_t cb, void *arg)
{
TIM_TypeDef *timer;
switch (dev) {
#if TIMER_0_EN
case TIMER_0:
/* enable timer peripheral clock */
TIMER_0_CLKEN();
/* set timer's IRQ priority */
NVIC_SetPriority(TIMER_0_IRQ_CHAN, TIMER_IRQ_PRIO);
/* select timer */
timer = TIMER_0_DEV;
break;
#endif
#if TIMER_1_EN
case TIMER_1:
/* enable timer peripheral clock */
TIMER_1_CLKEN();
/* set timer's IRQ priority */
NVIC_SetPriority(TIMER_1_IRQ_CHAN, TIMER_IRQ_PRIO);
/* select timer */
timer = TIMER_1_DEV;
break;
#endif
case TIMER_UNDEFINED:
default:
return -1;
}
/* set callback function */
config[dev].cb = cb;
config[dev].arg = arg;
/* set timer to run in counter mode */
timer->CR1 |= TIM_CR1_URS;
/* set auto-reload and prescaler values and load new values */
timer->ARR = TIMER_0_MAX_VALUE;
timer->PSC = (TIMER_0_FREQ / freq) - 1;
timer->EGR |= TIM_EGR_UG;
/* enable the timer's interrupt */
timer_irq_enable(dev);
/* start the timer */
timer_start(dev);
return 0;
}
int timer_init(tim_t dev, unsigned int us_per_tick, void (*callback)(int))
{
if (dev == TIMER_0) {
/* save callback */
config[TIMER_0].cb = callback;
/* enable power for timer */
TIMER_0_CLKEN();
/* set to timer mode */
TIMER_0_DEV->CTCR = 0;
/* configure prescaler */
TIMER_0_DEV->PR = (us_per_tick * TIMER_0_PRESCALER);
/* configure and enable timer interrupts */
NVIC_SetPriority(TIMER_0_IRQ, TIMER_IRQ_PRIO);
NVIC_EnableIRQ(TIMER_0_IRQ);
/* enable timer */
TIMER_0_DEV->TCR |= 1;
return 0;
}
return -1;
}
int timer_init(tim_t dev, unsigned long freq, timer_cb_t cb, void *arg)
{
if (dev == TIMER_0) {
/* save callback */
config[TIMER_0].cb = cb;
config[TIMER_0].arg = arg;
/* enable power for timer */
TIMER_0_CLKEN();
/* set to timer mode */
TIMER_0_DEV->CTCR = 0;
/* configure prescaler */
TIMER_0_DEV->PR = (TIMER_0_FREQ / freq) - 1;
/* configure and enable timer interrupts */
NVIC_SetPriority(TIMER_0_IRQ, TIMER_IRQ_PRIO);
NVIC_EnableIRQ(TIMER_0_IRQ);
/* enable timer */
TIMER_0_DEV->TCR |= 1;
return 0;
}
return -1;
}
int timer_init(tim_t dev, unsigned int ticks_per_us, void (*callback)(int))
{
TIM_TypeDef *timer;
switch (dev) {
#if TIMER_0_EN
case TIMER_0:
/* enable timer peripheral clock */
TIMER_0_CLKEN();
/* set timer's IRQ priority */
NVIC_SetPriority(TIMER_0_IRQ_CHAN, TIMER_IRQ_PRIO);
/* select timer */
timer = TIMER_0_DEV;
break;
#endif
case TIMER_UNDEFINED:
default:
return -1;
}
/* set callback function */
config[dev].cb = callback;
/* set timer to run in counter mode */
timer->CR1 = 0;
timer->CR2 = 0;
/* set auto-reload and prescaler values and load new values */
timer->PSC = TIMER_0_PRESCALER * ticks_per_us;
timer->EGR |= TIM_EGR_UG;
/* enable the timer's interrupt */
timer_irq_enable(dev);
/* start the timer */
timer_start(dev);
return 0;
}
int timer_init(tim_t dev, unsigned int ticks_per_us, void (*callback)(int))
{
TIM_TypeDef *timer0;
TIM_TypeDef *timer1;
uint8_t trigger_selector;
switch (dev) {
#if TIMER_0_EN
case TIMER_0:
/* enable timer peripheral clock */
TIMER_0_CLKEN();
/* set timer's IRQ priority */
NVIC_SetPriority(TIMER_0_IRQ_CHAN_0, TIMER_0_IRQ_PRIO);
NVIC_SetPriority(TIMER_0_IRQ_CHAN_1, TIMER_0_IRQ_PRIO);
/* select timer */
timer0 = TIMER_0_DEV_0;
timer1 = TIMER_0_DEV_1;
trigger_selector = TIMER_0_TRIG_SEL;
break;
#endif
#if TIMER_1_EN
case TIMER_1:
/* enable timer peripheral clock */
TIMER_1_CLKEN();
/* set timer's IRQ priority */
NVIC_SetPriority(TIMER_1_IRQ_CHAN_0, TIMER_1_IRQ_PRIO);
NVIC_SetPriority(TIMER_1_IRQ_CHAN_1, TIMER_1_IRQ_PRIO);
/* select timer */
timer0 = TIMER_1_DEV_0;
timer1 = TIMER_1_DEV_1;
trigger_selector = TIMER_1_TRIG_SEL;
break;
#endif
case TIMER_UNDEFINED:
default:
return -1;
}
/* set callback function */
config[dev].cb = callback;
/* set timer to run in counter mode */
timer0->CR1 = (TIM_CR1_ARPE | TIM_CR1_URS);
timer1->CR1 = TIM_CR1_URS;
/* configure master timer0 */
/* send update event as trigger output */
timer0->CR2 |= TIM_CR2_MMS_1;
/* set auto-reload and prescaler values and load new values */
timer0->ARR = TIMER_0_MAX_VALUE;
timer0->PSC = TIMER_0_PRESCALER * ticks_per_us;
// timer->EGR |= TIM_EGR_UG;
/* configure slave timer1 */
/* get input trigger */
timer1->SMCR |= trigger_selector;
/* external clock mode 1 */
timer1->SMCR |= TIM_SMCR_SMS;
/* enable the timer's interrupt */
timer_irq_enable(dev);
/* start the timer */
timer_start(dev);
return 0;
}
