/*********************************************************************** * * Function: timer1_user_interrupt * * Purpose: Timer 1 interrupt handler * * Processing: * See function. * * Parameters: None * * Outputs: None * * Returns: Nothing * * Notes: None * **********************************************************************/ void timer1_user_interrupt(void) { /* Clear latched timer interrupt */ timer_ioctl(timer1dev, TMR_CLEAR_INTS, TIMER_CNTR_MTCH_BIT(0)); /* Turn off LED1 */ fdi3250_toggle_led(FALSE); }
/*********************************************************************** * * Function: timer0_user_interrupt * * Purpose: Timer 0 interrupt handler * * Processing: * See function. * * Parameters: None * * Outputs: None * * Returns: Nothing * * Notes: None * **********************************************************************/ void timer0_user_interrupt(void) { /* Clear latched timer interrupt */ timer_ioctl(timer0dev, TMR_CLEAR_INTS, TIMER_CNTR_MTCH_BIT(0)); /* Turn on LED1 */ fdi3250_toggle_led(TRUE); msecs += 100; }
/*********************************************************************** * * Function: timer1_user_interrupt * * Purpose: Timer 1 interrupt handler * * Processing: * See function. * * Parameters: None * * Outputs: None * * Returns: Nothing * * Notes: None * **********************************************************************/ void timer1_user_interrupt(void) { /* Clear latched timer interrupt */ timer_ioctl(timer1dev, TMR_CLEAR_INTS, TIMER_CNTR_MTCH_BIT(0)); /* Turn off LED1 */ // phy3250_toggle_led(FALSE); gpio_set_gpo_state(0x00, 1<<14); //turn-off LED1 /* if (ch[0] == '1') gpio_set_gpo_state(1<<14, 0x00); //turn-on LED1 else if (ch[0] == '2') gpio_set_gpo_state(0x00, 1<<14); //turn-off LED1 else if (ch[0] == '3') gpio_set_gpo_state(1<<1, 0x00); //turn-on LED2 else if (ch[0] == '4') gpio_set_gpo_state(0x00, 1<<1); //turn-off LED2 */ }
/*********************************************************************** * * Function: c_entry * * Purpose: Application entry point from the startup code * * Processing: * See function. * * Parameters: None * * Outputs: None * * Returns: Always returns 1 * * Notes: None * **********************************************************************/ int c_entry(void) { TMR_PSCALE_SETUP_T pscale; TMR_MATCH_SETUP_T msetup; /* Disable interrupts in ARM core */ disable_irq_fiq(); /* Set virtual address of MMU table */ cp15_set_vmmu_addr((void *) (IRAM_BASE + (256 * 1024) - (16 * 1024))); /* Initialize interrupt system */ int_initialize(0xFFFFFFFF); /* Install standard IRQ dispatcher at ARM IRQ vector */ int_install_arm_vec_handler(IRQ_VEC, (PFV) lpc32xx_irq_handler); /* Install timer interrupts handlers as a IRQ interrupts */ int_install_irq_handler(IRQ_TIMER0, (PFV) timer0_user_interrupt); int_install_irq_handler(IRQ_TIMER1, (PFV) timer1_user_interrupt); /* Open timers - this will enable the clocks for all timers when match control, match output, and capture control functions disabled. Default clock will be internal. */ timer0dev = timer_open(TIMER_CNTR0, 0); timer1dev = timer_open(TIMER_CNTR1, 0); /******************************************************************/ /* Setup timer 0 for a 10Hz match rate */ /* Use a prescale count time of 100uS */ pscale.ps_tick_val = 0; /* Use ps_us_val value */ pscale.ps_us_val = 100; /* 100uS */ timer_ioctl(timer0dev, TMR_SETUP_PSCALE, (INT_32) &pscale); /* Use a match count value of 1000 (1000 * 100uS = 100mS (10Hz)) */ msetup.timer_num = 0; /* Use match register set 0 (of 0..3) */ msetup.use_match_int = TRUE; /* Generate match interrupt on match */ msetup.stop_on_match = FALSE; /* Do not stop timer on match */ msetup.reset_on_match = TRUE; /* Reset timer counter on match */ msetup.match_tick_val = 999; /* Match is when timer count is 1000 */ timer_ioctl(timer0dev, TMR_SETUP_MATCH, (INT_32) &msetup); /* Clear any latched timer 0 interrupts and enable match interrupt */ timer_ioctl(timer0dev, TMR_CLEAR_INTS, (TIMER_CNTR_MTCH_BIT(0) | TIMER_CNTR_MTCH_BIT(1) | TIMER_CNTR_MTCH_BIT(2) | TIMER_CNTR_MTCH_BIT(3) | TIMER_CNTR_CAPT_BIT(0) | TIMER_CNTR_CAPT_BIT(1) | TIMER_CNTR_CAPT_BIT(2) | TIMER_CNTR_CAPT_BIT(3))); /******************************************************************/ /******************************************************************/ /* Setup timer 1 for a 4.9Hz match rate */ /* Use a prescale count time of 100uS */ pscale.ps_tick_val = 0; /* Use ps_us_val value */ pscale.ps_us_val = 10; /* 100uS */ timer_ioctl(timer1dev, TMR_SETUP_PSCALE, (INT_32) &pscale); /* Use a match value of 490 (490 * 100uS) */ msetup.timer_num = 0; /* Use match register set 0 (of 0..3) */ msetup.use_match_int = TRUE; /* Generate match interrupt on match */ msetup.stop_on_match = FALSE; /* Do not stop timer on match */ msetup.reset_on_match = TRUE; /* Reset timer counter on match */ msetup.match_tick_val = 489; timer_ioctl(timer1dev, TMR_SETUP_MATCH, (INT_32) &msetup); /* Clear any latched timer 1 interrupts and enable match interrupt */ timer_ioctl(timer1dev, TMR_CLEAR_INTS, (TIMER_CNTR_MTCH_BIT(0) | TIMER_CNTR_MTCH_BIT(1) | TIMER_CNTR_MTCH_BIT(2) | TIMER_CNTR_MTCH_BIT(3) | TIMER_CNTR_CAPT_BIT(0) | TIMER_CNTR_CAPT_BIT(1) | TIMER_CNTR_CAPT_BIT(2) | TIMER_CNTR_CAPT_BIT(3))); /******************************************************************/ /* Enable timers (starts counting) */ msecs = 0; timer_ioctl(timer0dev, TMR_ENABLE, 1); timer_ioctl(timer1dev, TMR_ENABLE, 1); /* Enable timer interrupts in the interrupt controller */ int_enable(IRQ_TIMER0); int_enable(IRQ_TIMER1); /* Enable IRQ interrupts in the ARM core */ enable_irq(); /* Loop for 20 seconds and let interrupts toggle the LEDs */ while (msecs < (10 * 1000)); /* Disable timer interrupts in the interrupt controller */ int_disable(IRQ_TIMER0); int_disable(IRQ_TIMER1); /* Disable interrupts in ARM core */ disable_irq_fiq(); /* Close timers */ timer_close(timer0dev); timer_close(timer1dev); return 1; }
void ici_hdw_init(void) { //register long i; UART_CBS_T cbs; UART_CONTROL_T ucntl; //- typedef enum //- { //- UART_PAR_NONE, //- UART_PAR_EVEN, //- UART_PAR_ODD //- } UART_PAR_T; //- //- /* UART control */ //- typedef struct //- { //- UNS_32 baud_rate; /* Device baud rate */ //- UART_PAR_T parity; /* Parity selection */ //- UNS_32 databits; /* Number of data bits */ //- UNS_32 stopbits; /* Number of stop bits */ //- } UART_CONTROL_T; timer0dev = Timer_open(TIMER_CNTR0, 0); TIMER_CNTR_REGS_T *pTimer = TIMER_CNTR0; /* //-* Reset timer *-/ pTimer->tcr = TIMER_CNTR_TCR_RESET; pTimer->tcr = 0; //-* Count mode is PCLK edge *-/ pTimer->ctcr = TIMER_CNTR_SET_MODE(TIMER_CNTR_CTCR_TIMER_MODE); //-* Set prescale counter value for a 1uS tick *-/ pTimer->pr = (UNS_32) Timer_usec_to_val( CLKPWR_TIMER0_CLK, 1); //case TMR_VALUE_ST: // status = pTimer->tc; // break; //-* Enable the timer *-/ pTimer->tcr = TIMER_CNTR_TCR_EN; //-* Stop timer *-/ //pTimer->tcr = 0; */ //Init Module New //-* Enable timer system clock *-/ //.clkpwr_clk_en_dis(timer_num_to_clk_enum[timernum], 1); //-* Reset timer *-/ pTimer->tcr = TIMER_CNTR_TCR_RESET; pTimer->tcr = 0;pTimer->tc = 0; //-* Clear and enable match function *-/ pTimer->ir = TIMER_CNTR_MTCH_BIT(0); //-* Count mode is PCLK edge *-/ pTimer->ctcr = TIMER_CNTR_SET_MODE(TIMER_CNTR_CTCR_TIMER_MODE); //-* Set prescale counter value for a 1uS tick *-/ pTimer->pr = (UNS_32) Timer_usec_to_val( CLKPWR_TIMER0_CLK, 1); //-* Set match for number of usecs *-/ pTimer->mr[0] = 20000;//-usec; //-* Interrupt on match 0 *-/ pTimer->mcr = TIMER_CNTR_MCR_MTCH(0)|TIMER_CNTR_MCR_RESET(0); //-* Install timer interrupts handlers as a IRQ interrupts *-/ int_install_irq_handler(IRQ_TIMER0, (PFV) timer0_user_interrupt); //~ ucntl.baud_rate = 115200; //~ ucntl.parity = UART_PAR_NONE; //~ ucntl.databits = 8; //~ ucntl.stopbits = 1; //~ uartdev = Uart_open((void *) UART3, (INT_32) & ucntl); //~ if (uartdev != 0) //~ { //~ /* Setup RX and TX callbacks */ //~ cbs.rxcb = recv_cb; //~ cbs.txcb = send_cb; //~ cbs.rxerrcb = NULL; //~ Uart_ioctl(uartdev, UART_INSTALL_CBS, (INT_32) &cbs); //~ //.int_enable(IRQ_UART_IIR3); //~ } //~ //~ /* Initialize TX and RX ring buffers */ //~ //txfill = txget = rxfill = rxget = txsize = rxsize = 0; //~ Rst_LpduHSU2_TpCnState(); //~ /* Enable interrupts */ //~ int_enable(IRQ_UART_IIR3); //~ hs7_uart_hdw_init(); //~ hs1_uart_hdw_init(); //~ hs2_uart_hdw_init(); //~ //~ enable_irq(); //~ //int_enable(IRQ_UART_IIR7); //~ int_enable(IRQ_UART_IIR1); //~ int_enable(IRQ_UART_IIR2); ssp1_hdr_init(); Rst_LpduM2m_TpCnState(); Rst_LpduSpi_TpCnState(); GPIO->p0_mux_clr = 0xff; GPIO->p0_dir_clr = 0xff; GPIO->p0_dir_set = 0xf0; GPIO->p0_outp_clr =0xf0; M16_J18_K18_A15_PioInit(); //p3_outp_state AppReqTransmitTotVerInfoBrBs = 1; Int_install_ext_irq_handler(IRQ_GPIO_01,P02Int,FALLING_EDGE,0);//Interrupt in this place never can be workd look p606 datasheet - Only pin sic[8] activated Int_install_ext_irq_handler(IRQ_P0_P1_IRQ,P02Int,FALLING_EDGE,0); CLKPWR ->clkpwr_p01_er = CLKPWR_INTSRC_GPIO_01_BIT;// *((long*)0x40004018) |= 2; Int_enable(IRQ_GPIO_01); Int_enable(IRQ_P0_P1_IRQ); MIC->er |= (1<<(IRQ_SUB2IRQ)); //~^ pTimer->tcr = TIMER_CNTR_TCR_EN;//timer_ioctl(timer0dev, TMR_ENABLE, 1); //~^ int_enable(IRQ_TIMER0); }
long Samples_Ready_Handler(void* pv) { register long i=0;unsigned long uVl; register long j; if (samples_data_rdy & 0x20000) { samples_data_rdy = 0; //i = outU3((unsigned char*)DemoStr, 11); //i = outU7((unsigned char*)DemoStr, 2); //ActivateProxyTotMeas(); //TestActivateTransport(); //ActivatePrMngSettings(); // //TestSetup_SrcSamples_ForTransmit();// // ActivateProxyTenPerSamples(); //..TestSetup_LpduHSU7_ForTransmit(); //..ProcessTransmitLpduHSU7(); } //PrepDecompouseSrcSamplesUnit();- Move to Another function if( IciCopy_samples_data_rdy!=samples_data_rdy ) { lTmrDisableHSU2 ++; IciCopy_samples_data_rdy = samples_data_rdy; if (hldrHSU2LpduTRUnit.uchLpuHSU2State) { //Timer Halt - Need Reinit Timer System if(lTmrDisableHSU2 >= 4)//if(lTmrDisableHSU2>lDelta) { hldrHSU2LpduTRUnit.uchLpuHSU2State = 0;lMaxTimeTransmit = 0;//goto TstLab; RstTmr0(); lTmrDisableHSU2 = 0; } } else lTmrDisableHSU2--; lTmrAcivatorRawSamples++; if(lTmrAcivatorRawSamples>1) { lTmrAcivatorRawSamples = 0; chStartAppMoule++; } //Activator Transmit tot_Meas lTmrAcivatorTotMeasG++; if (lTmrAcivatorTotMeasG>= 500)//60) { lTmrAcivatorTotMeasG = 0; //Activate Transmit AppReqTransmitTotMeasG++; //AppReqTransmitTotMeasR = 1;//++; } //TestSetup_SrcSamples_ForTransmit();//Activate Transmit Samples //.uVl = ((TIMER_CNTR_REGS_T *)TIMER_CNTR0)-> tc; //.if (uVl>=lMaxTimeTransmit) //.{ //.i = uVl- (unsigned long)lMaxTimeTransmit; //. if (i<0x10000) //. i++; //.} //.else //.{ //. i = (-1) - (unsigned long)lMaxTimeTransmit; <- THIS IS FOR TEST ONLY TOO BUT IS WORKED //. i += uVl; //. i = ~i; //.} //.lMaxTimeTransmit = (long) uVl; //. } if (chStartAppMoule>=1)//Down Frequency { //Activate Transmit if(AppReqTransmitRawSampl>0) { //AppReqTransmitRawSampl +=2;Wait } else { if (chStartAppMoule>0) chStartAppMoule--;// = 0; AppReqTransmitRawSampl++; //if(AppReqTransmitTotMeasR == 0) //AppReqTransmitTotMeasR = 1;//++; //Send Data To Relay } } //.uVl = ((TIMER_CNTR_REGS_T *)TIMER_CNTR0)-> tc; //. //. if (uVl>=lMaxTimeTransmit) //. { //. i = uVl- (unsigned long)lMaxTimeTransmit; //. if (i<0x10000) //. i++; //. } //. else //. { //. i = (-1) - (unsigned long)lMaxTimeTransmit; <- THIS IS FOR TEST ONLY //. i += uVl; //. i = ~i; //. } //. lMaxTimeTransmit = (long) uVl; //. //Timer_delay_cmn(TIMER_CNTR0,10) ; //TimeOut for HSU2 /* j = lTmrHSU2Val;//for Exlude die in interrupt uVl = ((TIMER_CNTR_REGS_T *)TIMER_CNTR0)-> tc; if (uVl>= j)//lTmrHSU2Val i = uVl- (unsigned long)j;//lTmrHSU2Val; else { if(((long)uVl)>0)//Move from Zero { if (j<0)//lTmrHSU2Val { i = (-1)*j;//lTmrHSU2Val; i +=uVl; } else goto Err; } else { Err: i = 0;//error Variables } //i = (-1) - (unsigned long)lTmrHSU2Val; //i += uVl; //i = ~i; } if (hldrHSU2LpduTRUnit.uchLpuHSU2State)//&&(hs2_txsize==0) { if(hs2_txsize) lTmrHSU2Val = uVl;//Reset counter else { if (i>lDeltaTmrHSU2*3) i++;//Detect distance if( (i>lDeltaTmrHSU2)&&lMaxTimeTransmit) { if (hs2_txsize==0)//You can insert in this place additonal vars for ctrl end Transmit { hldrHSU2LpduTRUnit.uchLpuHSU2State = 0;lMaxTimeTransmit = 0; } } } } else { ;//Always hold distance //if (i>=1000)//Time out more 1Ms { lTmrHSU2Val = uVl; } } */ if(AppReqTransmitTotMeasR == 0) AppReqTransmitTotMeasR = 1;//++; if (hldrHSU2LpduTRUnit.uchLpuHSU2State)//&&(hs2_txsize==0) { TstLab: if(hs2_txsize) ;//Reset counter else { //Control State HSU2 if( chEOI_Hs2) { if(IsEOI_HS2()) chEOI_Hs2 = 0; } pv = (void*)TIMER_CNTR0;j = ((TIMER_CNTR_REGS_T *)pv)->ir;j&= TIMER_CNTR_MTCH_BIT(0);//(( ((TIMER_CNTR_REGS_T *)pv)->ir & TIMER_CNTR_MTCH_BIT(0)) != 0 ) if(j==0) { uVl = ((TIMER_CNTR_REGS_T *)pv)->tc; if (uVl >= 0x1f4) while(1); } if( j &&lMaxTimeTransmit) { if (hs2_txsize==0)//You can insert in this place additonal vars for ctrl end Transmit { hldrHSU2LpduTRUnit.uchLpuHSU2State = 0;lMaxTimeTransmit = 0;((TIMER_CNTR_REGS_T *)pv)->tcr = TIMER_CNTR_TCR_RESET; //Clear timer //-* Stop timer *-/ ((TIMER_CNTR_REGS_T *)pv)->tcr = 0; ((TIMER_CNTR_REGS_T *)pv)->tc = 0; //-* Clear and enable match function *-/ ((TIMER_CNTR_REGS_T *)pv)->ir = TIMER_CNTR_MTCH_BIT(0);((TIMER_CNTR_REGS_T *)pv)->tcr = TIMER_CNTR_TCR_RESET; //TIMER_CNTR_TCR_RESET; } } } } if (hldrHSU1LpduTRUnit.uchLpuHSU1State)//&&(hs2_txsize==0) { TstLab1: if(hs1_txsize) ;//Reset counter else { //Control State HSU2 if( chEOI_Hs1) { if(IsEOI_HS1()) chEOI_Hs1 = 0; } pv = (void*)TIMER_CNTR1;j = ((TIMER_CNTR_REGS_T *)pv)->ir;j&= TIMER_CNTR_MTCH_BIT(0);//(( ((TIMER_CNTR_REGS_T *)pv)->ir & TIMER_CNTR_MTCH_BIT(0)) != 0 ) if(j==0) { uVl = ((TIMER_CNTR_REGS_T *)pv)->tc; if (uVl >= 0x1f4) while(1); } if( j &&lMaxTimeTransmitHSU1) { if (hs1_txsize==0)//You can insert in this place additonal vars for ctrl end Transmit { hldrHSU1LpduTRUnit.uchLpuHSU1State = 0;lMaxTimeTransmitHSU1 = 0;((TIMER_CNTR_REGS_T *)pv)->tcr = TIMER_CNTR_TCR_RESET; //Clear timer //-* Stop timer *-/ ((TIMER_CNTR_REGS_T *)pv)->tcr = 0; ((TIMER_CNTR_REGS_T *)pv)->tc = 0; //-* Clear and enable match function *-/ ((TIMER_CNTR_REGS_T *)pv)->ir = TIMER_CNTR_MTCH_BIT(0);((TIMER_CNTR_REGS_T *)pv)->tcr = TIMER_CNTR_TCR_RESET; //TIMER_CNTR_TCR_RESET; } } } } return 0; }