/* TDM register programming */
static int tdm_fsl_starlite_reg_init(struct tdm_priv *priv)
{
	int i;
	phys_addr_t base = get_immrbase();

#ifdef CONFIG_MPC831x_RDB
	__be32 __iomem *psccr;
	__be32 __iomem *psicr;

	psccr = ioremap(base + SCCR_OFFSET, 4);
	if (!psccr)
		return -1;
	/* CSB:TDM clk =1 */
	clrsetbits_be32(psccr, SCCR_TDM_MASK, TDM_CM_01);
	iounmap(psccr);

	psicr = ioremap(base + SICRL_OFFSET, 4);
	if (!psicr)
		return -1;
	/* enable TDM in SICR */
	clrbits32(psicr, SICRL_TDM_MASK);
	iounmap(psicr);

#endif

#ifdef CONFIG_MPC85xx_RDB
	__be32 __iomem *pmuxcr;

	pmuxcr = ioremap(base + PMUXCR_OFFSET, 4);
	if (!pmuxcr)
		return -1;

	out_be32(pmuxcr, in_be32(pmuxcr) | PMUXCR_TDM_ENABLE);
	iounmap(pmuxcr);
#endif


	/* channel/group round robin */
	out_be32(&priv->dmac_regs->dmacr, DMACR_ERGA | DMACR_ERCA);
	/* Enable error Interrupts for TDM Rx &Tx */
	out_8(&priv->dmac_regs->dmaseei, TDMTX_DMA_CH);
	out_8(&priv->dmac_regs->dmaseei, TDMRX_DMA_CH);
	out_be32(&priv->dmac_regs->dmagpor, DMAGPOR_SNOOP);

	tx_tcd_init(priv);
	rx_tcd_init(priv);

	/* TDM RD->TD loopback, Share T/R Fsync,Clock */
	if (priv->cfg.loopback)
		out_be32(&priv->tdm_regs->gir, GIR_LPBK | GIR_RTS);
	else
		out_be32(&priv->tdm_regs->gir, GIR_RTS);

	/*
	   Rx Water mark 0,  FIFO enable,  Wide fifo, DMA enable for RX,
	   Receive Sync out, syncwidth = ch width, Rx clk out,zero sync,
	   falling edge , data order
	 */

	out_be32(&priv->tdm_regs->rir,
		 RIR_RFWM(0) | RIR_RFEN | RIR_RWEN | RIR_RDMA | RIR_RSL |
		 RIR_RSO | RIR_RCOE | RIR_RRDO | RIR_RFSD(0x01));
	out_be32(&priv->tdm_regs->tir,
		 TIR_TFWM(0) | TIR_TFEN | TIR_TWEN | TIR_TDMA | TIR_TSL |
		 TIR_TSO | TIR_TRDO | TIR_TFSD(0x01));

	/* no of channels ,Channel size-coading */
	out_be32(&priv->tdm_regs->rfp,
		 RFP_RNCF(priv->cfg.num_ch) | RFP_RCS(priv->cfg.ch_type));
	out_be32(&priv->tdm_regs->tfp,
		 TFP_TNCF(priv->cfg.num_ch) | TFP_TCS(priv->cfg.ch_type));

	out_be32(&priv->tdm_regs->rier, 0);
	out_be32(&priv->tdm_regs->tier, 0);

	/* clear all receive and transmit chs */
	for (i = 0; i < 4; i++) {
		out_be32(&priv->tdm_regs->tcma[i], 0);
		out_be32(&priv->tdm_regs->tcen[i], 0);
		out_be32(&priv->tdm_regs->rcen[i], 0);
	}

	return 0;

}
示例#2
0
/* TDM register programming */
static int tdm_fsl_reg_init(struct tdm_priv *priv)
{
	int i;
	int ch_size_type;
	phys_addr_t base = get_immrbase();
	struct tdm_adapter *adap;
	if (!priv) {
		pr_err("%s: Invalid handle\n", __func__);
		return -EINVAL;
	}
	adap = priv->adap;

	/* channel/group round robin */
	out_be32(&priv->dmac_regs->dmacr, DMACR_ERGA | DMACR_ERCA);
	/* Enable error Interrupts for TDM Rx &Tx */
	out_8(&priv->dmac_regs->dmaseei, TDMTX_DMA_CH);
	out_8(&priv->dmac_regs->dmaseei, TDMRX_DMA_CH);
	out_be32(&priv->dmac_regs->dmagpor, DMAGPOR_SNOOP);

	tx_tcd_init(priv);
	rx_tcd_init(priv);

	/* TDM RD->TD loopback, Share T/R Fsync,Clock */
	if (adap->adapt_cfg.loopback)
		out_be32(&priv->tdm_regs->gir, GIR_LPBK | GIR_RTS);
	else
		out_be32(&priv->tdm_regs->gir, GIR_RTS);

	/*
	   Rx Water mark 0,  FIFO enable,  Wide fifo, DMA enable for RX,
	   Receive Sync out, syncwidth = ch width, Rx clk out,zero sync,
	   falling edge , data order
	 */

	out_be32(&priv->tdm_regs->rir,
		 RIR_RFWM(RIR_RFWM_VAL) | RIR_RFEN | RIR_RWEN | RIR_RDMA |
		 RIR_RSL | RIR_RSO | RIR_RCOE | RIR_RRDO |
		 RIR_RFSD(RIR_RFSD_VAL));
	out_be32(&priv->tdm_regs->tir,
		 TIR_TFWM(TIR_RFWM_VAL) | TIR_TFEN | TIR_TWEN | TIR_TDMA |
		 TIR_TSL | TIR_TSO | TIR_TRDO | TIR_TFSD(TIR_RFSD_VAL));

	/* no of channels ,Channel size-coading */
	switch (adap->adapt_cfg.ch_size_type) {
	case CHANNEL_8BIT_LIN:
		ch_size_type = CHANNEL_8BIT_LIN;
		break;
	case CHANNEL_8BIT_ULAW:
		ch_size_type = CHANNEL_8BIT_ULAW;
		break;
	case CHANNEL_8BIT_ALAW:
		ch_size_type = CHANNEL_8BIT_ALAW;
		break;
	case CHANNEL_16BIT_LIN:
		ch_size_type = CHANNEL_16BIT_LIN;
		break;
	default:
		pr_err("%s:Invalid channel_size_type.\n"
			"Setting channel to default size: 16 bits", __func__);
		ch_size_type = CHANNEL_16BIT_LIN;

	}
	out_be32(&priv->tdm_regs->rfp,
		 RFP_RNCF(adap->adapt_cfg.num_ch) | RFP_RCS(ch_size_type));
	out_be32(&priv->tdm_regs->tfp,
		 TFP_TNCF(adap->adapt_cfg.num_ch) | TFP_TCS(ch_size_type));

	out_be32(&priv->tdm_regs->rier, 0);
	out_be32(&priv->tdm_regs->tier, 0);

	/* clear all receive and transmit chs */
	for (i = 0; i < 4; i++) {
		out_be32(&priv->tdm_regs->tcma[i], 0);
		out_be32(&priv->tdm_regs->tcen[i], 0);
		out_be32(&priv->tdm_regs->rcen[i], 0);
	}

	return 0;

}