void poweron_redraw(void)
{
unsigned char x;
unsigned int tmp;
if (!(AKBaval || BORTVaval))
{
if (alarming)
{
unsigned char min = ToBCD(alarm_time[1]);
unsigned char hour = ToBCD(alarm_time[0]);
monitor_On();
display_PutSubBitmap(45,35,(hour>>4)*7,0,7,10,numbers,MODE_SET);
display_PutSubBitmap(54,35,(hour&0x0F)*7,0,7,10,numbers,MODE_SET);
display_PutSubBitmap(67,35,(min>>4)*7,0,7,10,numbers,MODE_SET);
display_PutSubBitmap(76,35,(min&0x0F)*7,0,7,10,numbers,MODE_SET);
display_PutSubBitmap(63,35,73,0,2,10,numbers,MODE_SET);
if (isFlashing())
display_PutSubBitmap(55,12,0,0,19,19,icons2,MODE_SET);
}
else
{
monitor_Off();
}
return;
}
void QueryHeaderS(void)
{
HideCurrTime(1);
ulong dw = DateToHouIndex(tiDigPrev);
dw -= wBaseCurr;
tiDig = HouIndexToDate(dw);
InitPush(0);
PushChar(0xC0);
PushChar(0x48);
PushAddressS();
PushChar(0xD5);
PushChar(0x01);
PushChar(0x34);
PushChar(ToBCD(tiDig.bDay));
PushChar(ToBCD(tiDig.bMonth));
PushChar(ToBCD(tiDig.bYear));
PushChar(tiDig.bHour*2 + tiDig.bMinute/30);
PushChar(4);
QueryS(100+23, 20);
}
void alarm_redraw(void)
{
unsigned char min = ToBCD(alarm_time_toSet[1]);
unsigned char hour = ToBCD(alarm_time_toSet[0]);
display_PutSubBitmap(2,2,89,0,7,7,icons,MODE_SET);
display_PutSubBitmap(2,55,89,8,7,7,icons,MODE_SET);
display_PutSubBitmap(118,2,97,0,7,7,icons,MODE_SET);
display_Rectangle(110,50,17,13,MODE_SET);
display_PutStr(114,53,"OK",0,MODE_XOR);
display_PutSubBitmap(45,35,(hour>>4)*7,0,7,10,numbers,MODE_SET);
display_PutSubBitmap(54,35,(hour&0x0F)*7,0,7,10,numbers,MODE_SET);
display_PutSubBitmap(67,35,(min>>4)*7,0,7,10,numbers,MODE_SET);
display_PutSubBitmap(76,35,(min&0x0F)*7,0,7,10,numbers,MODE_SET);
display_PutSubBitmap(63,35,73,0,2,10,numbers,MODE_SET);
display_PutSubBitmap(55,12,0,0,19,19,icons2,MODE_SET);
switch (LANGUAGE)
{
case 1: display_PutStr(52,2,"Alarm",0,MODE_SET); break;
default: display_PutStr(46,2,"Ѕудильник",0,MODE_SET);
}
if (isFlashing())
{
if (al_cursor_pos)
display_Rectangle(66,34,18,12,MODE_XOR);
else
display_Rectangle(44,34,18,12,MODE_XOR);
}
}
void SetRtc(Rtc_t *pRtcData)
{
// Stop the RTC
RTCCTL01 |= RTCHOLD;
// These calls are to asm level patch functions provided by TI for the MSP430F5438
unsigned int Year = (pRtcData->YearMsb << 8) + pRtcData->YearLsb;
PrintF(">SetRtc Year: %d", Year);
RtcYear = (ToBCD(Year / 100) << 8) + ToBCD(Year % 100);
PrintF(" %04X", RtcYear);
RtcMon = ToBCD(pRtcData->Month);
RtcDay = ToBCD(pRtcData->Day);
RtcDow = ToBCD(pRtcData->DayOfWeek);
RtcHour = ToBCD(pRtcData->Hour);
RtcMin = ToBCD(pRtcData->Minute);
RtcSec = ToBCD(pRtcData->Second);
RTCYEAR = RtcYear;
RTCMON = RtcMon;
RTCDAY = RtcDay;
RTCDOW = RtcDow;
RTCHOUR = RtcHour;
RTCMIN = RtcMin;
RTCSEC = RtcSec;
// Enable the RTC
RTCCTL01 &= ~RTCHOLD;
EnableTimeStamp();
}
void params_drawVersion(void)
{
unsigned char x = 13;
display_PutStr(x,4,"v ",0,MODE_SET);
x+=display_StrLength("v ");
if (!values_aval[Version])
{
display_PutStr(x,4,"__._/",0,MODE_SET);
x+=display_StrLength("__._/");
}
else
{
unsigned char t = (values[Version]>>0)&0xFF;
unsigned long int pcb = (values[Version]>>8)&0xFF;
unsigned long int v = (values[Version]>>16)&0xFF;
switch (t)
{
case 0:
display_PutStr(x,4,"m",0,MODE_SET);
x+=6;
break;
case 1:
display_PutStr(x,4,"y",0,MODE_SET);
x+=4;
break;
case 2:
display_PutStr(x,4,"k",0,MODE_SET);
x+=4;
break;
default:
display_PutStr(x,4,"x",0,MODE_SET);
x+=4;
}
x=display_PutBCD(x,4,ToBCD(pcb),0,MODE_SET);
display_PutStr(x,4,".",0,MODE_SET);
x+=2;
x=display_PutBCD(x,4,ToBCD(v),0,MODE_SET);
display_PutStr(x,4,"/",0,MODE_SET);
x+=6;
}
display_PutStr(x,4,(const char*)version,0,MODE_SET);
}
static unsigned char IncBCD(unsigned char Rtc, unsigned char Index)
{
Rtc = ToBin(Rtc) + 1;
if (Rtc > MaxRtc[Index])
Rtc = (Index == RTC_MIN || Index == RTC_DOW || Index == RTC_SEC) ? 0 : 1;
return ToBCD(Rtc);
}
void QueryControlS(time ti)
{
InitPush(0);
PushChar(0xC0);
PushChar(0x48);
PushAddressS();
PushChar(0xD7);
PushChar(0x01);
PushChar(0x21);
PushChar(ToBCD(tiCurr.bSecond));
PushChar(ToBCD(tiCurr.bMinute));
PushChar(ToBCD(tiCurr.bHour));
PushChar((GetWeekdayYMD(ti.bYear, ti.bMonth, ti.bDay) + 1) % 7);
PushChar(ToBCD(tiCurr.bDay));
PushChar(ToBCD(tiCurr.bMonth));
PushChar(ToBCD(tiCurr.bYear));
QueryS(100+11, 22);
}
void speedk_OnInit(void)
{
unsigned long k;
driver_ReadID(PerOtnSpeedometr);
if (values_aval[PerOtnSpeedometr])
{
k = ToBCD(values[PerOtnSpeedometr]);
s_speedk[0] = (k&0xF00000)>>20;
s_speedk[1] = (k&0xF0000)>>16;
s_speedk[2] = (k&0xF000)>>12;
s_speedk[3] = (k&0xF00)>>8;
s_speedk[4] = (k&0xF0)>>4;
s_speedk[5] = (k&0xF);
}
else
{
static void DrawBatteryOnIdleScreen(unsigned char Row, unsigned char Col, etFontType Font)
{
// Battery
CopyColumnsIntoMyBuffer(GetBatteryIcon(ICON_SET_BATTERY_V), Row,
IconInfo[ICON_SET_BATTERY_V].Height, Col, IconInfo[ICON_SET_BATTERY_V].Width);
SetFont(Font);
gRow = Row + (Font == MetaWatch7 ? 23 : 21); //29
gColumn = Col - 1; //8
gBitColumnMask = (Font == MetaWatch7) ? BIT4 : BIT7;
unsigned char BattVal = BatteryPercentage();
if (BattVal < 100)
{
BattVal = ToBCD(BattVal);
DrawChar(BattVal > 9 ? BCD_H(BattVal) +ZERO : SPACE, DRAW_OPT_BITWISE_OR);
DrawChar(BCD_L(BattVal) +ZERO, DRAW_OPT_BITWISE_OR);
}
else DrawString("100", DRAW_OPT_BITWISE_OR);
DrawChar('%', DRAW_OPT_BITWISE_OR);
}
CDPR::CDPR(CConfigurator * cfg, CSystem * c) : CSystemComponent(cfg,c)
{
if (theDPR)
FAILURE("More than one DPR!!");
theDPR = this;
u8 i;
c->RegisterMemory(this, 0, X64(0000080110000000),0x100000); // 16KB
memset(state.ram,0,16*1024);
//
state.ram[0x3401] = 1; // SROM valid
state.ram[0] = 1; // EV6 BIST
state.ram[1] = 0x80; // SROM status
state.ram[2] = 1; // STR status
state.ram[3] = 1; // CSC status
state.ram[4] = 1; // Pchip0 status
state.ram[5] = 1; // Pchip1 status
state.ram[6] = 1; // DIMx status
state.ram[7] = 1; // TIG bus status
state.ram[8] = 0xdd; // DPR test started
state.ram[9] = 1; // DPR status
state.ram[10] = 0xff; // CPU speed status
state.ram[11] = 833%256; //speed
state.ram[12] = 833/256; //speed
// powerup time BCD:
time_t now = time(NULL);
struct tm *t = localtime(&now);
state.ram[16] = ToBCD(t->tm_hour);
state.ram[17] = ToBCD(t->tm_min);
state.ram[18] = ToBCD(t->tm_sec);
state.ram[19] = ToBCD(t->tm_mday);
state.ram[20] = ToBCD(t->tm_mon+1);
state.ram[21] = ToBCD(t->tm_year-100); // tm_year is based on 1900
#if defined(DEBUG_DPR)
printf("%%DPR-I-BOOTDATE: %02x-%02x-%02x, %02x:%02x:%02x\n",
state.ram[21],state.ram[20],state.ram[19],
state.ram[16],state.ram[17],state.ram[18]);
#endif
state.ram[0x16] = 0; // no error
state.ram[0x1e] = 0x80; // CPU SROM sync moet 0x80 zijn; anders --> cpu0 startup failure
state.ram[0x1f] = 8; // cach size in MB
state.ram[0xda] = 0xaa; // TIG load
// DIMM config
state.ram[0x80] = 0xf0; // twice-split 8 dimms array 0
state.ram[0x81] = 0x01; // 64 MB
// state.ram[0x82] = 0xf1; // twice-split 8 dimms array 1
// state.ram[0x83] = 0x01; // 64 MB
// state.ram[0x84] = 0xf2; // twice-split 8 dimms array 2
// state.ram[0x85] = 0x01; // 64 MB
// state.ram[0x86] = 0xf3; // twice-split 8 dimms array 3
// state.ram[0x87] = 0x01; // 64 MB
// powerup failure bits
state.ram[0x88] = 0; // each bit is one DIMM on MMB0
state.ram[0x89] = 0x00; // MMB1
state.ram[0x8a] = 0x00; // MMB2
state.ram[0x8b] = 0x00; // MMB3
// misconfigured DIMM bits
state.ram[0x8c] = 0; // each bit is one DIMM on MMB0
state.ram[0x8d] = 0; // MMB1
state.ram[0x8e] = 0; // MMB2
state.ram[0x8f] = 0; // MMB3
state.ram[0x90] = 0xff; // psu / vterm present
state.ram[0x91] = 0x00; // psu ok bits
state.ram[0x92] = 0x07; // ac inputs valid
state.ram[0x93] = 0x25; // cpu 0 temp in C
state.ram[0x94] = 0x25; // cpu 1 temp in C
state.ram[0x95] = 0x25; // cpu 2 temp in C
state.ram[0x96] = 0x25; // cpu 3 temp in C
state.ram[0x97] = 0x25; // pci 0 temp in C
state.ram[0x98] = 0x25; // pci 1 temp in C
state.ram[0x99] = 0x25; // pci 2 temp in C
state.ram[0x9a] = 0x8b; // fan 0 speed
state.ram[0x9b] = 0x8b; // fan 1 speed
state.ram[0x9c] = 0x8b; // fan 2 speed
state.ram[0x9d] = 0x8b; // fan 3 speed
state.ram[0x9e] = 0x8b; // fan 4 speed
state.ram[0x9f] = 0x8b; // fan 5 speed
// vector 680 info (various faults)
for (i=0xa0;i<0xaa;i++)
state.ram[i] = 0;
state.ram[0xaa] = 0x00; // fans good
// RMC read failure DIMM bits
state.ram[0xab] = 0; // each bit is one DIMM on MMB0
state.ram[0xac] = 0xff; // MMB1
state.ram[0xad] = 0xff; // MMB2
state.ram[0xae] = 0xff; // MMB3
state.ram[0xaf] = 0x0e; // all MMB I2C's read + CPU 0
state.ram[0xb0] = 0x00; // PCI i2c read
state.ram[0xb1] = 0x00; // mainboard i2c read
state.ram[0xb2] = 0x00; // psu's and scsi backplanes i2c read
state.ram[0xba] = 0xba; // i2c finished
state.ram[0xbb] = 0x00; // rmc error
state.ram[0xbc] = 0x00; //rmc flash update error status
// 680 fatal registers
state.ram[0xbd] = 0x07; // ac inputs valid
state.ram[0xbe] = 0; // faults
state.ram[0xbf] = 0; // faults
state.ram[0xda] = 0xaa; // tig load success
// Power-supplies
state.ram[0xdb] = 0xf4; // PS0 id
state.ram[0xdc] = 0x45; // 3.3v current
state.ram[0xdd] = 0x51; // 5.0v current
state.ram[0xde] = 0x37; // 12v current
state.ram[0xdf] = 0x8b; // fan speed
state.ram[0xe0] = 0xd6; // ac voltage (230v)
state.ram[0xe1] = 0x49; // internal temp. (56 C)
state.ram[0xe2] = 0x4b; // inlet temp. (20 C)
state.ram[0xe4] = 0xf5; // PS1 id
state.ram[0xe5] = 0x45; // 3.3v current
state.ram[0xe6] = 0x51; // 5.0v current
state.ram[0xe7] = 0x37; // 12v current
state.ram[0xe8] = 0x8b; // fan speed
state.ram[0xe9] = 0xd6; // ac voltage (230v)
state.ram[0xea] = 0x49; // internal temp. (56 C)
state.ram[0xeb] = 0x4b; // inlet temp. (20 C)
state.ram[0xed] = 0xf6; // PS2 id
state.ram[0xee] = 0x45; // 3.3v current
state.ram[0xef] = 0x51; // 5.0v current
state.ram[0xf0] = 0x37; // 12v current
state.ram[0xf1] = 0x8b; // fan speed
state.ram[0xf2] = 0xd6; // ac voltage (230v)
state.ram[0xf3] = 0x49; // internal temp. (56 C)
state.ram[0xf4] = 0x4b; // inlet temp. (20 C)
// EEROMs
/*
100: MMB0 DIMM 2
200: MMB0 DIMM 3
300: MMB0 DIMM 4
400: MMB0 DIMM 5
500: MMB0 DIMM 6
600: MMB0 DIMM 7
700: MMB0 DIMM 8
800: MMB0 DIMM 1
900: MMB1 DIMM 2
a00: MMB1 DIMM 3
b00: MMB1 DIMM 4
c00: MMB1 DIMM 5
d00: MMB1 DIMM 6
e00: MMB1 DIMM 7
f00: MMB1 DIMM 8
1000: MMB1 DIMM 1
1100: MMB2 DIMM 2
1200: MMB2 DIMM 3
1300: MMB2 DIMM 4
1400: MMB2 DIMM 5
1500: MMB2 DIMM 6
1600: MMB2 DIMM 7
1700: MMB2 DIMM 8
1800: MMB2 DIMM 1
1900: MMB3 DIMM 2
1a00: MMB3 DIMM 3
1b00: MMB3 DIMM 4
1c00: MMB3 DIMM 5
1d00: MMB3 DIMM 6
1e00: MMB3 DIMM 7
1f00: MMB3 DIMM 8
2000: MMB3 DIMM 1
2100: CPU0
2200: CPU1
2300: CPU2
2400: CPU3
2500: MMB0
2600: MMB1
2700: MMB2
2800: MMB3
2900: CPB (PCI backplane)
2a00: CSB (motherboard)
3100: PSU0 cont @ 3d00
3200: PSU1 cont @ 3e00
3300: PSU2 cont @ 3f00
3b00: SCSI0 (backplane)
3c00: SCSI1
2B00:2BFF RMC Last EV6 Correctable Error
ASCII character string that indicates correctable error occurred, type, FRU, and so on.
2C00:2CFF RMC Last Redundant Failure
ASCII character string that indicates redundant failure occurred, type, FRU, and so on.
2D00:2DFF RMC Last System Failure
ASCII character string that indicates system failure occurred, type, FRU, and so on.
2E00:2FFF RMC Uncorrectable machine logout frame (512 bytes)
*/
// 3000:3008 SROM Version (ASCII string)
state.ram[0x3000] = 'V';
state.ram[0x3001] = '2';
state.ram[0x3002] = '.';
state.ram[0x3003] = '2';
state.ram[0x3004] = '2';
state.ram[0x3005] = 'G';
state.ram[0x3006] = 0;
state.ram[0x3007] = 0;
state.ram[0x3008] = 0;
// 3009:300B RMC Rev Level of RMC first byte is letter Rev [x/t/v] second 2 bytes are major/minor.
// This is the rev level of the RMC on-chip code.
state.ram[0x3009] = 'V';
state.ram[0x300a] = 0x01;
state.ram[0x300b] = 0x00;
// 300C:300E RMC Rev Level of RMC first byte is letter Rev [x/t/v] second 2 bytes are major/minor.
// This is the rev level of the RMC flash code.
state.ram[0x300c] = 'V';
state.ram[0x300d] = 0x01;
state.ram[0x300e] = 0x00;
// 300F:3010 300F RMC Revision Field of the DPR Structure
// 3400 SROM Size of Bcache in MB
state.ram[0x3400] = 8;
//3401 SROM Flash SROM is valid flag; 8 = valid,0 = invalid
state.ram[0x3401] = 1;
//3402 SROM System's errors determined by SROM
state.ram[0x3402] = 0;
//3410:3417 SROM/SRM Jump to address for CPU0
//3418 SROM/SRM Waiting to jump to flag for CPU0
//3419 SROM Shadow of value written to EV6 DC_CTL register.
//341A:341E SROM Shadow of most recent writes to EV6 CBOX "Write-many" chain.
//34A0:34A7 SROM Array 0 to DIMM ID translation
// Bits<4:0>
// Bits<7:5>
// 0 = Exists, No Error Bits <2:0> =
// 1 = Expected Missing DIMM + 1 (1-8)
// 2 = Error - Missing DIMM(s) Bits <4:3> =
// 4 = Error - Illegal MMB (0-3) DIMM(s)
// 6 = Error - Incompatible DIMM(s)
// 34A8:34AF SROM Repeat for Array 1 of Array 0 34A0:34A7
// 34B0:34B7 SROM Repeat for Array 2 of Array 0 34A0:34A7
// 34B8:34CF SROM Repeat for Array 3 of Array 0 34A0:34A7
for (i=0;i<0x20;i++)
state.ram[0x34a0+i] = i;
// 34C0:34FF Used as scratch area for SROM
// 3500:35FF Used as the dedicated buffer in which SRM writes OCP or FRU EEROM data.
// Firmware will write this data, RMC will only read this data.
// 3600:36FF 3600 SRM Reserved
// 3700:37FF SRM Reserved
// 3800:3AFF RMC RMC scratch space
printf("%s: $Id: DPR.cpp,v 1.16 2008/02/29 10:23:09 iamcamiel Exp $\n",devid_string);
}
