virtual BOOL Init()
	{
		PHYSICAL_ADDRESS	ioPhysicalBase = { S3C6400_BASE_REG_PA_GPIO, 0};
		ULONG				inIoSpace = 0;
		if (TranslateBusAddr(m_hParent,Internal,0, ioPhysicalBase,&inIoSpace,&ioPhysicalBase))
		{
			// Map it if it is Memeory Mapped IO.
			m_pIOPregs = (S3C6400_GPIO_REG *)DrvLib_MapIoSpace(ioPhysicalBase.LowPart , sizeof(S3C6400_GPIO_REG),FALSE);
		}
		ioPhysicalBase.LowPart = S3C6400_BASE_REG_PA_SYSCON;
		ioPhysicalBase.HighPart = 0;
		if (TranslateBusAddr(m_hParent,Internal,0, ioPhysicalBase,&inIoSpace,&ioPhysicalBase))
		{
			m_pSysconRegs = (S3C6400_SYSCON_REG *) DrvLib_MapIoSpace(ioPhysicalBase.LowPart ,sizeof(S3C6400_SYSCON_REG),FALSE);
		}
		if(m_pSysconRegs)
		{
			m_pSysconRegs->PCLK_GATE  |= (1<<1);		// UART0
			m_pSysconRegs->SCLK_GATE  |= (1<<5);		// UART0~3	
		}
		if (m_pIOPregs)
		{
			DDKISRINFO ddi;
			if (GetIsrInfo(&ddi)== ERROR_SUCCESS && 
				 KernelIoControl(IOCTL_HAL_REQUEST_SYSINTR, &ddi.dwIrq, sizeof(UINT32), &ddi.dwSysintr, sizeof(UINT32), NULL))
			{   
				//RETAILMSG( TRUE, (TEXT("DEBUG: Serial0 SYSINTR : %d\r\n"), (PBYTE)&ddi.dwSysintr)); 
				RegSetValueEx(DEVLOAD_SYSINTR_VALNAME,REG_DWORD,(PBYTE)&ddi.dwSysintr, sizeof(UINT32));
			}
			else
			{
				return FALSE;
			}

			m_pDTRPort = (volatile ULONG *)&(m_pIOPregs->GPNDAT);
			m_pDSRPort = (volatile ULONG *)&(m_pIOPregs->GPNDAT);
			m_dwDTRPortNum = 6;
			m_dwDSRPortNum = 7;

			// CTS0(GPA2), RTS0(GPA3), TXD0(GPA1), RXD0(GPA0)
			m_pIOPregs->GPACON &= ~(0xf<<0 | 0xf<<4 | 0xf<<8 | 0xf<<12 );	///< Clear Bit
			m_pIOPregs->GPACON |=  (0x2<<0 | 0x2<<4 | 0x2<<8 | 0x2<<12 ); 	///< Select UART IP                
			m_pIOPregs->GPAPUD &= ~(0x3<<0 | 0x3<<2 | 0x3<<4 | 0x3<<6 );    ///< Pull-Up/Down Disable  

			// DTR0(GPN6), DSR0(GPN7)
			// If you want to use COM1 port for ActiveSync, use these statements.     
			m_pIOPregs->GPNCON &= ~(0x3<<12);	///< DTR0 Clear Bit
			m_pIOPregs->GPNCON |= (0x1<<12);	///< Output
			m_pIOPregs->GPNPUD &= ~(0x3<<12);	///< Pull-Up/Down Disable 
			m_pIOPregs->GPNCON &= ~(0x3<<14);	///< DSR0 Clear Bit
			m_pIOPregs->GPNCON |= (0x0<<14);	///< Input
			m_pIOPregs->GPNPUD &= ~(0x3<<14);	///< Pull-Up/Down Disable 

			return CPdd6400Uart::Init();
		}
		return FALSE;
	}
示例#2
0
BOOL CPdd6410Uart::MapHardware() 
{
    if (m_pRegVirtualAddr !=NULL)
    {
        return TRUE;
    }

    // Get IO Window From Registry
    DDKWINDOWINFO dwi;
    if ( GetWindowInfo( &dwi)!=ERROR_SUCCESS || 
    dwi.dwNumMemWindows < 1 || 
    dwi.memWindows[0].dwBase == 0 || 
    dwi.memWindows[0].dwLen < m_dwMemLen)
    {
        return FALSE;
    }

    DWORD dwInterfaceType;
    if (m_ActiveReg.IsKeyOpened() && 
    m_ActiveReg.GetRegValue( DEVLOAD_INTERFACETYPE_VALNAME, (PBYTE)&dwInterfaceType,sizeof(DWORD)))
    {
        dwi.dwInterfaceType = dwInterfaceType;
    }

    // Translate to System Address.
    PHYSICAL_ADDRESS    ioPhysicalBase = { dwi.memWindows[0].dwBase, 0};
    ULONG                inIoSpace = 0;
    if (TranslateBusAddr(m_hParent,(INTERFACE_TYPE)dwi.dwInterfaceType,dwi.dwBusNumber, ioPhysicalBase,&inIoSpace,&ioPhysicalBase))
    {
        // Map it if it is Memeory Mapped IO.
        m_pRegVirtualAddr = MmMapIoSpace(ioPhysicalBase, dwi.memWindows[0].dwLen,FALSE);
    }

    return (m_pRegVirtualAddr!=NULL );
}
示例#3
0
BOOL CSerialPDD::Open()
{
    PHYSICAL_ADDRESS	ioPhysicalBase = { S3C6410_BASE_REG_PA_GPIO, 0};
    ULONG				inIoSpace = 0;

    if (InterlockedExchange(&m_lOpenCount,1) !=0)
        return FALSE;
    
    PREFAST_ASSERT(m_PowerHelperHandle!=INVALID_HANDLE_VALUE);
    ASSERT(m_hPowerLock==NULL);
    m_hPowerLock= DDKPwr_RequestLevel( m_PowerHelperHandle, D0 );  
    ASSERT(m_hPowerLock!=NULL);
    
    SetDefaultConfiguration(); 
    InitLine(TRUE);
    InitReceive(TRUE);
    InitXmit(TRUE);

    if(cUart_Index==3)
    {
        if (TranslateBusAddr(m_hParent,Internal,0, ioPhysicalBase,&inIoSpace,&ioPhysicalBase))
    	{
	// Map it if it is Memeory Mapped IO.
	g_pIOPregs = (S3C6410_GPIO_REG *)DrvLib_MapIoSpace(ioPhysicalBase.LowPart , sizeof(S3C6410_GPIO_REG),FALSE);	
	g_pIOPregs->GPCCON &= ~(0xf<<28);	///< Clear Bit
	g_pIOPregs->GPCCON |=  (0x1<<28); 	///< Select UART IP                
	g_pIOPregs->GPCPUD &= ~(0x3<<14);    ///< Pull-Up/Down Disable  
	//g_pIOPregs->GPCDAT |=1<<7;

    	}
    }
    return TRUE;
}
	virtual BOOL Init()
	{
		PHYSICAL_ADDRESS	ioPhysicalBase = { S3C6400_BASE_REG_PA_GPIO, 0};
		ULONG				inIoSpace = 0;
		if (TranslateBusAddr(m_hParent,Internal,0, ioPhysicalBase,&inIoSpace,&ioPhysicalBase))
		{
			// Map it if it is Memeory Mapped IO.
			m_pIOPregs =(S3C6400_GPIO_REG *) DrvLib_MapIoSpace(ioPhysicalBase.LowPart, sizeof(S3C6400_GPIO_REG),FALSE);
		}
		ioPhysicalBase.LowPart = S3C6400_BASE_REG_PA_SYSCON;
		ioPhysicalBase.HighPart = 0;
		if (TranslateBusAddr(m_hParent,Internal,0, ioPhysicalBase,&inIoSpace,&ioPhysicalBase))
		{
			m_pSysconRegs = (S3C6400_SYSCON_REG *) DrvLib_MapIoSpace(ioPhysicalBase.LowPart,sizeof(S3C6400_SYSCON_REG),FALSE);
		}
		if(m_pSysconRegs)
		{		
			m_pSysconRegs->PCLK_GATE  |= (1<<4);		// UART3
			m_pSysconRegs->SCLK_GATE  |= (1<<5);		// UART0~3	
		}
		if (m_pIOPregs)
		{
			DDKISRINFO ddi;
			if (GetIsrInfo(&ddi)== ERROR_SUCCESS && 
				KernelIoControl(IOCTL_HAL_REQUEST_SYSINTR, &ddi.dwIrq, sizeof(UINT32), &ddi.dwSysintr, sizeof(UINT32), NULL))
			{   
				//RETAILMSG( TRUE, (TEXT("DEBUG: Serial3 SYSINTR : %d\r\n"), (PBYTE)&ddi.dwSysintr)); 
				RegSetValueEx(DEVLOAD_SYSINTR_VALNAME,REG_DWORD,(PBYTE)&ddi.dwSysintr, sizeof(UINT32));
			}
			else
			{
				return FALSE;
			}

			// TXD3(GPB3), RXD3(GPB2)
			m_pIOPregs->GPBCON &= ~(0xf<<8 | 0xf<<12); 
			m_pIOPregs->GPBCON |= (0x2<<8 | 0x2<<12); 
			m_pIOPregs->GPBPUD &= ~(0x3<<4 | 0x3<<6);

			return CPdd6400Uart::Init();
		}
		return FALSE;
	}