/**
* Initalize the RS232 port.
*
*/
void
uart1_init(unsigned long ubr)
{
/* RS232 */
P3DIR &= ~0x80; /* Select P37 for input (UART1RX) */
P3DIR |= 0x40; /* Select P36 for output (UART1TX) */
P3SEL |= 0xC0; /* Select P36,P37 for UART1{TX,RX} */
UCTL1 = SWRST | CHAR; /* 8-bit character, UART mode */
#if 0
U1RCTL &= ~URXEIE; /* even erroneous characters trigger interrupts */
#endif
UTCTL1 = SSEL1; /* UCLK = MCLK */
UBR01 = ubr;
UBR11 = ubr >> 8;
/*
* UMCTL1 values calculated using
* http://mspgcc.sourceforge.net/baudrate.html
* Table assumes that F_CPU = 2,457,600 Hz.
*/
switch(ubr) {
case UART1_BAUD2UBR(115200ul):
UMCTL1 = 0x4a;
break;
case UART1_BAUD2UBR(57600ul):
UMCTL1 = 0x5b;
break;
default:
/* 9600, 19200, 38400 don't require any correction */
UMCTL1 = 0x00;
}
ME2 &= ~USPIE1; /* USART1 SPI module disable */
ME2 |= (UTXE1 | URXE1); /* Enable USART1 TXD/RXD */
UCTL1 &= ~SWRST;
/* XXX Clear pending interrupts before enable!!! */
IFG2 &= ~URXIFG1;
U1TCTL |= URXSE;
rx_in_progress = 0;
transmitting = 0;
IE2 |= URXIE1; /* Enable USART1 RX interrupt */
#if TX_WITH_INTERRUPT
IE2 |= UTXIE1; /* Enable USART1 RX interrupt */
ringbuf_init(&txbuf, txbuf_data, sizeof(txbuf_data));
#endif /* TX_WITH_INTERRUPT */
}
/**
* Initalize the RS232 port.
*
*/
void
uart1_init(unsigned long ubr)
{
/* RS232 */
P3DIR &= ~0x80; /* Select P37 for input (UART1RX) */
P3DIR |= 0x40; /* Select P36 for output (UART1TX) */
P3SEL |= 0xC0; /* Select P36,P37 for UART1{TX,RX} */
UCTL1 = SWRST | CHAR; /* 8-bit character, UART mode */
#if 0
U1RCTL &= ~URXEIE; /* even erroneous characters trigger interrupts */
#endif
UTCTL1 = SSEL1; /* UCLK = MCLK */
UBR01 = ubr;
UBR11 = ubr >> 8;
/*
* UMCTL1 values calculated using
* http://mspgcc.sourceforge.net/baudrate.html
*/
switch(ubr) {
#if F_CPU == 3900000ul
case UART1_BAUD2UBR(115200ul):
UMCTL1 = 0xF7;
break;
case UART1_BAUD2UBR(57600ul):
UMCTL1 = 0xED;
break;
case UART1_BAUD2UBR(38400ul):
UMCTL1 = 0xD6;
break;
case UART1_BAUD2UBR(19200ul):
UMCTL1 = 0x08;
break;
case UART1_BAUD2UBR(9600ul):
UMCTL1 = 0x22;
break;
#elif F_CPU == 2457600ul
case UART1_BAUD2UBR(115200ul):
UMCTL1 = 0x4A;
break;
case UART1_BAUD2UBR(57600ul):
UMCTL1 = 0x5B;
break;
default:
/* 9600, 19200, 38400 don't require any correction */
UMCTL1 = 0x00;
#else
#error Unsupported CPU speed in uart1.c
#endif
}
ME2 &= ~USPIE1; /* USART1 SPI module disable */
ME2 |= (UTXE1 | URXE1); /* Enable USART1 TXD/RXD */
UCTL1 &= ~SWRST;
/* XXX Clear pending interrupts before enable!!! */
IFG2 &= ~URXIFG1;
U1TCTL |= URXSE;
rx_in_progress = 0;
transmitting = 0;
IE2 |= URXIE1; /* Enable USART1 RX interrupt */
#if TX_WITH_INTERRUPT
ringbuf_init(&txbuf, txbuf_data, sizeof(txbuf_data));
IE2 |= UTXIE1; /* Enable USART1 TX interrupt */
#endif /* TX_WITH_INTERRUPT */
#if RX_WITH_DMA
IE2 &= ~URXIE1; /* disable USART1 RX interrupt */
/* UART1_RX trigger */
DMACTL0 = DMA0TSEL_9;
/* source address = RXBUF1 */
DMA0SA = (unsigned int) &RXBUF1;
DMA0DA = (unsigned int) &rxbuf;
DMA0SZ = RXBUFSIZE;
last_size = RXBUFSIZE;
DMA0CTL = DMADT_4 + DMASBDB + DMADSTINCR_3 + DMAEN + DMAREQ;// DMAIE;
msp430_add_lpm_req(MSP430_REQUIRE_LPM1);
#endif /* RX_WITH_DMA */
}
