void platform_dgetc(char *c)
{
while (UARTREG(UART0_FR) & UART0_RX_FIFO_EMPTY)
;
*c = UARTREG(UART0_DR) & 0xff;
}
static int imx_uart_pgetc() {
if (!uart_base) {
return ZX_ERR_NOT_SUPPORTED;
}
if ((UARTREG(MX8_UTS) & UTS_RXEMPTY)) {
return ZX_ERR_INTERNAL;
}
return UARTREG(MX8_URXD);
}
/* panic-time getc/putc */
static int imx_uart_pputc(char c) {
if (!uart_base) {
return -1;
}
/* spin while fifo is full */
while (UARTREG(MX8_UTS) & UTS_TXFULL)
;
UARTREG(MX8_UTXD) = c;
return 1;
}
static void imx_dputs(const char* str, size_t len,
bool block, bool map_NL) {
spin_lock_saved_state_t state;
bool copied_CR = false;
if (!uart_base) {
return;
}
if (!uart_tx_irq_enabled) {
block = false;
}
spin_lock_irqsave(&uart_spinlock, state);
while (len > 0) {
// is FIFO full?
while ((UARTREG(MX8_UTS) & UTS_TXFULL)) {
spin_unlock_irqrestore(&uart_spinlock, state);
if (block) {
event_wait(&uart_dputc_event);
} else {
arch_spinloop_pause();
}
spin_lock_irqsave(&uart_spinlock, state);
}
if (*str == '\n' && map_NL && !copied_CR) {
copied_CR = true;
imx_uart_pputc('\r');
} else {
copied_CR = false;
imx_uart_pputc(*str++);
len--;
}
}
spin_unlock_irqrestore(&uart_spinlock, state);
}
static void
dumpitall(void)
{
iprint("intr: icip %lux iclr %lux iccr %lux icmr %lux\n",
INTRREG->icip,
INTRREG->iclr, INTRREG->iccr, INTRREG->icmr );
iprint("gpio: lvl %lux dir %lux, re %lux, fe %lux sts %lux alt %lux\n",
GPIOREG->gplr,
GPIOREG->gpdr, GPIOREG->grer, GPIOREG->gfer,
GPIOREG->gpsr, GPIOREG->gafr);
iprint("uart1: %lux %lux %lux\nuart3: %lux %lux %lux\n",
UARTREG(1)->utcr0, UARTREG(1)->utsr0, UARTREG(1)->utsr1,
UARTREG(3)->utcr0, UARTREG(3)->utsr0, UARTREG(3)->utsr1);
iprint("tmr: osmr %lux %lux %lux %lux oscr %lux ossr %lux oier %lux\n",
OSTMRREG->osmr[0], OSTMRREG->osmr[1],
OSTMRREG->osmr[2], OSTMRREG->osmr[3],
OSTMRREG->oscr, OSTMRREG->ossr, OSTMRREG->oier);
iprint("dram: mdcnfg %lux mdrefr %lux cas %lux %lux %lux %lux %lux %lux\n",
MEMCFGREG->mdcnfg, MEMCFGREG->mdrefr,
MEMCFGREG->mdcas0[0], MEMCFGREG->mdcas0[1],MEMCFGREG->mdcas0[2],
MEMCFGREG->mdcas2[0], MEMCFGREG->mdcas2[1],MEMCFGREG->mdcas2[2]);
iprint("dram: mdcnfg msc %lux %lux %lux mecr %lux\n",
MEMCFGREG->msc0, MEMCFGREG->msc1,MEMCFGREG->msc2,
MEMCFGREG->mecr);
}
static interrupt_eoi uart_irq_handler(void* arg) {
/* read interrupt status and mask */
while ((UARTREG(MX8_USR1) & USR1_RRDY)) {
if (cbuf_space_avail(&uart_rx_buf) == 0) {
break;
}
char c = UARTREG(MX8_URXD) & 0xFF;
cbuf_write_char(&uart_rx_buf, c);
}
/* Signal if anyone is waiting to TX */
if (UARTREG(MX8_UCR1) & UCR1_TRDYEN) {
spin_lock(&uart_spinlock);
if (!(UARTREG(MX8_USR2) & UTS_TXFULL)) {
// signal
event_signal(&uart_dputc_event, true);
}
spin_unlock(&uart_spinlock);
}
return IRQ_EOI_DEACTIVATE;
}
static void imx_uart_init(const void* driver_data, uint32_t length) {
uint32_t regVal;
// create circular buffer to hold received data
cbuf_initialize(&uart_rx_buf, RXBUF_SIZE);
// register uart irq
register_int_handler(uart_irq, &uart_irq_handler, NULL);
// set rx fifo threshold to 1 character
regVal = UARTREG(MX8_UFCR);
regVal &= ~UFCR_RXTL(UFCR_MASK);
regVal &= ~UFCR_TXTL(UFCR_MASK);
regVal |= UFCR_RXTL(1);
regVal |= UFCR_TXTL(0x2);
UARTREG(MX8_UFCR) = regVal;
// enable rx interrupt
regVal = UARTREG(MX8_UCR1);
regVal |= UCR1_RRDYEN;
if (dlog_bypass() == false) {
// enable tx interrupt
regVal |= UCR1_TRDYEN;
}
UARTREG(MX8_UCR1) = regVal;
// enable rx and tx transmisster
regVal = UARTREG(MX8_UCR2);
regVal |= UCR2_RXEN | UCR2_TXEN;
UARTREG(MX8_UCR2) = regVal;
if (dlog_bypass() == true) {
uart_tx_irq_enabled = false;
} else {
/* start up tx driven output */
printf("UART: started IRQ driven TX\n");
uart_tx_irq_enabled = true;
}
initialized = true;
// enable interrupts
unmask_interrupt(uart_irq);
}
