OSStatus MicoUartSend( mico_uart_t uart, const void* data, uint32_t size ) { // /* Reset DMA transmission result. The result is assigned in interrupt handler */ uint32_t Instance = getInstanceBy(uart); uart_interfaces[uart].tx_dma_result = kGeneralErr; #ifndef NO_MICO_RTOS mico_rtos_lock_mutex(&uart_interfaces[uart].tx_mutex); #endif MicoMcuPowerSaveConfig(false); #ifdef UART_IRQ_APP if (UART_DRV_SendData(Instance, data, size) == kStatus_UART_Success){ #else if (UART_DRV_EdmaSendData(Instance, data, size) == kStatus_UART_Success){ #endif #ifndef NO_MICO_RTOS mico_rtos_set_semaphore( &uart_interfaces[ uart ].tx_complete ); #else uart_interfaces[ uart ].rx_complete = true; #endif } #ifndef NO_MICO_RTOS mico_rtos_get_semaphore( &uart_interfaces[ uart ].tx_complete, MICO_NEVER_TIMEOUT ); #else while(uart_interfaces[ uart ].tx_complete == false); uart_interfaces[ uart ].tx_complete = false; #endif // return uart_interfaces[uart].tx_dma_result; MicoMcuPowerSaveConfig(true); #ifndef NO_MICO_RTOS mico_rtos_unlock_mutex(&uart_interfaces[uart].tx_mutex); #endif return kNoErr; } void UART_DRV_CompleteReceiveData(uint32_t instance) { assert(instance < HW_UART_INSTANCE_COUNT); uart_state_t * uartState = (uart_state_t *)g_uartStatePtr[instance]; uint32_t baseAddr = g_uartBaseAddr[instance]; mico_uart_t uart = getUartBy(instance); /* Disable receive data full interrupt */ UART_HAL_SetRxDataRegFullIntCmd(baseAddr, false); /* Signal the synchronous completion object. */ if (uartState->isRxBlocking) { mico_rtos_set_semaphore(&uart_interfaces[uart].rx_complete); //OSA_SemaPost(&uartState->rxIrqSync); } /* Update the information of the module driver state */ uartState->isRxBusy = false; }
void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable) { IRQn_Type irq_n = (IRQn_Type)0; uint32_t vector = 0; switch (obj->index) { case 0: irq_n=UART0_RX_TX_IRQn; vector = (uint32_t)&uart0_irq; break; case 1: irq_n=UART1_RX_TX_IRQn; vector = (uint32_t)&uart1_irq; break; case 2: irq_n=UART2_RX_TX_IRQn; vector = (uint32_t)&uart2_irq; break; #if (UART_NUM > 3) case 3: irq_n=UART3_RX_TX_IRQn; vector = (uint32_t)&uart3_irq; break; case 4: irq_n=UART4_RX_TX_IRQn; vector = (uint32_t)&uart4_irq; break; #endif } uint32_t uart_addrs[] = UART_BASE_ADDRS; if (enable) { switch (irq) { case RxIrq: UART_HAL_SetRxDataRegFullIntCmd(uart_addrs[obj->index], true); break; case TxIrq: UART_HAL_SetTxDataRegEmptyIntCmd(uart_addrs[obj->index], true); break; } NVIC_SetVector(irq_n, vector); NVIC_EnableIRQ(irq_n); } else { // disable int all_disabled = 0; SerialIrq other_irq = (irq == RxIrq) ? (TxIrq) : (RxIrq); switch (irq) { case RxIrq: UART_HAL_SetRxDataRegFullIntCmd(uart_addrs[obj->index], false); break; case TxIrq: UART_HAL_SetTxDataRegEmptyIntCmd(uart_addrs[obj->index], false); break; } switch (other_irq) { case RxIrq: all_disabled = UART_HAL_GetRxDataRegFullIntCmd(uart_addrs[obj->index]) == 0; break; case TxIrq: all_disabled = UART_HAL_GetTxDataRegEmptyIntCmd(uart_addrs[obj->index]) == 0; break; } if (all_disabled) NVIC_DisableIRQ(irq_n); } }
uart_status_t UART_DRV_ReceiveDataBlocking(uint32_t instance, uint8_t * rxBuff, uint32_t rxSize, uint32_t timeout) { assert(rxBuff); assert(instance < HW_UART_INSTANCE_COUNT); mico_uart_t uart; uart_state_t * uartState = (uart_state_t *)g_uartStatePtr[instance]; uart_status_t error = kStatus_UART_Success; uint32_t baseAddr = g_uartBaseAddr[instance]; OSStatus Status; if(instance == BOARD_APP_UART_INSTANCE) uart = MICO_UART_1; /* Indicates current transaction is blocking.*/ uartState->isRxBlocking = true; if (uartState->isRxBusy) { return kStatus_UART_RxBusy; } uartState->rxBuff = rxBuff; uartState->rxSize = rxSize; uartState->isRxBusy = true; /* enable the receive data full interrupt */ UART_HAL_SetRxDataRegFullIntCmd(baseAddr, true); /* Wait until all the data is received or for timeout.*/ Status = mico_rtos_get_semaphore( &uart_interfaces[uart].rx_complete, timeout ); if (Status != kNoErr) { /* Abort the transfer so it doesn't continue unexpectedly.*/ UART_DRV_AbortReceivingData(instance); error = kStatus_UART_Timeout; // kGeneralErr; } return error; }