// This fuction sorts the UE in order their dlsch buffer and CQI
void sort_UEs (module_id_t Mod_idP,
int frameP,
sub_frame_t subframeP)
{
int UE_id1,UE_id2;
int pCC_id1,pCC_id2;
int cqi1,cqi2,round1,round2;
int i=0,ii=0,j=0;
rnti_t rnti1,rnti2;
UE_list_t *UE_list = &eNB_mac_inst[Mod_idP].UE_list;
for (i=UE_list->head; i>=0; i=UE_list->next[i]) {
for(ii=UE_list->next[i]; ii>=0; ii=UE_list->next[ii]) {
UE_id1 = i;
rnti1 = UE_RNTI(Mod_idP,UE_id1);
if(rnti1 == NOT_A_RNTI)
continue;
pCC_id1 = UE_PCCID(Mod_idP,UE_id1);
cqi1 = maxcqi(Mod_idP,UE_id1); //
round1 = maxround(Mod_idP,rnti1,frameP,subframeP,0);
UE_id2 = ii;
rnti2 = UE_RNTI(Mod_idP,UE_id2);
if(rnti2 == NOT_A_RNTI)
continue;
cqi2 = maxcqi(Mod_idP,UE_id2);
round2 = maxround(Mod_idP,rnti2,frameP,subframeP,0); //mac_xface->get_ue_active_harq_pid(Mod_id,rnti2,subframe,&harq_pid2,&round2,0);
pCC_id2 = UE_PCCID(Mod_idP,UE_id2);
if(round2 > round1) { // Check first if one of the UEs has an active HARQ process which needs service and swap order
swap_UEs(UE_list,UE_id1,UE_id2,0);
} else if (round2 == round1) {
// RK->NN : I guess this is for fairness in the scheduling. This doesn't make sense unless all UEs have the same configuration of logical channels. This should be done on the sum of all information that has to be sent. And still it wouldn't ensure fairness. It should be based on throughput seen by each UE or maybe using the head_sdu_creation_time, i.e. swap UEs if one is waiting longer for service.
// for(j=0;j<MAX_NUM_LCID;j++){
// if (eNB_mac_inst[Mod_id][pCC_id1].UE_template[UE_id1].dl_buffer_info[j] <
// eNB_mac_inst[Mod_id][pCC_id2].UE_template[UE_id2].dl_buffer_info[j]){
// first check the buffer status for SRB1 and SRB2
if ( (UE_list->UE_template[pCC_id1][UE_id1].dl_buffer_info[1] + UE_list->UE_template[pCC_id1][UE_id1].dl_buffer_info[2]) <
(UE_list->UE_template[pCC_id2][UE_id2].dl_buffer_info[1] + UE_list->UE_template[pCC_id2][UE_id2].dl_buffer_info[2]) ) {
swap_UEs(UE_list,UE_id1,UE_id2,0);
} else if (UE_list->UE_template[pCC_id1][UE_id1].dl_buffer_head_sdu_creation_time_max <
UE_list->UE_template[pCC_id2][UE_id2].dl_buffer_head_sdu_creation_time_max ) {
swap_UEs(UE_list,UE_id1,UE_id2,0);
} else if (UE_list->UE_template[pCC_id1][UE_id1].dl_buffer_total <
UE_list->UE_template[pCC_id2][UE_id2].dl_buffer_total ) {
swap_UEs(UE_list,UE_id1,UE_id2,0);
} else if (cqi1 < cqi2) {
swap_UEs(UE_list,UE_id1,UE_id2,0);
}
}
}
}
}
void sort_ue_ul (module_id_t module_idP,int frameP, sub_frame_t subframeP){
int UE_id1,UE_id2;
int pCCid1,pCCid2;
int round1,round2;
int i=0,ii=0,j=0;
rnti_t rnti1,rnti2;
UE_list_t *UE_list = &eNB_mac_inst[module_idP].UE_list;
for (i=UE_list->head_ul;i>=0;i=UE_list->next_ul[i]) {
//LOG_I(MAC,"sort ue ul i %d\n",i);
rnti1 = UE_RNTI(module_idP,i);
if(rnti1 == 0)
continue;
UE_id1 = i;
pCCid1 = UE_PCCID(module_idP,UE_id1);
round1 = maxround(module_idP,rnti1,frameP,subframeP,1);
for (ii=UE_list->next_ul[i];ii>=0;ii=UE_list->next_ul[ii]) {
//LOG_I(MAC,"sort ul ue 2 ii %d\n",ii);
rnti2 = UE_RNTI(module_idP,ii);
if(rnti2 == 0)
continue;
UE_id2 = ii;
pCCid2 = UE_PCCID(module_idP,UE_id2);
round2 = maxround(module_idP,rnti2,frameP,subframeP,1);
if(round2 > round1){
swap_UEs(UE_list,UE_id1,UE_id2,1);
}
else if (round2 == round1){
if (UE_list->UE_template[pCCid1][UE_id1].ul_buffer_info[LCGID0] < UE_list->UE_template[pCCid2][UE_id2].ul_buffer_info[LCGID0]){
swap_UEs(UE_list,UE_id1,UE_id2,1);
}
else if (UE_list->UE_template[pCCid1][UE_id1].ul_total_buffer < UE_list->UE_template[pCCid2][UE_id2].ul_total_buffer){
swap_UEs(UE_list,UE_id1,UE_id2,1);
}
else if (UE_list->UE_template[pCCid1][UE_id1].pre_assigned_mcs_ul < UE_list->UE_template[pCCid2][UE_id2].pre_assigned_mcs_ul){
if (UE_list->UE_template[pCCid2][UE_id2].ul_total_buffer > 0 )
swap_UEs(UE_list,UE_id1,UE_id2,1);
}
}
}
}
}
int maxcqi(module_id_t Mod_id,int32_t UE_id) {
LTE_eNB_UE_stats *eNB_UE_stats = NULL;
UE_list_t *UE_list = &eNB_mac_inst[Mod_id].UE_list;
int CC_id,n;
int CQI = 0;
for (n=0;n<UE_list->numactiveCCs[UE_id];n++) {
CC_id = UE_list->ordered_CCids[n][UE_id];
eNB_UE_stats = mac_xface->get_eNB_UE_stats(Mod_id,CC_id,UE_RNTI(Mod_id,UE_id));
if (eNB_UE_stats==NULL)
mac_xface->macphy_exit("maxcqi: could not get eNB_UE_stats\n");
if (eNB_UE_stats->DL_cqi[0] > CQI)
CQI = eNB_UE_stats->DL_cqi[0];
}
return(CQI);
}
void assign_max_mcs_min_rb(module_id_t module_idP,int frameP, sub_frame_t subframeP, uint16_t *first_rb){
int i;
uint16_t n,UE_id;
uint8_t CC_id;
rnti_t rnti = -1;
int mcs=cmin(16,openair_daq_vars.target_ue_ul_mcs);
int rb_table_index=0,tbs,tx_power;
UE_list_t *UE_list = &eNB_mac_inst[module_idP].UE_list;
UE_TEMPLATE *UE_template;
LTE_DL_FRAME_PARMS *frame_parms;
for (i=UE_list->head_ul;i>=0;i=UE_list->next_ul[i]) {
rnti = UE_RNTI(module_idP,i);
if (rnti==0)
continue;
UE_id = i;
for (n=0;n<UE_list->numactiveULCCs[UE_id];n++) {
// This is the actual CC_id in the list
CC_id = UE_list->ordered_ULCCids[n][UE_id];
frame_parms=mac_xface->get_lte_frame_parms(module_idP,CC_id);
UE_template = &UE_list->UE_template[CC_id][UE_id];
// if this UE has UL traffic
if (UE_template->ul_total_buffer > 0 ) {
tbs = mac_xface->get_TBS_UL(mcs,1);
// fixme: set use_srs flag
tx_power= mac_xface->estimate_ue_tx_power(tbs,rb_table[rb_table_index],0,frame_parms->Ncp,0);
while (((UE_template->phr_info - tx_power) < 0 ) &&
(mcs > 3)){
// LOG_I(MAC,"UE_template->phr_info %d tx_power %d mcs %d\n", UE_template->phr_info,tx_power, mcs);
mcs--;
tbs = mac_xface->get_TBS_UL(mcs,rb_table[rb_table_index]);
tx_power = mac_xface->estimate_ue_tx_power(tbs,rb_table[rb_table_index],0,frame_parms->Ncp,0); // fixme: set use_srs
}
while ((tbs < UE_template->ul_total_buffer) &&
(rb_table[rb_table_index]<(frame_parms->N_RB_UL-first_rb[CC_id])) &&
((UE_template->phr_info - tx_power) > 0) &&
(rb_table_index < 33 )){
// LOG_I(MAC,"tbs %d ul buffer %d rb table %d max ul rb %d\n", tbs, UE_template->ul_total_buffer, rb_table[rb_table_index], frame_parms->N_RB_UL-first_rb[CC_id]);
rb_table_index++;
tbs = mac_xface->get_TBS_UL(mcs,rb_table[rb_table_index]);
tx_power = mac_xface->estimate_ue_tx_power(tbs,rb_table[rb_table_index],0,frame_parms->Ncp,0);
}
UE_template->ue_tx_power = tx_power;
if (rb_table[rb_table_index]>(frame_parms->N_RB_UL-first_rb[CC_id]-1)) {
rb_table_index--;
}
// 1 or 2 PRB with cqi enabled does not work well!
if (rb_table[rb_table_index]<3)
rb_table_index=2; //3PRB
UE_template->pre_assigned_mcs_ul=mcs;
UE_template->pre_allocated_rb_table_index_ul=rb_table_index;
UE_template->pre_allocated_nb_rb_ul= rb_table[rb_table_index];
LOG_D(MAC,"[eNB %d] frame %d subframe %d: for UE %d CC %d: pre-assigned mcs %d, pre-allocated rb_table[%d]=%d RBs (phr %d, tx power %d)\n",
module_idP, frameP, subframeP, UE_id, CC_id,
UE_template->pre_assigned_mcs_ul,
UE_template->pre_allocated_rb_table_index_ul,
UE_template->pre_allocated_nb_rb_ul,
UE_template->phr_info,tx_power);
} else {
UE_template->pre_allocated_rb_table_index_ul=-1;
UE_template->pre_allocated_nb_rb_ul=0;
}
}
}
}
// This function stores the downlink buffer for all the logical channels
void store_dlsch_buffer (module_id_t Mod_id,
frame_t frameP,
sub_frame_t subframeP){
int UE_id,i;
rnti_t rnti;
mac_rlc_status_resp_t rlc_status;
UE_list_t *UE_list = &eNB_mac_inst[Mod_id].UE_list;
UE_TEMPLATE *UE_template;
for (UE_id=UE_list->head;UE_id>=0;UE_id=UE_list->next[UE_id]){
UE_template = &UE_list->UE_template[UE_PCCID(Mod_id,UE_id)][UE_id];
// clear logical channel interface variables
UE_template->dl_buffer_total = 0;
UE_template->dl_pdus_total = 0;
for(i=0;i< MAX_NUM_LCID; i++) {
UE_template->dl_buffer_info[i]=0;
UE_template->dl_pdus_in_buffer[i]=0;
UE_template->dl_buffer_head_sdu_creation_time[i]=0;
UE_template->dl_buffer_head_sdu_remaining_size_to_send[i]=0;
}
rnti = UE_RNTI(Mod_id,UE_id);
for(i=0;i< MAX_NUM_LCID; i++){ // loop over all the logical channels
rlc_status = mac_rlc_status_ind(Mod_id,UE_id, frameP,ENB_FLAG_YES,MBMS_FLAG_NO,i,0 );
UE_template->dl_buffer_info[i] = rlc_status.bytes_in_buffer; //storing the dlsch buffer for each logical channel
UE_template->dl_pdus_in_buffer[i] = rlc_status.pdus_in_buffer;
UE_template->dl_buffer_head_sdu_creation_time[i] = rlc_status.head_sdu_creation_time ;
UE_template->dl_buffer_head_sdu_creation_time_max = cmax(UE_template->dl_buffer_head_sdu_creation_time_max,
rlc_status.head_sdu_creation_time );
UE_template->dl_buffer_head_sdu_remaining_size_to_send[i] = rlc_status.head_sdu_remaining_size_to_send;
UE_template->dl_buffer_head_sdu_is_segmented[i] = rlc_status.head_sdu_is_segmented;
UE_template->dl_buffer_total += UE_template->dl_buffer_info[i];//storing the total dlsch buffer
UE_template->dl_pdus_total += UE_template->dl_pdus_in_buffer[i];
#ifdef DEBUG_eNB_SCHEDULER
/* note for dl_buffer_head_sdu_remaining_size_to_send[i] :
* 0 if head SDU has not been segmented (yet), else remaining size not already segmented and sent
*/
if (UE_template->dl_buffer_info[i]>0)
LOG_D(MAC,"[eNB %d] Frame %d Subframe %d : RLC status for UE %d in LCID%d: total of %d pdus and size %d, head sdu queuing time %d, remaining size %d, is segmeneted %d \n",
Mod_id, frameP, subframeP, UE_id,
i, UE_template->dl_pdus_in_buffer[i],UE_template->dl_buffer_info[i],
UE_template->dl_buffer_head_sdu_creation_time[i],
UE_template->dl_buffer_head_sdu_remaining_size_to_send[i],
UE_template->dl_buffer_head_sdu_is_segmented[i]
);
#endif
}
//#ifdef DEBUG_eNB_SCHEDULER
if ( UE_template->dl_buffer_total>0)
LOG_D(MAC,"[eNB %d] Frame %d Subframe %d : RLC status for UE %d : total DL buffer size %d and total number of pdu %d \n",
Mod_id, frameP, subframeP, UE_id,
UE_template->dl_buffer_total,
UE_template->dl_pdus_total
);
//#endif
}
}
void ulsch_scheduler_pre_processor(module_id_t module_idP,
int frameP,
sub_frame_t subframeP,
uint16_t *first_rb,
uint8_t aggregation,
uint32_t *nCCE){
int16_t i;
uint16_t UE_id,n,r;
uint8_t CC_id, round, harq_pid;
uint16_t nb_allocated_rbs[MAX_NUM_CCs][NUMBER_OF_UE_MAX],total_allocated_rbs[MAX_NUM_CCs],average_rbs_per_user[MAX_NUM_CCs];
int16_t total_remaining_rbs[MAX_NUM_CCs];
uint16_t max_num_ue_to_be_scheduled=0,total_ue_count=0;
rnti_t rnti= -1;
uint32_t nCCE_to_be_used[CC_id];
UE_list_t *UE_list = &eNB_mac_inst[module_idP].UE_list;
UE_TEMPLATE *UE_template;
LTE_DL_FRAME_PARMS *frame_parms;
// LOG_I(MAC,"store ulsch buffers\n");
// convert BSR to bytes for comparison with tbs
store_ulsch_buffer(module_idP,frameP, subframeP);
//LOG_I(MAC,"assign max mcs min rb\n");
// maximize MCS and then allocate required RB according to the buffer occupancy with the limit of max available UL RB
assign_max_mcs_min_rb(module_idP,frameP, subframeP, first_rb);
//LOG_I(MAC,"sort ue \n");
// sort ues
sort_ue_ul (module_idP,frameP, subframeP);
// we need to distribute RBs among UEs
// step1: reset the vars
for (CC_id=0;CC_id<MAX_NUM_CCs;CC_id++) {
nCCE_to_be_used[CC_id]= nCCE[CC_id];
total_allocated_rbs[CC_id]=0;
total_remaining_rbs[CC_id]=0;
average_rbs_per_user[CC_id]=0;
for (i=UE_list->head_ul;i>=0;i=UE_list->next_ul[i]) {
nb_allocated_rbs[CC_id][i]=0;
}
}
//LOG_I(MAC,"step2 \n");
// step 2: calculate the average rb per UE
total_ue_count =0;
max_num_ue_to_be_scheduled=0;
for (i=UE_list->head_ul;i>=0;i=UE_list->next_ul[i]) {
rnti = UE_RNTI(module_idP,i);
if (rnti==0)
continue;
UE_id = i;
for (n=0;n<UE_list->numactiveULCCs[UE_id];n++) {
// This is the actual CC_id in the list
CC_id = UE_list->ordered_ULCCids[n][UE_id];
UE_template = &UE_list->UE_template[CC_id][UE_id];
average_rbs_per_user[CC_id]=0;
frame_parms = mac_xface->get_lte_frame_parms(module_idP,CC_id);
if (UE_template->pre_allocated_nb_rb_ul > 0) {
total_ue_count+=1;
}
if((mac_xface->get_nCCE_max(module_idP,CC_id) - nCCE_to_be_used[CC_id]) > (1<<aggregation)){
nCCE_to_be_used[CC_id] = nCCE_to_be_used[CC_id] + (1<<aggregation);
max_num_ue_to_be_scheduled+=1;
}
if (total_ue_count == 0)
average_rbs_per_user[CC_id] = 0;
else if (total_ue_count == 1 ) // increase the available RBs, special case,
average_rbs_per_user[CC_id] = frame_parms->N_RB_UL-first_rb[CC_id]+1;
else if( (total_ue_count <= (frame_parms->N_RB_DL-first_rb[CC_id])) &&
(total_ue_count <= max_num_ue_to_be_scheduled))
average_rbs_per_user[CC_id] = (uint16_t) floor((frame_parms->N_RB_UL-first_rb[CC_id])/total_ue_count);
else if (max_num_ue_to_be_scheduled > 0 )
average_rbs_per_user[CC_id] = (uint16_t) floor((frame_parms->N_RB_UL-first_rb[CC_id])/max_num_ue_to_be_scheduled);
else {
average_rbs_per_user[CC_id]=1;
LOG_W(MAC,"[eNB %d] frame %d subframe %d: UE %d CC %d: can't get average rb per user (should not be here)\n",
module_idP,frameP,subframeP,UE_id,CC_id);
}
}
}
LOG_D(MAC,"[eNB %d] Frame %d subframe %d: total ue %d, max num ue to be scheduled %d\n",
module_idP, frameP, subframeP,total_ue_count, max_num_ue_to_be_scheduled);
//LOG_D(MAC,"step3\n");
// step 3: assigne RBS
for (i=UE_list->head_ul;i>=0;i=UE_list->next_ul[i]) {
rnti = UE_RNTI(module_idP,i);
if (rnti==0)
continue;
UE_id = i;
for (n=0;n<UE_list->numactiveULCCs[UE_id];n++) {
// This is the actual CC_id in the list
CC_id = UE_list->ordered_ULCCids[n][UE_id];
mac_xface->get_ue_active_harq_pid(module_idP,CC_id,rnti,frameP,subframeP,&harq_pid,&round,1);
if(round>0)
nb_allocated_rbs[CC_id][UE_id] = UE_list->UE_template[CC_id][UE_id].nb_rb_ul[harq_pid];
else
nb_allocated_rbs[CC_id][UE_id] = cmin(UE_template->pre_allocated_nb_rb_ul, average_rbs_per_user[CC_id]);
total_allocated_rbs[CC_id]+= nb_allocated_rbs[CC_id][UE_id];
}
}
// step 4: assigne the remaining RBs and set the pre_allocated rbs accordingly
for(r=0;r<2;r++){
for (i=UE_list->head_ul;i>=0;i=UE_list->next_ul[i]) {
rnti = UE_RNTI(module_idP,i);
if (rnti==0)
continue;
UE_id = i;
for (n=0;n<UE_list->numactiveULCCs[UE_id];n++) {
// This is the actual CC_id in the list
CC_id = UE_list->ordered_ULCCids[n][UE_id];
UE_template = &UE_list->UE_template[CC_id][UE_id];
frame_parms = mac_xface->get_lte_frame_parms(module_idP,CC_id);
total_remaining_rbs[CC_id]=frame_parms->N_RB_UL - first_rb[CC_id] - total_allocated_rbs[CC_id];
if (total_ue_count == 1 )
total_remaining_rbs[CC_id]+=1;
if ( r == 0 ) {
while ( (UE_template->pre_allocated_nb_rb_ul > 0 ) &&
(nb_allocated_rbs[CC_id][UE_id] < UE_template->pre_allocated_nb_rb_ul) &&
(total_remaining_rbs[CC_id] > 0)){
nb_allocated_rbs[CC_id][UE_id] = cmin(nb_allocated_rbs[CC_id][UE_id]+1,UE_template->pre_allocated_nb_rb_ul);
total_remaining_rbs[CC_id]--;
total_allocated_rbs[CC_id]++;
}
}
else {
UE_template->pre_allocated_nb_rb_ul= nb_allocated_rbs[CC_id][UE_id];
LOG_D(MAC,"******************UL Scheduling Information for UE%d CC_id %d ************************\n",UE_id, CC_id);
LOG_D(MAC,"[eNB %d] total RB allocated for UE%d CC_id %d = %d\n", module_idP, UE_id, CC_id, UE_template->pre_allocated_nb_rb_ul);
}
}
}
}
for (CC_id=0;CC_id<MAX_NUM_CCs;CC_id++) {
frame_parms= mac_xface->get_lte_frame_parms(module_idP,CC_id);
if (total_allocated_rbs[CC_id]>0)
LOG_D(MAC,"[eNB %d] total RB allocated for all UEs = %d/%d\n", module_idP, total_allocated_rbs[CC_id], frame_parms->N_RB_UL - first_rb[CC_id]);
}
}
// This function assigns pre-available RBS to each UE in specified sub-bands before scheduling is done
void dlsch_scheduler_pre_processor (module_id_t Mod_id,
frame_t frameP,
sub_frame_t subframeP,
uint8_t dl_pow_off[MAX_NUM_CCs][NUMBER_OF_UE_MAX],
uint16_t pre_nb_available_rbs[MAX_NUM_CCs][NUMBER_OF_UE_MAX],
int N_RBG[MAX_NUM_CCs],
unsigned char rballoc_sub_UE[MAX_NUM_CCs][NUMBER_OF_UE_MAX][N_RBG_MAX],
int *mbsfn_flag){
unsigned char rballoc_sub[MAX_NUM_CCs][N_RBG_MAX],harq_pid=0,harq_pid1=0,harq_pid2=0,round=0,round1=0,round2=0,total_ue_count;
unsigned char MIMO_mode_indicator[MAX_NUM_CCs][N_RBG_MAX];
int UE_id, UE_id2, i;
uint16_t ii,j;
uint16_t nb_rbs_required[MAX_NUM_CCs][NUMBER_OF_UE_MAX];
uint16_t nb_rbs_required_remaining[MAX_NUM_CCs][NUMBER_OF_UE_MAX];
uint16_t nb_rbs_required_remaining_1[MAX_NUM_CCs][NUMBER_OF_UE_MAX];
uint16_t i1,i2,i3,r1=0;
uint16_t average_rbs_per_user[MAX_NUM_CCs];
rnti_t rnti,rnti1,rnti2;
LTE_eNB_UE_stats *eNB_UE_stats1 = NULL;
LTE_eNB_UE_stats *eNB_UE_stats2 = NULL;
int min_rb_unit[MAX_NUM_CCs];
uint8_t CC_id;
UE_list_t *UE_list = &eNB_mac_inst[Mod_id].UE_list;
LTE_DL_FRAME_PARMS *frame_parms[MAX_NUM_CCs];
int rrc_status = RRC_IDLE;
int transmission_mode = 0;
for (CC_id=0;CC_id<MAX_NUM_CCs;CC_id++) {
if (mbsfn_flag[CC_id]>0) // If this CC is allocated for MBSFN skip it here
continue;
frame_parms[CC_id] = mac_xface->get_lte_frame_parms(Mod_id,CC_id);
min_rb_unit[CC_id]=get_min_rb_unit(Mod_id,CC_id);
for (i=UE_list->head;i>=0;i=UE_list->next[i]) {
UE_id = i;
// Initialize scheduling information for all active UEs
dlsch_scheduler_pre_processor_reset(UE_id,
CC_id,
N_RBG[CC_id],
dl_pow_off,
nb_rbs_required,
pre_nb_available_rbs,
nb_rbs_required_remaining,
rballoc_sub_UE,
rballoc_sub,
MIMO_mode_indicator);
}
}
// Store the DLSCH buffer for each logical channel
store_dlsch_buffer (Mod_id,frameP,subframeP);
// Calculate the number of RBs required by each UE on the basis of logical channel's buffer
assign_rbs_required (Mod_id,frameP,subframeP,nb_rbs_required,min_rb_unit);
// Sorts the user on the basis of dlsch logical channel buffer and CQI
sort_UEs (Mod_id,frameP,subframeP);
total_ue_count =0;
// loop over all active UEs
for (i=UE_list->head;i>=0;i=UE_list->next[i]) {
rnti = UE_RNTI(Mod_id,i);
if(rnti == 0)
continue;
UE_id = i;
for (ii=0;ii<UE_num_active_CC(UE_list,UE_id);ii++) {
CC_id = UE_list->ordered_CCids[ii][UE_id];
average_rbs_per_user[CC_id]=0;
mac_xface->get_ue_active_harq_pid(Mod_id,CC_id,rnti,frameP,subframeP,&harq_pid,&round,0);
if(round>0)
nb_rbs_required[CC_id][UE_id] = UE_list->UE_template[CC_id][UE_id].nb_rb[harq_pid];
//nb_rbs_required_remaining[UE_id] = nb_rbs_required[UE_id];
if (nb_rbs_required[CC_id][UE_id] > 0) {
total_ue_count = total_ue_count + 1;
}
// hypotetical assignement
/*
* If schedule is enabled and if the priority of the UEs is modified
* The average rbs per logical channel per user will depend on the level of
* priority. Concerning the hypothetical assignement, we should assign more
* rbs to prioritized users. Maybe, we can do a mapping between the
* average rbs per user and the level of priority or multiply the average rbs
* per user by a coefficient which represents the degree of priority.
*/
if (total_ue_count == 0)
average_rbs_per_user[CC_id] = 0;
else if( (min_rb_unit[CC_id] * total_ue_count) <= (frame_parms[CC_id]->N_RB_DL) )
average_rbs_per_user[CC_id] = (uint16_t) floor(frame_parms[CC_id]->N_RB_DL/total_ue_count);
else
average_rbs_per_user[CC_id] = min_rb_unit[CC_id];
}
}
// note: nb_rbs_required is assigned according to total_buffer_dl
// extend nb_rbs_required to capture per LCID RB required
for(i=UE_list->head;i>=0;i=UE_list->next[i]){
for (ii=0;ii<UE_num_active_CC(UE_list,i);ii++) {
CC_id = UE_list->ordered_CCids[ii][i];
// control channel
if (mac_get_rrc_status(Mod_id,1,i) < RRC_RECONFIGURED)
nb_rbs_required_remaining_1[CC_id][i] = nb_rbs_required[CC_id][i];
else
nb_rbs_required_remaining_1[CC_id][i] = cmin(average_rbs_per_user[CC_id],nb_rbs_required[CC_id][i]);
}
}
//Allocation to UEs is done in 2 rounds,
// 1st round: average number of RBs allocated to each UE
// 2nd round: remaining RBs are allocated to high priority UEs
for(r1=0;r1<2;r1++){
for(i=UE_list->head; i>=0;i=UE_list->next[i]) {
for (ii=0;ii<UE_num_active_CC(UE_list,i);ii++) {
CC_id = UE_list->ordered_CCids[ii][i];
if(r1 == 0)
nb_rbs_required_remaining[CC_id][i] = nb_rbs_required_remaining_1[CC_id][i];
else // rb required based only on the buffer - rb allloctaed in the 1st round + extra reaming rb form the 1st round
nb_rbs_required_remaining[CC_id][i] = nb_rbs_required[CC_id][i]-nb_rbs_required_remaining_1[CC_id][i]+nb_rbs_required_remaining[CC_id][i];
LOG_D(MAC,"round %d : nb_rbs_required_remaining[%d][%d]= %d (remaining_1 %d, required %d, pre_nb_available_rbs %d, N_RBG %d, rb_unit %d)\n",
r1, CC_id, i,
nb_rbs_required_remaining[CC_id][i],
nb_rbs_required_remaining_1[CC_id][i],
nb_rbs_required[CC_id][i],
pre_nb_available_rbs[CC_id][i],
N_RBG[CC_id],
min_rb_unit[CC_id]);
}
}
if (total_ue_count > 0 ) {
for(i=UE_list->head; i>=0;i=UE_list->next[i]) {
UE_id = i;
for (ii=0;ii<UE_num_active_CC(UE_list,UE_id);ii++) {
CC_id = UE_list->ordered_CCids[ii][UE_id];
rnti = UE_RNTI(Mod_id,UE_id);
// LOG_D(MAC,"UE %d rnti 0x\n", UE_id, rnti );
if(rnti == 0)
continue;
transmission_mode = mac_xface->get_transmission_mode(Mod_id,CC_id,rnti);
mac_xface->get_ue_active_harq_pid(Mod_id,CC_id,rnti,frameP,subframeP,&harq_pid,&round,0);
rrc_status = mac_get_rrc_status(Mod_id,1,UE_id);
/* 1st allocate for the retx */
// retransmission in data channels
// control channel in the 1st transmission
// data channel for all TM
LOG_D(MAC,"calling dlsch_scheduler_pre_processor_allocate .. \n ");
dlsch_scheduler_pre_processor_allocate (Mod_id,
UE_id,
CC_id,
N_RBG[CC_id],
transmission_mode,
min_rb_unit[CC_id],
frame_parms[CC_id]->N_RB_DL,
dl_pow_off,
nb_rbs_required,
pre_nb_available_rbs,
nb_rbs_required_remaining,
rballoc_sub_UE,
rballoc_sub,
MIMO_mode_indicator);
#ifdef TM5
// data chanel TM5: to be revisted
if ((round == 0 ) &&
(transmission_mode == 5) &&
(dl_pow_off[CC_id][UE_id] != 1)){
for(j=0;j<N_RBG[CC_id];j+=2) {
if( (((j == (N_RBG[CC_id]-1))&& (rballoc_sub[CC_id][j] == 0) && (rballoc_sub_UE[CC_id][UE_id][j] == 0)) ||
((j < (N_RBG[CC_id]-1)) && (rballoc_sub[CC_id][j+1] == 0) && (rballoc_sub_UE[CC_id][UE_id][j+1] == 0)) ) &&
(nb_rbs_required_remaining[CC_id][UE_id]>0)){
for (ii = UE_list->next[i+1];ii >=0;ii=UE_list->next[ii]) {
UE_id2 = ii;
rnti2 = UE_RNTI(Mod_id,UE_id2);
if(rnti2 == 0)
continue;
eNB_UE_stats2 = mac_xface->get_eNB_UE_stats(Mod_id,CC_id,rnti2);
mac_xface->get_ue_active_harq_pid(Mod_id,CC_id,rnti2,frameP,subframeP,&harq_pid2,&round2,0);
if ((mac_get_rrc_status(Mod_id,1,UE_id2) >= RRC_RECONFIGURED) &&
(round2==0) &&
(mac_xface->get_transmission_mode(Mod_id,CC_id,rnti2)==5) &&
(dl_pow_off[CC_id][UE_id2] != 1)) {
if( (((j == (N_RBG[CC_id]-1)) && (rballoc_sub_UE[CC_id][UE_id2][j] == 0)) ||
((j < (N_RBG[CC_id]-1)) && (rballoc_sub_UE[CC_id][UE_id2][j+1] == 0)) ) &&
(nb_rbs_required_remaining[CC_id][UE_id2]>0)){
if((((eNB_UE_stats2->DL_pmi_single^eNB_UE_stats1->DL_pmi_single)<<(14-j))&0xc000)== 0x4000){ //MU-MIMO only for 25 RBs configuration
rballoc_sub[CC_id][j] = 1;
rballoc_sub_UE[CC_id][UE_id][j] = 1;
rballoc_sub_UE[CC_id][UE_id2][j] = 1;
MIMO_mode_indicator[CC_id][j] = 0;
if (j< N_RBG[CC_id]-1) {
rballoc_sub[CC_id][j+1] = 1;
rballoc_sub_UE[CC_id][UE_id][j+1] = 1;
rballoc_sub_UE[CC_id][UE_id2][j+1] = 1;
MIMO_mode_indicator[CC_id][j+1] = 0;
}
dl_pow_off[CC_id][UE_id] = 0;
dl_pow_off[CC_id][UE_id2] = 0;
if ((j == N_RBG[CC_id]-1) &&
((PHY_vars_eNB_g[Mod_id][CC_id]->lte_frame_parms.N_RB_DL == 25) ||
(PHY_vars_eNB_g[Mod_id][CC_id]->lte_frame_parms.N_RB_DL == 50))){
nb_rbs_required_remaining[CC_id][UE_id] = nb_rbs_required_remaining[CC_id][UE_id] - min_rb_unit[CC_id]+1;
pre_nb_available_rbs[CC_id][UE_id] = pre_nb_available_rbs[CC_id][UE_id] + min_rb_unit[CC_id]-1;
nb_rbs_required_remaining[CC_id][UE_id2] = nb_rbs_required_remaining[CC_id][UE_id2] - min_rb_unit[CC_id]+1;
pre_nb_available_rbs[CC_id][UE_id2] = pre_nb_available_rbs[CC_id][UE_id2] + min_rb_unit[CC_id]-1;
}
else {
nb_rbs_required_remaining[CC_id][UE_id] = nb_rbs_required_remaining[CC_id][UE_id] - 4;
pre_nb_available_rbs[CC_id][UE_id] = pre_nb_available_rbs[CC_id][UE_id] + 4;
nb_rbs_required_remaining[CC_id][UE_id2] = nb_rbs_required_remaining[CC_id][UE_id2] - 4;
pre_nb_available_rbs[CC_id][UE_id2] = pre_nb_available_rbs[CC_id][UE_id2] + 4;
}
break;
}
}
}
}
}
}
}
#endif
}
}
} // total_ue_count
} // end of for for r1 and r2
#ifdef TM5
// This has to be revisited!!!!
for (CC_id=0;CC_id<MAX_NUM_CCs;CC_id++) {
i1=0;
i2=0;
i3=0;
for (j=0;j<N_RBG[CC_id];j++){
if(MIMO_mode_indicator[CC_id][j] == 2)
i1 = i1+1;
else if(MIMO_mode_indicator[CC_id][j] == 1)
i2 = i2+1;
else if(MIMO_mode_indicator[CC_id][j] == 0)
i3 = i3+1;
}
if((i1 < N_RBG[CC_id]) && (i2>0) && (i3==0))
PHY_vars_eNB_g[Mod_id][CC_id]->check_for_SUMIMO_transmissions = PHY_vars_eNB_g[Mod_id][CC_id]->check_for_SUMIMO_transmissions + 1;
if(i3 == N_RBG[CC_id] && i1==0 && i2==0)
PHY_vars_eNB_g[Mod_id][CC_id]->FULL_MUMIMO_transmissions = PHY_vars_eNB_g[Mod_id][CC_id]->FULL_MUMIMO_transmissions + 1;
if((i1 < N_RBG[CC_id]) && (i3 > 0))
PHY_vars_eNB_g[Mod_id][CC_id]->check_for_MUMIMO_transmissions = PHY_vars_eNB_g[Mod_id][CC_id]->check_for_MUMIMO_transmissions + 1;
PHY_vars_eNB_g[Mod_id][CC_id]->check_for_total_transmissions = PHY_vars_eNB_g[Mod_id][CC_id]->check_for_total_transmissions + 1;
}
#endif
for(i=UE_list->head; i>=0;i=UE_list->next[i]) {
UE_id = i;
for (ii=0;ii<UE_num_active_CC(UE_list,UE_id);ii++) {
CC_id = UE_list->ordered_CCids[ii][UE_id];
//PHY_vars_eNB_g[Mod_id]->mu_mimo_mode[UE_id].dl_pow_off = dl_pow_off[UE_id];
LOG_D(MAC,"******************DL Scheduling Information for UE%d ************************\n",UE_id);
LOG_D(MAC,"dl power offset UE%d = %d \n",UE_id,dl_pow_off[CC_id][UE_id]);
LOG_D(MAC,"***********RB Alloc for every subband for UE%d ***********\n",UE_id);
for(j=0;j<N_RBG[CC_id];j++){
//PHY_vars_eNB_g[Mod_id]->mu_mimo_mode[UE_id].rballoc_sub[i] = rballoc_sub_UE[CC_id][UE_id][i];
LOG_D(MAC,"RB Alloc for UE%d and Subband%d = %d\n",UE_id,j,rballoc_sub_UE[CC_id][UE_id][j]);
}
//PHY_vars_eNB_g[Mod_id]->mu_mimo_mode[UE_id].pre_nb_available_rbs = pre_nb_available_rbs[CC_id][UE_id];
LOG_D(MAC,"Total RBs allocated for UE%d = %d\n",UE_id,pre_nb_available_rbs[CC_id][UE_id]);
}
}
}
void eNB_dlsch_ulsch_scheduler(module_id_t module_idP,uint8_t cooperation_flag, frame_t frameP, sub_frame_t subframeP) //, int calibration_flag) {
{
unsigned int nprb[MAX_NUM_CCs];
unsigned int nCCE[MAX_NUM_CCs];
int mbsfn_status[MAX_NUM_CCs];
uint32_t RBalloc[MAX_NUM_CCs];
protocol_ctxt_t ctxt;
#ifdef EXMIMO
int ret;
#endif
#if defined(ENABLE_ITTI)
MessageDef *msg_p;
const char *msg_name;
instance_t instance;
int result;
#endif
DCI_PDU *DCI_pdu[MAX_NUM_CCs];
int CC_id,i,next_i;
UE_list_t *UE_list=&eNB_mac_inst[module_idP].UE_list;
rnti_t rnti;
LOG_D(MAC,"[eNB %d] Frame %d, Subframe %d, entering MAC scheduler (UE_list->head %d)\n",module_idP, frameP, subframeP,UE_list->head);
start_meas(&eNB_mac_inst[module_idP].eNB_scheduler);
VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_ENB_DLSCH_ULSCH_SCHEDULER,VCD_FUNCTION_IN);
for (CC_id=0; CC_id<MAX_NUM_CCs; CC_id++) {
DCI_pdu[CC_id] = &eNB_mac_inst[module_idP].common_channels[CC_id].DCI_pdu;
nCCE[CC_id]=0;
nprb[CC_id]=0;
RBalloc[CC_id]=0;
mbsfn_status[CC_id]=0;
}
// refresh UE list based on UEs dropped by PHY in previous subframe
i = UE_list->head;
while (i>=0) {
rnti = UE_RNTI(module_idP, i);
CC_id = UE_PCCID(module_idP, i);
LOG_D(MAC,"UE %d: rnti %x (%p)\n", i, rnti,
mac_xface->get_eNB_UE_stats(module_idP, CC_id, rnti));
next_i= UE_list->next[i];
if (mac_xface->get_eNB_UE_stats(module_idP, CC_id, rnti)==NULL) {
mac_remove_ue(module_idP, i, frameP, subframeP);
}
i = next_i;
}
#if defined(ENABLE_ITTI)
do {
// Checks if a message has been sent to MAC sub-task
itti_poll_msg (TASK_MAC_ENB, &msg_p);
if (msg_p != NULL) {
msg_name = ITTI_MSG_NAME (msg_p);
instance = ITTI_MSG_INSTANCE (msg_p);
switch (ITTI_MSG_ID(msg_p)) {
case MESSAGE_TEST:
LOG_D(MAC, "Received %s\n", ITTI_MSG_NAME(msg_p));
break;
case RRC_MAC_BCCH_DATA_REQ:
LOG_D(MAC, "Received %s from %s: instance %d, frameP %d, eNB_index %d\n",
msg_name, ITTI_MSG_ORIGIN_NAME(msg_p), instance,
RRC_MAC_BCCH_DATA_REQ (msg_p).frame, RRC_MAC_BCCH_DATA_REQ (msg_p).enb_index);
// TODO process BCCH data req.
break;
case RRC_MAC_CCCH_DATA_REQ:
LOG_D(MAC, "Received %s from %s: instance %d, frameP %d, eNB_index %d\n",
msg_name, ITTI_MSG_ORIGIN_NAME(msg_p), instance,
RRC_MAC_CCCH_DATA_REQ (msg_p).frame, RRC_MAC_CCCH_DATA_REQ (msg_p).enb_index);
// TODO process CCCH data req.
break;
#ifdef Rel10
case RRC_MAC_MCCH_DATA_REQ:
LOG_D(MAC, "Received %s from %s: instance %d, frameP %d, eNB_index %d, mbsfn_sync_area %d\n",
msg_name, ITTI_MSG_ORIGIN_NAME(msg_p), instance,
RRC_MAC_MCCH_DATA_REQ (msg_p).frame, RRC_MAC_MCCH_DATA_REQ (msg_p).enb_index, RRC_MAC_MCCH_DATA_REQ (msg_p).mbsfn_sync_area);
// TODO process MCCH data req.
break;
#endif
default:
LOG_E(MAC, "Received unexpected message %s\n", msg_name);
break;
}
result = itti_free (ITTI_MSG_ORIGIN_ID(msg_p), msg_p);
AssertFatal (result == EXIT_SUCCESS, "Failed to free memory (%d)!\n", result);
}
} while(msg_p != NULL);
#endif
// clear DCI and BCCH contents before scheduling
for (CC_id=0; CC_id<MAX_NUM_CCs; CC_id++) {
DCI_pdu[CC_id]->Num_common_dci = 0;
DCI_pdu[CC_id]->Num_ue_spec_dci = 0;
eNB_mac_inst[module_idP].common_channels[CC_id].bcch_active = 0;
#ifdef Rel10
eNB_mac_inst[module_idP].common_channels[CC_id].mcch_active =0;
#endif
eNB_mac_inst[module_idP].frame = frameP;
eNB_mac_inst[module_idP].subframe = subframeP;
}
//if (subframeP%5 == 0)
//#ifdef EXMIMO
PROTOCOL_CTXT_SET_BY_MODULE_ID(&ctxt, module_idP, ENB_FLAG_YES, NOT_A_RNTI, frameP, 0,module_idP);
pdcp_run(&ctxt);
//#endif
// check HO
rrc_rx_tx(&ctxt,
0, // eNB index, unused in eNB
CC_id);
#ifdef Rel10
for (CC_id=0; CC_id<MAX_NUM_CCs; CC_id++) {
if (eNB_mac_inst[module_idP].common_channels[CC_id].MBMS_flag >0) {
start_meas(&eNB_mac_inst[module_idP].schedule_mch);
mbsfn_status[CC_id] = schedule_MBMS(module_idP,CC_id,frameP,subframeP);
stop_meas(&eNB_mac_inst[module_idP].schedule_mch);
}
}
#endif
// refresh UE list based on UEs dropped by PHY in previous subframe
/*
i=UE_list->head;
while (i>=0) {
next_i = UE_list->next[i];
LOG_T(MAC,"UE %d : rnti %x, stats %p\n",i,UE_RNTI(module_idP,i),mac_xface->get_eNB_UE_stats(module_idP,0,UE_RNTI(module_idP,i)));
if (mac_xface->get_eNB_UE_stats(module_idP,0,UE_RNTI(module_idP,i))==NULL) {
mac_remove_ue(module_idP,i,frameP);
}
i=next_i;
}
*/
switch (subframeP) {
case 0:
// FDD/TDD Schedule Downlink RA transmissions (RA response, Msg4 Contention resolution)
// Schedule ULSCH for FDD or subframeP 4 (TDD config 0,3,6)
// Schedule Normal DLSCH
schedule_RA(module_idP,frameP,subframeP,2,nprb,nCCE);
if (mac_xface->lte_frame_parms->frame_type == FDD) { //FDD
schedule_ulsch(module_idP,frameP,cooperation_flag,0,4,nCCE);//,calibration_flag);
} else if ((mac_xface->lte_frame_parms->tdd_config == TDD) || //TDD
(mac_xface->lte_frame_parms->tdd_config == 3) ||
(mac_xface->lte_frame_parms->tdd_config == 6)) {
//schedule_ulsch(module_idP,frameP,cooperation_flag,subframeP,4,nCCE);//,calibration_flag);
}
// schedule_ue_spec(module_idP,frameP,subframeP,nprb,nCCE,mbsfn_status);
fill_DLSCH_dci(module_idP,frameP,subframeP,RBalloc,1,mbsfn_status);
break;
case 1:
// TDD, schedule UL for subframeP 7 (TDD config 0,1) / subframeP 8 (TDD Config 6)
// FDD, schedule normal UL/DLSCH
if (mac_xface->lte_frame_parms->frame_type == TDD) { // TDD
switch (mac_xface->lte_frame_parms->tdd_config) {
case 0:
case 1:
schedule_ulsch(module_idP,frameP,cooperation_flag,subframeP,7,nCCE);
fill_DLSCH_dci(module_idP,frameP,subframeP,RBalloc,0,mbsfn_status);
break;
case 6:
schedule_ulsch(module_idP,frameP,cooperation_flag,subframeP,8,nCCE);
fill_DLSCH_dci(module_idP,frameP,subframeP,RBalloc,0,mbsfn_status);
break;
default:
break;
}
} else { //FDD
schedule_ue_spec(module_idP,frameP,subframeP,nprb,nCCE,mbsfn_status);
fill_DLSCH_dci(module_idP,frameP,subframeP,RBalloc,0,mbsfn_status);
schedule_ulsch(module_idP,frameP,cooperation_flag,1,5,nCCE);
}
break;
case 2:
// TDD, nothing
// FDD, normal UL/DLSCH
if (mac_xface->lte_frame_parms->frame_type == FDD) { //FDD
schedule_ue_spec(module_idP,frameP,subframeP,nprb,nCCE,mbsfn_status);
fill_DLSCH_dci(module_idP,frameP,subframeP,RBalloc,0,mbsfn_status);
schedule_ulsch(module_idP,frameP,cooperation_flag,2,6,nCCE);
}
break;
case 3:
// TDD Config 2, ULSCH for subframeP 7
// TDD Config 2/5 normal DLSCH
// FDD, normal UL/DLSCH
if (mac_xface->lte_frame_parms->frame_type == TDD) {
switch (mac_xface->lte_frame_parms->tdd_config) {
case 2:
schedule_ulsch(module_idP,frameP,cooperation_flag,subframeP,7,nCCE);
// no break here!
case 5:
schedule_ue_spec(module_idP,frameP,subframeP,nprb,nCCE,mbsfn_status);
fill_DLSCH_dci(module_idP,frameP,subframeP,RBalloc,0,mbsfn_status);
break;
default:
break;
}
} else { //FDD
schedule_ue_spec(module_idP,frameP,subframeP,nprb,nCCE,mbsfn_status);
fill_DLSCH_dci(module_idP,frameP,subframeP,RBalloc,0,mbsfn_status);
schedule_ulsch(module_idP,frameP,cooperation_flag,3,7,nCCE);
}
break;
case 4:
// TDD Config 1, ULSCH for subframeP 8
// TDD Config 1/2/4/5 DLSCH
// FDD UL/DLSCH
if (mac_xface->lte_frame_parms->frame_type == 1) { // TDD
switch (mac_xface->lte_frame_parms->tdd_config) {
case 1:
// schedule_RA(module_idP,frameP,subframeP,nprb,nCCE);
schedule_ulsch(module_idP,frameP,cooperation_flag,subframeP,8,nCCE);
// no break here!
case 2:
// no break here!
case 4:
// no break here!
case 5:
schedule_ue_spec(module_idP,frameP,subframeP,nprb,nCCE,mbsfn_status);
fill_DLSCH_dci(module_idP,frameP,subframeP,RBalloc,1,mbsfn_status);
break;
default:
break;
}
} else {
if (mac_xface->lte_frame_parms->frame_type == FDD) { //FDD
// schedule_RA(module_idP,frameP, subframeP, 0, nprb, nCCE);
// schedule_ulsch(module_idP, frameP, cooperation_flag, 4, 8, nCCE);
schedule_ue_spec(module_idP, frameP, subframeP, nprb, nCCE, mbsfn_status);
fill_DLSCH_dci(module_idP, frameP, subframeP, RBalloc, 1, mbsfn_status);
}
}
break;
case 5:
// TDD/FDD Schedule SI
// TDD Config 0,6 ULSCH for subframes 9,3 resp.
// TDD normal DLSCH
// FDD normal UL/DLSCH
schedule_SI(module_idP,frameP,nprb,nCCE);
//schedule_RA(module_idP,frameP,subframeP,5,nprb,nCCE);
if (mac_xface->lte_frame_parms->frame_type == FDD) {
schedule_RA(module_idP,frameP,subframeP,1,nprb,nCCE);
// schedule_ulsch(module_idP,frameP,cooperation_flag,5,9,nCCE);
fill_DLSCH_dci(module_idP,frameP,subframeP,RBalloc,1,mbsfn_status);
} else if ((mac_xface->lte_frame_parms->tdd_config == 0) || // TDD Config 0
(mac_xface->lte_frame_parms->tdd_config == 6)) { // TDD Config 6
//schedule_ulsch(module_idP,cooperation_flag,subframeP,nCCE);
fill_DLSCH_dci(module_idP,frameP,subframeP,RBalloc,0,mbsfn_status);
} else {
//schedule_ue_spec(module_idP,frameP,subframeP,nprb,nCCE,mbsfn_status);
fill_DLSCH_dci(module_idP,frameP,subframeP,RBalloc,0,mbsfn_status);
}
break;
case 6:
// TDD Config 0,1,6 ULSCH for subframes 2,3
// TDD Config 3,4,5 Normal DLSCH
// FDD normal ULSCH/DLSCH
if (mac_xface->lte_frame_parms->frame_type == TDD) { // TDD
switch (mac_xface->lte_frame_parms->tdd_config) {
case 0:
break;
case 1:
schedule_ulsch(module_idP,frameP,cooperation_flag,subframeP,2,nCCE);
// schedule_ue_spec(module_idP,frameP,subframeP,nprb,nCCE,mbsfn_status);
fill_DLSCH_dci(module_idP,frameP,subframeP,RBalloc,0,mbsfn_status);
break;
case 6:
schedule_ulsch(module_idP,frameP,cooperation_flag,subframeP,3,nCCE);
// schedule_ue_spec(module_idP,frameP,subframeP,nprb,nCCE,mbsfn_status);
fill_DLSCH_dci(module_idP,frameP,subframeP,RBalloc,0,mbsfn_status);
break;
case 5:
schedule_RA(module_idP,frameP,subframeP,2,nprb,nCCE);
schedule_ue_spec(module_idP,frameP,subframeP,nprb,nCCE,mbsfn_status);
fill_DLSCH_dci(module_idP,frameP,subframeP,RBalloc,1,mbsfn_status);
break;
case 3:
case 4:
schedule_ue_spec(module_idP,frameP,subframeP,nprb,nCCE,mbsfn_status);
fill_DLSCH_dci(module_idP,frameP,subframeP,RBalloc,0,mbsfn_status);
break;
default:
break;
}
} else { //FDD
// schedule_ulsch(module_idP,frameP,cooperation_flag,6,0,nCCE);
schedule_ue_spec(module_idP,frameP,subframeP,nprb,nCCE,mbsfn_status);
fill_DLSCH_dci(module_idP,frameP,subframeP,RBalloc,0,mbsfn_status);
}
break;
case 7:
// TDD Config 3,4,5 Normal DLSCH
// FDD Normal UL/DLSCH
if (mac_xface->lte_frame_parms->frame_type == TDD) { // TDD
switch (mac_xface->lte_frame_parms->tdd_config) {
case 3:
case 4:
schedule_RA(module_idP,frameP,subframeP,3,nprb,nCCE); // 3 = Msg3 subframeP, not
schedule_ue_spec(module_idP,frameP,subframeP,nprb,nCCE,mbsfn_status);
fill_DLSCH_dci(module_idP,frameP,subframeP,RBalloc,1,mbsfn_status);
break;
case 5:
schedule_ue_spec(module_idP,frameP,subframeP,nprb,nCCE,mbsfn_status);
fill_DLSCH_dci(module_idP,frameP,subframeP,RBalloc,0,mbsfn_status);
break;
default:
break;
}
} else { //FDD
//schedule_ulsch(module_idP,frameP,cooperation_flag,7,1,nCCE);
schedule_ue_spec(module_idP,frameP,subframeP,nprb,nCCE,mbsfn_status);
fill_DLSCH_dci(module_idP,frameP,subframeP,RBalloc,0,mbsfn_status);
}
break;
case 8:
// TDD Config 2,3,4,5 ULSCH for subframeP 2
//
// FDD Normal UL/DLSCH
if (mac_xface->lte_frame_parms->frame_type == TDD) { // TDD
switch (mac_xface->lte_frame_parms->tdd_config) {
case 2:
case 3:
case 4:
case 5:
// schedule_RA(module_idP,subframeP,nprb,nCCE);
schedule_ulsch(module_idP,frameP,cooperation_flag,subframeP,2,nCCE);
schedule_ue_spec(module_idP,frameP,subframeP,nprb,nCCE,mbsfn_status);
fill_DLSCH_dci(module_idP,frameP,subframeP,RBalloc,0,mbsfn_status);
break;
default:
break;
}
} else { //FDD
//schedule_ulsch(module_idP,frameP,cooperation_flag,8,2,nCCE);
schedule_ue_spec(module_idP,frameP,subframeP,nprb,nCCE,mbsfn_status);
fill_DLSCH_dci(module_idP,frameP,subframeP,RBalloc,0,mbsfn_status);
}
break;
case 9:
// TDD Config 1,3,4,6 ULSCH for subframes 3,3,3,4
if (mac_xface->lte_frame_parms->frame_type == TDD) {
switch (mac_xface->lte_frame_parms->tdd_config) {
case 1:
schedule_ulsch(module_idP,frameP,cooperation_flag,subframeP,3,nCCE);
schedule_RA(module_idP,frameP,subframeP,7,nprb,nCCE); // 7 = Msg3 subframeP, not
schedule_ue_spec(module_idP,frameP,subframeP,nprb,nCCE,mbsfn_status);
fill_DLSCH_dci(module_idP,frameP,subframeP,RBalloc,1,mbsfn_status);
break;
case 3:
case 4:
schedule_ulsch(module_idP,frameP,cooperation_flag,subframeP,3,nCCE);
schedule_ue_spec(module_idP,frameP,subframeP,nprb,nCCE,mbsfn_status);
fill_DLSCH_dci(module_idP,frameP,subframeP,RBalloc,0,mbsfn_status);
break;
case 6:
schedule_ulsch(module_idP,frameP,cooperation_flag,subframeP,4,nCCE);
//schedule_RA(module_idP,frameP,subframeP,nprb,nCCE);
schedule_ue_spec(module_idP,frameP,subframeP,nprb,nCCE,mbsfn_status);
fill_DLSCH_dci(module_idP,frameP,subframeP,RBalloc,0,mbsfn_status);
break;
case 2:
case 5:
//schedule_RA(module_idP,frameP,subframeP,nprb,nCCE);
schedule_ue_spec(module_idP,frameP,subframeP,nprb,nCCE,mbsfn_status);
fill_DLSCH_dci(module_idP,frameP,subframeP,RBalloc,0,mbsfn_status);
break;
default:
break;
}
} else { //FDD
// schedule_ulsch(module_idP,frameP,cooperation_flag,9,3,nCCE);
schedule_ue_spec(module_idP,frameP,subframeP,nprb,nCCE,mbsfn_status);
fill_DLSCH_dci(module_idP,frameP,subframeP,RBalloc,0,mbsfn_status);
}
break;
}
for (CC_id=0; CC_id<MAX_NUM_CCs; CC_id++) {
DCI_pdu[CC_id]->nCCE = nCCE[CC_id];
}
LOG_D(MAC,"frameP %d, subframeP %d nCCE %d\n",frameP,subframeP,nCCE[0]);
stop_meas(&eNB_mac_inst[module_idP].eNB_scheduler);
VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_ENB_DLSCH_ULSCH_SCHEDULER,VCD_FUNCTION_OUT);
}