int main(void) { UQueue *queue = queue_new(); if (!queue_push(queue, UINT_TO_POINTER(1))) abort(); if (!queue_push(queue, UINT_TO_POINTER(2))) abort(); if (queue_is_empty(queue)) abort(); if (POINTER_TO_UINT(queue_pop(queue)) != 1) abort(); if (POINTER_TO_UINT(queue_pop(queue)) != 2) abort(); if (!queue_is_empty(queue)) abort(); if (!queue_push(queue, UINT_TO_POINTER(3))) abort(); if (POINTER_TO_UINT(queue_pop(queue)) != 3) abort(); queue_free(queue); }
/* * Process successfully sent packets */ static void tx_completed(Gmac *gmac, struct gmac_queue *queue) { struct gmac_desc_list *tx_desc_list = &queue->tx_desc_list; struct gmac_desc *tx_desc; struct net_pkt *pkt; __ASSERT(tx_desc_list->buf[tx_desc_list->tail].w1 & GMAC_TXW1_USED, "first buffer of a frame is not marked as own by GMAC"); while (tx_desc_list->tail != tx_desc_list->head) { tx_desc = &tx_desc_list->buf[tx_desc_list->tail]; MODULO_INC(tx_desc_list->tail, tx_desc_list->len); k_sem_give(&queue->tx_desc_sem); if (tx_desc->w1 & GMAC_TXW1_LASTBUFFER) { /* Release net buffer to the buffer pool */ pkt = UINT_TO_POINTER(ring_buf_get(&queue->tx_frames)); net_pkt_unref(pkt); SYS_LOG_DBG("Dropping pkt %p", pkt); break; } } }
/* * Reset TX queue when errors are detected */ static void tx_error_handler(Gmac *gmac, struct gmac_queue *queue) { struct net_pkt *pkt; struct ring_buf *tx_frames = &queue->tx_frames; queue->err_tx_flushed_count++; /* Stop transmission, clean transmit pipeline and control registers */ gmac->GMAC_NCR &= ~GMAC_NCR_TXEN; /* Free all pkt resources in the TX path */ while (tx_frames->tail != tx_frames->head) { /* Release net buffer to the buffer pool */ pkt = UINT_TO_POINTER(tx_frames->buf[tx_frames->tail]); net_pkt_unref(pkt); SYS_LOG_DBG("Dropping pkt %p", pkt); MODULO_INC(tx_frames->tail, tx_frames->len); } /* Reinitialize TX descriptor list */ k_sem_reset(&queue->tx_desc_sem); tx_descriptors_init(gmac, queue); for (int i = 0; i < queue->tx_desc_list.len - 1; i++) { k_sem_give(&queue->tx_desc_sem); } /* Restart transmission */ gmac->GMAC_NCR |= GMAC_NCR_TXEN; }
static void send_tcp_data(struct net_app_ctx *ctx, struct data *data) { struct net_pkt *pkt; size_t len; int ret; do { data->expecting_tcp = sys_rand32_get() % ipsum_len; } while (data->expecting_tcp == 0); data->received_tcp = 0; pkt = prepare_send_pkt(ctx, data->proto, data->expecting_tcp); if (!pkt) { return; } len = net_pkt_get_len(pkt); NET_ASSERT_INFO(data->expecting_tcp == len, "%s data to send %d bytes, real len %zu", data->proto, data->expecting_tcp, len); ret = net_app_send_pkt(ctx, pkt, NULL, 0, K_FOREVER, UINT_TO_POINTER(len)); if (ret < 0) { NET_ERR("Cannot send %s data to peer (%d)", data->proto, ret); net_pkt_unref(pkt); } }
clock_control_subsys_t stm32_get_port_clock(int port) { const clock_control_subsys_t ports_to_clock[STM32_PORTS_MAX] = { UINT_TO_POINTER(STM32F10X_CLOCK_SUBSYS_IOPA), UINT_TO_POINTER(STM32F10X_CLOCK_SUBSYS_IOPB), UINT_TO_POINTER(STM32F10X_CLOCK_SUBSYS_IOPC), UINT_TO_POINTER(STM32F10X_CLOCK_SUBSYS_IOPD), UINT_TO_POINTER(STM32F10X_CLOCK_SUBSYS_IOPE), }; if (port > STM32_PORTE) { return NULL; } return ports_to_clock[port]; }
static void tcp_received(struct net_context *context, struct net_pkt *pkt, int status, void *user_data) { static char dbg[MAX_DBG_PRINT + 1]; sa_family_t family = net_pkt_family(pkt); struct net_pkt *reply_pkt; int ret; snprintf(dbg, MAX_DBG_PRINT, "TCP IPv%c", family == AF_INET6 ? '6' : '4'); reply_pkt = build_reply_pkt(dbg, context, pkt); net_pkt_unref(pkt); ret = net_context_send(reply_pkt, pkt_sent, K_NO_WAIT, UINT_TO_POINTER(net_pkt_get_len(reply_pkt)), NULL); if (ret < 0) { printk("Cannot send data to peer (%d)", ret); net_pkt_unref(reply_pkt); quit(); } }
static void udp_received(struct net_context *context, struct net_pkt *pkt, int status, void *user_data) { struct net_pkt *reply_pkt; struct sockaddr dst_addr; sa_family_t family = net_pkt_family(pkt); static char dbg[MAX_DBG_PRINT + 1]; int ret; snprintf(dbg, MAX_DBG_PRINT, "UDP IPv%c", family == AF_INET6 ? '6' : '4'); set_dst_addr(family, pkt, &dst_addr); reply_pkt = build_reply_pkt(dbg, context, pkt); net_pkt_unref(pkt); ret = net_context_sendto(reply_pkt, &dst_addr, family == AF_INET6 ? sizeof(struct sockaddr_in6) : sizeof(struct sockaddr_in), pkt_sent, 0, UINT_TO_POINTER(net_pkt_get_len(reply_pkt)), user_data); if (ret < 0) { printk("Cannot send data to peer (%d)", ret); net_pkt_unref(reply_pkt); } }
static int register_fd(void *x, int *fd, const char *path) { char full[_MAX_PATH]; if (NULL == _fullpath(full, path, _MAX_PATH)) { return 0; } else { char *copy = mem_dup(full); *fd = --FD_FROM_P(x); hashtable_put(HT_FROM_P(x), UINT_TO_POINTER(*fd), copy); return 1; } }
bool sctpEventManager::createEvent(sc_memory_context *ctx, sc_event_type type, sc_addr addr, sctpCommand *cmd, tEventId &event) { QMutexLocker locker(&mEventsMutex); if (!_getAvailableEventId(event)) return false; sEventData *evt = new sEventData(); evt->cmd = cmd; evt->id = event; evt->event = sc_event_new(ctx, addr, type, UINT_TO_POINTER(event), &sctpEventManager::_eventsCallback, 0); Q_ASSERT(mEvents.find(evt->id) == mEvents.end()); mEvents[evt->id] = evt; return true; }
int win32_fstat(void *x, int fd, struct stat *buffer) { if (fd == -1) { errno = EBADF; return -1; } else if (fd >= 0) { return fstat(fd, buffer); } else { void *ptr; if (hashtable_get(HT_FROM_P(x), UINT_TO_POINTER(fd), &ptr)) { if (NULL == ptr) { errno = EBADF; return -1; } else { return stat(ptr, buffer); } } else { errno = EBADF; return -1; } } }
SYS_LOG_DBG("Designware SPI driver initialized on device: %p", dev); return 0; } #ifdef CONFIG_SPI_0 void spi_config_0_irq(void); struct spi_dw_data spi_dw_data_port_0; const struct spi_dw_config spi_dw_config_0 = { .regs = SPI_DW_PORT_0_REGS, #ifdef CONFIG_SPI_DW_CLOCK_GATE .clock_data = UINT_TO_POINTER(CONFIG_SPI_0_CLOCK_GATE_SUBSYS), #endif /* CONFIG_SPI_DW_CLOCK_GATE */ #ifdef CONFIG_SPI_DW_CS_GPIO .cs_gpio_name = CONFIG_SPI_0_CS_GPIO_PORT, .cs_gpio_pin = CONFIG_SPI_0_CS_GPIO_PIN, #endif .config_func = spi_config_0_irq }; DEVICE_AND_API_INIT(spi_dw_port_0, CONFIG_SPI_0_NAME, spi_dw_init, &spi_dw_data_port_0, &spi_dw_config_0, POST_KERNEL, CONFIG_SPI_INIT_PRIORITY, &dw_spi_api); void spi_config_0_irq(void) {
#ifdef CONFIG_UART_STM32_PORT_1 #ifdef CONFIG_UART_INTERRUPT_DRIVEN static void uart_stm32_irq_config_func_1(struct device *dev); #endif /* CONFIG_UART_INTERRUPT_DRIVEN */ static const struct uart_stm32_config uart_stm32_dev_cfg_1 = { .uconf = { .base = (uint8_t *)USART1_BASE, #ifdef CONFIG_UART_INTERRUPT_DRIVEN .irq_config_func = uart_stm32_irq_config_func_1, #endif /* CONFIG_UART_INTERRUPT_DRIVEN */ }, #ifdef CONFIG_SOC_SERIES_STM32F1X .clock_subsys = UINT_TO_POINTER(STM32F10X_CLOCK_SUBSYS_USART1), #elif CONFIG_SOC_SERIES_STM32F4X .pclken = { .bus = STM32F4X_CLOCK_BUS_APB2, .enr = STM32F4X_CLOCK_ENABLE_USART1 }, #elif CONFIG_SOC_SERIES_STM32L4X .clock_subsys = UINT_TO_POINTER(STM32L4X_CLOCK_SUBSYS_USART1), #endif /* CONFIG_SOC_SERIES_STM32FX */ }; static struct uart_stm32_data uart_stm32_dev_data_1 = { .huart = { .Init = { .BaudRate = CONFIG_UART_STM32_PORT_1_BAUD_RATE} } }; DEVICE_AND_API_INIT(uart_stm32_1, CONFIG_UART_STM32_PORT_1_NAME,
static void unregister_fd(void *x, int fd) { hashtable_remove(HT_FROM_P(x), UINT_TO_POINTER(fd)); }
} #ifdef CONFIG_SPI_0 void spi_config_0_irq(void); struct spi_dw_data spi_dw_data_port_0 = { SPI_CONTEXT_INIT_LOCK(spi_dw_data_port_0, ctx), SPI_CONTEXT_INIT_SYNC(spi_dw_data_port_0, ctx), }; const struct spi_dw_config spi_dw_config_0 = { .regs = DT_SPI_0_BASE_ADDRESS, #ifdef CONFIG_SPI_DW_PORT_0_CLOCK_GATE .clock_name = CONFIG_SPI_DW_PORT_1_CLOCK_GATE_DRV_NAME, .clock_data = UINT_TO_POINTER(CONFIG_SPI_DW_PORT_0_CLOCK_GATE_SUBSYS), #endif /* CONFIG_SPI_DW_PORT_0_CLOCK_GATE */ .config_func = spi_config_0_irq, .op_modes = CONFIG_SPI_0_OP_MODES }; DEVICE_AND_API_INIT(spi_dw_port_0, DT_SPI_0_NAME, spi_dw_init, &spi_dw_data_port_0, &spi_dw_config_0, POST_KERNEL, CONFIG_SPI_INIT_PRIORITY, &dw_spi_api); void spi_config_0_irq(void) { #ifdef CONFIG_SPI_DW_PORT_0_INTERRUPT_SINGLE_LINE IRQ_CONNECT(DT_SPI_0_IRQ, DT_SPI_0_IRQ_PRI, spi_dw_isr, DEVICE_GET(spi_dw_port_0), DT_SPI_DW_IRQ_FLAGS);
#if CONFIG_PCI .pci_dev.class_type = GPIO_DW_PCI_CLASS, .pci_dev.bus = GPIO_DW_0_PCI_BUS, .pci_dev.dev = GPIO_DW_0_PCI_DEV, .pci_dev.vendor_id = GPIO_DW_PCI_VENDOR_ID, .pci_dev.device_id = GPIO_DW_PCI_DEVICE_ID, .pci_dev.function = GPIO_DW_0_PCI_FUNCTION, .pci_dev.bar = GPIO_DW_0_PCI_BAR, #endif .config_func = gpio_config_0_irq, #ifdef CONFIG_GPIO_DW_0_IRQ_SHARED .shared_irq_dev_name = CONFIG_GPIO_DW_0_IRQ_SHARED_NAME, #endif #ifdef CONFIG_GPIO_DW_CLOCK_GATE .clock_data = UINT_TO_POINTER(CONFIG_GPIO_DW_0_CLOCK_GATE_SUBSYS), #endif }; struct gpio_dw_runtime gpio_0_runtime; #ifdef CONFIG_DEVICE_POWER_MANAGEMENT struct device_pm_ops gpio_dev_pm_ops = { .suspend = gpio_dw_suspend_port, .resume = gpio_dw_resume_port }; DEVICE_INIT_PM(gpio_dw_0, CONFIG_GPIO_DW_0_NAME, gpio_dw_initialize, &gpio_dev_pm_ops, &gpio_0_runtime, &gpio_config_0, SECONDARY, CONFIG_GPIO_DW_INIT_PRIORITY); #else