/** * This function will initialize susb host controller device. * * @param dev the host controller device to be initalize. * * @return the error code, RT_EOK on successfully. */ static rt_err_t susb_init(rt_device_t dev) { rt_sem_init(&sem_lock, "s_lock", 1, RT_IPC_FLAG_FIFO); /* roothub initilizition */ root_hub.num_ports = 1; root_hub.is_roothub = RT_TRUE; root_hub.self = RT_NULL; root_hub.hcd = &susb_hcd; /* Hardware Init */ USB_OTG_BSP_Init(&USB_OTG_Core); /* configure GPIO pin used for switching VBUS power */ USB_OTG_BSP_ConfigVBUS(0); /* Host de-initializations */ USBH_DeInit(&USB_OTG_Core, &USB_Host); /* Start the USB OTG core */ HCD_Init(&USB_OTG_Core , USB_OTG_FS_CORE_ID); USBH_DeAllocate_AllChannel(&USB_OTG_Core); /* Enable Interrupts */ USB_OTG_BSP_EnableInterrupt(&USB_OTG_Core); return RT_EOK; }
/** * @brief USBH_Init * Host hardware and stack initializations * @param class_cb: Class callback structure address * @param usr_cb: User callback structure address * @retval None */ void USBH_Init(USB_OTG_CORE_HANDLE *pdev, USB_OTG_CORE_ID_TypeDef coreID, USBH_HOST *phost, USBH_Class_cb_TypeDef *class_cb, USBH_Usr_cb_TypeDef *usr_cb) { /* Hardware Init */ USB_OTG_BSP_Init(pdev); /* configure GPIO pin used for switching VBUS power */ USB_OTG_BSP_ConfigVBUS(0); /* Host de-initializations */ USBH_DeInit(pdev, phost); /*Register class and user callbacks */ phost->class_cb = class_cb; phost->usr_cb = usr_cb; /* Start the USB OTG core */ HCD_Init(pdev , coreID); /* Upon Init call usr call back */ phost->usr_cb->Init(); /* Enable Interrupts */ USB_OTG_BSP_EnableInterrupt(pdev); }
//-------------------------------------------------------------- USB_OTG_STS USB_OTG_CoreInitHost(USB_OTG_CORE_HANDLE *pdev) { USB_OTG_STS status = USB_OTG_OK; USB_OTG_FSIZ_TypeDef nptxfifosize; USB_OTG_FSIZ_TypeDef ptxfifosize; USB_OTG_HCFG_TypeDef hcfg; uint32_t i = 0; nptxfifosize.d32 = 0; ptxfifosize.d32 = 0; hcfg.d32 = 0; /* configure charge pump IO */ USB_OTG_BSP_ConfigVBUS(pdev); /* Restart the Phy Clock */ USB_OTG_WRITE_REG32(pdev->regs.PCGCCTL, 0); /* Initialize Host Configuration Register */ if (pdev->cfg.phy_itface == USB_OTG_ULPI_PHY) { USB_OTG_InitFSLSPClkSel(pdev , HCFG_30_60_MHZ); } else { USB_OTG_InitFSLSPClkSel(pdev , HCFG_48_MHZ); } USB_OTG_ResetPort(pdev); hcfg.d32 = USB_OTG_READ_REG32(&pdev->regs.HREGS->HCFG); hcfg.b.fslssupp = 0; USB_OTG_WRITE_REG32(&pdev->regs.HREGS->HCFG, hcfg.d32); /* Configure data FIFO sizes */ /* Rx FIFO */ if (pdev->cfg.coreID == USB_OTG_HS_CORE_ID) { /* set Rx FIFO size */ USB_OTG_WRITE_REG32(&pdev->regs.GREGS->GRXFSIZ, RX_FIFO_HS_SIZE); nptxfifosize.b.startaddr = RX_FIFO_HS_SIZE; nptxfifosize.b.depth = TXH_NP_HS_FIFOSIZ; USB_OTG_WRITE_REG32(&pdev->regs.GREGS->DIEPTXF0_HNPTXFSIZ, nptxfifosize.d32); ptxfifosize.b.startaddr = RX_FIFO_HS_SIZE + TXH_NP_HS_FIFOSIZ; ptxfifosize.b.depth = TXH_P_HS_FIFOSIZ; USB_OTG_WRITE_REG32(&pdev->regs.GREGS->HPTXFSIZ, ptxfifosize.d32); } /* Make sure the FIFOs are flushed. */ USB_OTG_FlushTxFifo(pdev, 0x10 ); /* all Tx FIFOs */ USB_OTG_FlushRxFifo(pdev); /* Clear all pending HC Interrupts */ for (i = 0; i < pdev->cfg.host_channels; i++) { USB_OTG_WRITE_REG32( &pdev->regs.HC_REGS[i]->HCINT, 0xFFFFFFFF ); USB_OTG_WRITE_REG32( &pdev->regs.HC_REGS[i]->HCINTMSK, 0 ); } USB_OTG_DriveVbus(pdev, 1); USB_OTG_EnableHostInt(pdev); return status; }