//-------------------------------------------------------------- void USB_OTG_SetEPStatus(USB_OTG_CORE_HANDLE * pdev, USB_OTG_EP * ep, uint32_t Status) { USB_OTG_DEPCTL_TypeDef depctl; __IO uint32_t *depctl_addr; depctl.d32 = 0; /* Process for IN endpoint */ if (ep->is_in == 1) { depctl_addr = &(pdev->regs.INEP_REGS[ep->num]->DIEPCTL); depctl.d32 = USB_OTG_READ_REG32(depctl_addr); if (Status == USB_OTG_EP_TX_STALL) { USB_OTG_EPSetStall(pdev, ep); return; } else if (Status == USB_OTG_EP_TX_NAK) depctl.b.snak = 1; else if (Status == USB_OTG_EP_TX_VALID) { if (depctl.b.stall == 1) { ep->even_odd_frame = 0; USB_OTG_EPClearStall(pdev, ep); return; } depctl.b.cnak = 1; depctl.b.usbactep = 1; depctl.b.epena = 1; } else if (Status == USB_OTG_EP_TX_DIS) depctl.b.usbactep = 0; } else { /* Process for OUT endpoint */ depctl_addr = &(pdev->regs.OUTEP_REGS[ep->num]->DOEPCTL); depctl.d32 = USB_OTG_READ_REG32(depctl_addr); if (Status == USB_OTG_EP_RX_STALL) { depctl.b.stall = 1; } else if (Status == USB_OTG_EP_RX_NAK) depctl.b.snak = 1; else if (Status == USB_OTG_EP_RX_VALID) { if (depctl.b.stall == 1) { ep->even_odd_frame = 0; USB_OTG_EPClearStall(pdev, ep); return; } depctl.b.cnak = 1; depctl.b.usbactep = 1; depctl.b.epena = 1; } else if (Status == USB_OTG_EP_RX_DIS) { depctl.b.usbactep = 0; } } USB_OTG_WRITE_REG32(depctl_addr, depctl.d32); }
/** * @brief Clear stall condition on endpoints. * @param pdev: device instance * @param epnum: endpoint address * @retval : status */ uint32_t DCD_EP_ClrStall (USB_OTG_CORE_HANDLE *pdev, uint8_t epnum) { USB_OTG_EP *ep; if ((0x80 & epnum) == 0x80) { ep = &pdev->dev.in_ep[epnum & 0x7F]; } else { ep = &pdev->dev.out_ep[epnum]; } ep->is_stall = 0; ep->num = epnum & 0x7F; ep->is_in = ((epnum & 0x80) == 0x80); USB_OTG_EPClearStall(pdev , ep); return (0); }