int main()
{
int Status;
#ifdef XPAR_UARTNS550_0_BASEADDR
Uart550_Setup();
#endif
xil_printf("\r\n--- Entering main() --- \r\n");
/* Run the interrupt example for simple transfer
*/
Status = XAxiCdma_SgPollExample(DMA_CTRL_DEVICE_ID);
if (Status != XST_SUCCESS) {
xil_printf("XAxiCdma_SgPollExample: Failed\r\n");
return XST_FAILURE;
}
xil_printf("XAxiCdma_SgPollExample: Passed\r\n");
xil_printf("--- Exiting main() --- \r\n");
return XST_SUCCESS;
}
/**
*
* Main function
*
* This function is the main entry of the tests on DMA core. It sets up
* DMA engine to be ready to receive and send packets, then a packet is
* transmitted and will be verified after it is received via the loopback on the
* Local Link interface of the DMA.
*
* @return 0 if tests pass, 1 otherwise.
*
* @note None.
*
******************************************************************************/
int main(void)
{
int Status;
XAxiDma_Config *Config;
#if defined(XPAR_UARTNS550_0_BASEADDR)
Uart550_Setup();
#endif
xil_printf("\r\n--- Entering main() --- \r\n");
Config = XAxiDma_LookupConfig(DMA_DEV_ID);
if (!Config) {
xdbg_printf(XDBG_DEBUG_ERROR,
"No config found for %d\r\n", DMA_DEV_ID);
return 1;
}
/* Initialize DMA engine */
Status = XAxiDma_CfgInitialize(&AxiDma, Config);
if (Status != XST_SUCCESS) {
xil_printf("Initialization failed %d\r\n", Status);
return 1;
}
Status = TxSetup(&AxiDma);
if (Status != XST_SUCCESS) {
return 1;
}
Status = RxSetup(&AxiDma);
if (Status != XST_SUCCESS) {
return 1;
}
/* Send a packet */
Status = SendPacket(&AxiDma);
if (Status != XST_SUCCESS) {
return 1;
}
/* Check DMA transfer result */
Status = CheckDmaResult(&AxiDma);
xil_printf("Test %s\r\n",
(Status == XST_SUCCESS)? "passed":"failed");
xil_printf("--- Exiting main() --- \r\n");
if (Status != XST_SUCCESS) {
return XST_FAILURE;
}
return 0;
}
int main(void)
{
int Status;
#ifdef XPAR_UARTNS550_0_BASEADDR
Uart550_Setup();
#endif
xil_printf("\r\n--- Entering main() --- \r\n");
/* Run the interrupt example for simple transfer
*/
Status = XAxiCdma_HybridIntrExample(&IntcController, &Engine,
DMA_CTRL_DEVICE_ID, DMA_CTRL_IRPT_INTR);
xil_printf("Test status: %s\r\n",
(Status == XST_SUCCESS)? "passed":"failed");
xil_printf("--- Exiting main() --- \r\n");
return XST_SUCCESS;
}
/**
*
* Main function
*
* This function is the main entry of the interrupt test. It does the following:
* - Set up the output terminal if UART16550 is in the hardware build
* - Initialize the DMA engine
* - Set up Tx and Rx channels
* - Set up the interrupt system for the Tx and Rx interrupts
* - Submit a transfer
* - Wait for the transfer to finish
* - Check transfer status
* - Disable Tx and Rx interrupts
* - Print test status and exit
*
* @param None
*
* @return - XST_SUCCESS if tests pass
* - XST_FAILURE if fails.
*
* @note None.
*
******************************************************************************/
int main(void)
{
int Status;
XAxiDma_Config *Config;
/* Initial setup for Uart16550 */
#ifdef XPAR_UARTNS550_0_BASEADDR
Uart550_Setup();
#endif
xil_printf("\r\n--- Entering main() --- \r\n");
Config = XAxiDma_LookupConfig(DMA_DEV_ID);
if (!Config) {
xil_printf("No config found for %d\r\n", DMA_DEV_ID);
return XST_FAILURE;
}
/* Initialize DMA engine */
XAxiDma_CfgInitialize(&AxiDma, Config);
if(!XAxiDma_HasSg(&AxiDma)) {
xil_printf("Device configured as Simple mode \r\n");
return XST_FAILURE;
}
/* Set up TX/RX channels to be ready to transmit and receive packets */
Status = TxSetup(&AxiDma);
if (Status != XST_SUCCESS) {
xil_printf("Failed TX setup\r\n");
return XST_FAILURE;
}
Status = RxSetup(&AxiDma);
if (Status != XST_SUCCESS) {
xil_printf("Failed RX setup\r\n");
return XST_FAILURE;
}
/* Set up Interrupt system */
Status = SetupIntrSystem(&Intc, &AxiDma, TX_INTR_ID,
RX_INTR_ID, 1);
if (Status != XST_SUCCESS) {
xil_printf("Failed intr setup\r\n");
return XST_FAILURE;
}
/* Initialize flags before start transfer test */
TxDone = 0;
RxDone = 0;
Error = 0;
/* Send a packet */
Status = SendPacket(&AxiDma, TDEST0, TID0, PACKET0_DATA);
if (Status != XST_SUCCESS) {
xil_printf("Failed send packet\r\n");
return XST_FAILURE;
}
/*
* Wait TX done and RX done
*/
while (((TxDone < NUMBER_OF_BDS_TO_TRANSFER) ||
(RxDone < NUMBER_OF_BDS_TO_TRANSFER)) && !Error) {
/* NOP */
}
if (Error) {
xil_printf("Failed test transmit%s done, "
"receive%s done\r\n", TxDone? "":" not",
RxDone? "":" not");
goto Done;
}else {
/*
* Test finished, check data
*/
Status = CheckData(MAX_PKT_LEN * NUMBER_OF_BDS_TO_TRANSFER,
RxPacket1, PACKET0_DATA);
if (Status != XST_SUCCESS) {
xil_printf("Data check failed\r\n");
goto Done;
}
}
xil_printf("Sent Packet with Tdest 0 Successfully\n\r");
/* Initialize flags before start transfer test */
TxDone = 0;
RxDone = 0;
Error = 0;
/* Send a packet */
Status = SendPacket(&AxiDma, TDEST1, TID1, PACKET1_DATA);
if (Status != XST_SUCCESS) {
xil_printf("Failed send packet\r\n");
return XST_FAILURE;
}
/*
* Wait TX done and RX done
*/
while (((TxDone < NUMBER_OF_BDS_TO_TRANSFER) ||
(RxDone < NUMBER_OF_BDS_TO_TRANSFER)) && !Error) {
/* NOP */
}
if (Error) {
xil_printf("Failed test transmit%s done, "
"receive%s done\r\n", TxDone? "":" not",
RxDone? "":" not");
goto Done;
}else {
/*
* Test finished, check data
*/
Status = CheckData(MAX_PKT_LEN * NUMBER_OF_BDS_TO_TRANSFER,
RxPacket0, PACKET1_DATA);
if (Status != XST_SUCCESS) {
xil_printf("Data check failed\r\n");
goto Done;
}
}
/* Disable TX and RX Ring interrupts and return success */
DisableIntrSystem(&Intc, TX_INTR_ID, RX_INTR_ID);
xil_printf("Sent Packet with Tdest 1 Successfully\n\r");
xil_printf("AXI DMA SG interrupt Test passed\r\n");
Done:
xil_printf("--- Exiting main() --- \r\n");
if (Status != XST_SUCCESS) {
return XST_FAILURE;
}
return XST_SUCCESS;
}
/**
*
* Main function
*
* This function is the main entry of the interrupt test. It does the following:
* Set up the output terminal if UART16550 is in the hardware build
* Initialize the DMA engine
* Set up Tx and Rx channels
* Set up the interrupt system for the Tx and Rx interrupts
* Submit a transfer
* Wait for the transfer to finish
* Check transfer status
* Disable Tx and Rx interrupts
* Print test status and exit
*
* @param None
*
* @return
* - XST_SUCCESS if example finishes successfully
* - XST_FAILURE if example fails.
*
* @note None.
*
******************************************************************************/
int main(void)
{
int Status;
XAxiDma_Config *Config;
int Tries = NUMBER_OF_TRANSFERS;
int Index;
u8 *TxBufferPtr;
u8 *RxBufferPtr;
u8 Value;
TxBufferPtr = (u8 *)TX_BUFFER_BASE ;
RxBufferPtr = (u8 *)RX_BUFFER_BASE;
/* Initial setup for Uart16550 */
#ifdef XPAR_UARTNS550_0_BASEADDR
Uart550_Setup();
#endif
xil_printf("\r\n--- Entering main() --- \r\n");
Config = XAxiDma_LookupConfig(DMA_DEV_ID);
if (!Config) {
xil_printf("No config found for %d\r\n", DMA_DEV_ID);
return XST_FAILURE;
}
/* Initialize DMA engine */
Status = XAxiDma_CfgInitialize(&AxiDma, Config);
if (Status != XST_SUCCESS) {
xil_printf("Initialization failed %d\r\n", Status);
return XST_FAILURE;
}
if(XAxiDma_HasSg(&AxiDma)){
xil_printf("Device configured as SG mode \r\n");
return XST_FAILURE;
}
/* Set up Interrupt system */
Status = SetupIntrSystem(&Intc, &AxiDma, TX_INTR_ID, RX_INTR_ID);
if (Status != XST_SUCCESS) {
xil_printf("Failed intr setup\r\n");
return XST_FAILURE;
}
/* Disable all interrupts before setup */
XAxiDma_IntrDisable(&AxiDma, XAXIDMA_IRQ_ALL_MASK,
XAXIDMA_DMA_TO_DEVICE);
XAxiDma_IntrDisable(&AxiDma, XAXIDMA_IRQ_ALL_MASK,
XAXIDMA_DEVICE_TO_DMA);
/* Enable all interrupts */
XAxiDma_IntrEnable(&AxiDma, XAXIDMA_IRQ_ALL_MASK,
XAXIDMA_DMA_TO_DEVICE);
XAxiDma_IntrEnable(&AxiDma, XAXIDMA_IRQ_ALL_MASK,
XAXIDMA_DEVICE_TO_DMA);
/* Initialize flags before start transfer test */
TxDone = 0;
RxDone = 0;
Error = 0;
Value = TEST_START_VALUE;
for(Index = 0; Index < MAX_PKT_LEN; Index ++) {
TxBufferPtr[Index] = Value;
Value = (Value + 1) & 0xFF;
}
/* Flush the SrcBuffer before the DMA transfer, in case the Data Cache
* is enabled
*/
Xil_DCacheFlushRange((u32)TxBufferPtr, MAX_PKT_LEN);
#ifdef __aarch64__
Xil_DCacheFlushRange((UINTPTR)RxBufferPtr, MAX_PKT_LEN);
#endif
/* Send a packet */
for(Index = 0; Index < Tries; Index ++) {
Status = XAxiDma_SimpleTransfer(&AxiDma,(u32) RxBufferPtr,
MAX_PKT_LEN, XAXIDMA_DEVICE_TO_DMA);
if (Status != XST_SUCCESS) {
return XST_FAILURE;
}
Status = XAxiDma_SimpleTransfer(&AxiDma,(u32) TxBufferPtr,
MAX_PKT_LEN, XAXIDMA_DMA_TO_DEVICE);
if (Status != XST_SUCCESS) {
return XST_FAILURE;
}
/*
* Wait TX done and RX done
*/
while (!TxDone && !RxDone && !Error) {
/* NOP */
}
if (Error) {
xil_printf("Failed test transmit%s done, "
"receive%s done\r\n", TxDone? "":" not",
RxDone? "":" not");
goto Done;
}
/*
* Test finished, check data
*/
Status = CheckData(MAX_PKT_LEN, 0xC);
if (Status != XST_SUCCESS) {
xil_printf("Data check failed\r\n");
goto Done;
}
}
xil_printf("AXI DMA interrupt example test passed\r\n");
/* Disable TX and RX Ring interrupts and return success */
DisableIntrSystem(&Intc, TX_INTR_ID, RX_INTR_ID);
Done:
xil_printf("--- Exiting main() --- \r\n");
return XST_SUCCESS;
}
/**
*
* This function demonstrates the usage AXI FIFO
* It does the following:
* - Set up the output terminal if UART16550 is in the hardware build
* - Initialize the Axi FIFO Device.
* - Transmit the data
* - Receive the data from fifo
* - Compare the data
* - Return the result
*
* @param InstancePtr is a pointer to the instance of the
* XLlFifo component.
* @param DeviceId is Device ID of the Axi Fifo Deive instance,
* typically XPAR_<AXI_FIFO_instance>_DEVICE_ID value from
* xparameters.h.
*
* @return -XST_SUCCESS to indicate success
* -XST_FAILURE to indicate failure
*
******************************************************************************/
int XLlFifoPollingExample(XLlFifo *InstancePtr, u16 DeviceId)
{
XLlFifo_Config *Config;
int Status;
int i;
int Error;
Status = XST_SUCCESS;
/* Initial setup for Uart16550 */
#ifdef XPAR_UARTNS550_0_BASEADDR
Uart550_Setup();
#endif
/* Initialize the Device Configuration Interface driver */
Config = XLlFfio_LookupConfig(DeviceId);
if (!Config) {
xil_printf("No config found for %d\r\n", DeviceId);
return XST_FAILURE;
}
/*
* This is where the virtual address would be used, this example
* uses physical address.
*/
Status = XLlFifo_CfgInitialize(InstancePtr, Config, Config->BaseAddress);
if (Status != XST_SUCCESS) {
xil_printf("Initialization failed\n\r");
return Status;
}
/* Check for the Reset value */
Status = XLlFifo_Status(InstancePtr);
XLlFifo_IntClear(InstancePtr,0xffffffff);
Status = XLlFifo_Status(InstancePtr);
if(Status != 0x0) {
xil_printf("\n ERROR : Reset value of ISR0 : 0x%x\t"
"Expected : 0x0\n\r",
XLlFifo_Status(InstancePtr));
return XST_FAILURE;
}
/* Transmit the Data Stream */
Status = TxSend(InstancePtr, SourceBuffer);
if (Status != XST_SUCCESS){
xil_printf("Transmisson of Data failed\n\r");
return XST_FAILURE;
}
/* Revceive the Data Stream */
Status = RxReceive(InstancePtr, DestinationBuffer);
if (Status != XST_SUCCESS){
xil_printf("Receiving data failed");
return XST_FAILURE;
}
Error = 0;
/* Compare the data send with the data received */
xil_printf(" Comparing data ...\n\r");
for( i=0 ; i<MAX_DATA_BUFFER_SIZE ; i++ ){
if ( *(SourceBuffer + i) != *(DestinationBuffer + i) ){
Error = 1;
break;
}
}
if (Error != 0){
return XST_FAILURE;
}
return Status;
}
/**
*
* This function demonstrates the usage Traffic Generator
* It does the following:
* - Set up the output terminal if UART16550 is in the hardware build
* - Initialize the AXI Traffic Generator device
* - Initialize Master RAM
* - Initialize commands and add them to list
* - Program internal command and parameter RAMs
* - Start Master Logic
* - Wait for the master logic to finish
* - Check for errors
* - Read Master RAM and verify data
* - Return test status and exit
*
* @param InstancePtr is a pointer to the instance of the
* XTrafGen component.
* @param DeviceId is Device ID of the Axi Traffic Generator Device,
* typically XPAR_<TRAFGEN_instance>_DEVICE_ID value from
* xparameters.h.
*
* @return -XST_SUCCESS to indicate success
* -XST_FAILURE to indicate failure
*
******************************************************************************/
int XTrafGenInterruptExample(XTrafGen *InstancePtr, u16 DeviceId)
{
XTrafGen_Config *Config;
XTrafGen_Cmd Cmd;
XTrafGen_Cmd *CmdPtr = &Cmd;
u32 MasterRamIndex = 0;
int Status = XST_SUCCESS;
int Index;
/* Initial setup for Uart16550 */
#ifdef XPAR_UARTNS550_0_BASEADDR
Uart550_Setup();
#endif
/* Initialize the Device Configuration Interface driver */
Config = XTrafGen_LookupConfig(DeviceId);
if (!Config) {
xil_printf("No config found for %d\r\n", DeviceId);
return XST_FAILURE;
}
/*
* This is where the virtual address would be used, this example
* uses physical address.
*/
Status = XTrafGen_CfgInitialize(InstancePtr, Config, Config->BaseAddress);
if (Status != XST_SUCCESS) {
xil_printf("Initialization failed\n\r");
return Status;
}
/* Program Master RAM with Test Data */
XTrafGen_AccessMasterRam(InstancePtr, MasterRamIndex,
sizeof(MasterRamData), XTG_WRITE, MasterRamData);
/* Initialize default command fields */
InitDefaultCommands(CmdPtr);
/* Add Valid Command for Write Region */
CmdPtr->CRamCmd.Address = AXI_ADDRESS;
CmdPtr->CRamCmd.MasterRamIndex = 0x0;
CmdPtr->CRamCmd.Length = TEST_LENGTH - 1;
CmdPtr->RdWrFlag = XTG_WRITE;
CmdPtr->CRamCmd.ValidCmd = 1;
CmdPtr->CRamCmd.MyDepend = 0;
CmdPtr->CRamCmd.OtherDepend = XTrafGen_GetLastValidIndex(InstancePtr,
XTG_WRITE) + 1;
Status = XTrafGen_AddCommand(InstancePtr, CmdPtr);
if (Status != XST_SUCCESS) {
xil_printf("AddCommand() failed\n\r");
return Status;
}
/* Add Valid Command for Read Region */
CmdPtr->CRamCmd.Address = AXI_ADDRESS;
CmdPtr->CRamCmd.MasterRamIndex = MSTRRAM_INDEX;
CmdPtr->CRamCmd.Length = 7;
CmdPtr->CRamCmd.Size = 0x2;
CmdPtr->RdWrFlag = XTG_READ;
CmdPtr->CRamCmd.ValidCmd = 1;
CmdPtr->CRamCmd.MyDepend = 0;
/* Make this command dependent on Write logic command 1 */
CmdPtr->CRamCmd.OtherDepend = XTrafGen_GetLastValidIndex(InstancePtr,
XTG_WRITE) + 1;
Status = XTrafGen_AddCommand(InstancePtr, CmdPtr);
if (Status != XST_SUCCESS) {
xil_printf("AddCommand() failed\n\r");
return Status;
}
/* Add second valid command to Write Region */
CmdPtr->CRamCmd.Address = AXI_ADDRESS + MSTRRAM_INDEX;
CmdPtr->CRamCmd.MasterRamIndex = MSTRRAM_INDEX;
CmdPtr->CRamCmd.Length = 0;
CmdPtr->RdWrFlag = XTG_WRITE;
CmdPtr->CRamCmd.ValidCmd = 1;
CmdPtr->CRamCmd.MyDepend = 0;
/* Make this command dependent on Read logic command 1 */
CmdPtr->CRamCmd.OtherDepend = XTrafGen_GetLastValidIndex(InstancePtr,
XTG_READ) + 1;
Status = XTrafGen_AddCommand(InstancePtr, CmdPtr);
if (Status != XST_SUCCESS) {
xil_printf("AddCommand() failed\n\r");
return Status;
}
/* Add invalid command at the end of Write Queue */
CmdPtr->CRamCmd.Address = AXI_ADDRESS;
CmdPtr->CRamCmd.MasterRamIndex = 0x0;
CmdPtr->RdWrFlag = XTG_WRITE;
CmdPtr->CRamCmd.Size = 0;
CmdPtr->CRamCmd.ValidCmd = 0;
CmdPtr->CRamCmd.MyDepend = 0;
/* Make this command dependent on Read logic command 1 */
CmdPtr->CRamCmd.OtherDepend = XTrafGen_GetLastValidIndex(InstancePtr,
XTG_READ) + 1;;
Status = XTrafGen_AddCommand(InstancePtr, CmdPtr);
if (Status != XST_SUCCESS) {
xil_printf("AddCommand() failed\n\r");
return Status;
}
/* Add invalid command at the end of Read Queue */
CmdPtr->CRamCmd.MasterRamIndex = 0x0;
CmdPtr->RdWrFlag = XTG_READ;
CmdPtr->CRamCmd.Length = 0;
CmdPtr->CRamCmd.Size = 0x0;
CmdPtr->CRamCmd.ValidCmd = 0;
/* Make this command dependent on Write logic command 2 */
CmdPtr->CRamCmd.OtherDepend = XTrafGen_GetLastValidIndex(InstancePtr,
XTG_WRITE) + 1;
Status = XTrafGen_AddCommand(InstancePtr, CmdPtr);
if (Status != XST_SUCCESS) {
xil_printf("AddCommand() failed\n\r");
return Status;
}
/* Display Command list */
#ifdef DEBUG
XTrafGen_PrintCmds(InstancePtr);
#endif
/* Program all prepared commands */
Status = XTrafGen_WriteCmdsToHw(InstancePtr);
if (Status != XST_SUCCESS) {
xil_printf("WriteCmdsToHw() failed\n\r");
return Status;
}
/* Enable Complete Interrupt bit */
XTrafGen_EnableMasterCmpInterrupt(InstancePtr);
/* Set up Interrupt system */
Status = SetupIntrSystem(&Intc, InstancePtr, CMP_INTR_ID, ERR_INTR_ID);
if (Status != XST_SUCCESS) {
xil_printf("Failed intr setup\r\n");
return Status;
}
/* Initialize flags before start transfer test */
Done = 0;
Error = 0;
/* Start Master Logic */
XTrafGen_StartMasterLogic(InstancePtr);
while (!Done && !Error);
if (Error) {
xil_printf("Errors in transfer\r\n");
return XST_FAILURE;
}
/* Read Master RAM */
XTrafGen_AccessMasterRam(InstancePtr, MSTRRAM_INDEX,
sizeof(MasterRamData), XTG_READ, VerifyRamData);
/* Verify Data */
for (Index = 0 ; Index < TEST_LENGTH - 1; Index++) {
if (VerifyRamData[Index] != MasterRamData[Index]) {
xil_printf("Data Mismatch\n\r");
return XST_FAILURE;
}
}
DisableIntrSystem(&Intc, CMP_INTR_ID, ERR_INTR_ID);
return Status;
}
/**
*
* This function demonstrates the usage of AXI FIFO
* It does the following:
* - Set up the output terminal if UART16550 is in the hardware build
* - Initialize the Axi FIFO Device.
* - Set up the interrupt handler for fifo
* - Transmit the data
* - Compare the data
* - Return the result
*
* @param InstancePtr is a pointer to the instance of the
* XLlFifo instance.
* @param DeviceId is Device ID of the Axi Fifo Deive instance,
* typically XPAR_<AXI_FIFO_instance>_DEVICE_ID value from
* xparameters.h.
*
* @return -XST_SUCCESS to indicate success
* -XST_FAILURE to indicate failure
*
******************************************************************************/
int XLlFifoInterruptExample(XLlFifo *InstancePtr, u16 DeviceId)
{
XLlFifo_Config *Config;
int Status;
int i;
int err;
Status = XST_SUCCESS;
/* Initial setup for Uart16550 */
#ifdef XPAR_UARTNS550_0_BASEADDR
Uart550_Setup();
#endif
/* Initialize the Device Configuration Interface driver */
Config = XLlFfio_LookupConfig(DeviceId);
if (!Config) {
xil_printf("No config found for %d\r\n", DeviceId);
return XST_FAILURE;
}
/*
* This is where the virtual address would be used, this example
* uses physical address.
*/
Status = XLlFifo_CfgInitialize(InstancePtr, Config, Config->BaseAddress);
if (Status != XST_SUCCESS) {
xil_printf("Initialization failed\n\r");
return Status;
}
/* Check for the Reset value */
Status = XLlFifo_Status(InstancePtr);
XLlFifo_IntClear(InstancePtr,0xffffffff);
Status = XLlFifo_Status(InstancePtr);
if(Status != 0x0) {
xil_printf("\n ERROR : Reset value of ISR0 : 0x%x\t"
"Expected : 0x0\n\r",
XLlFifo_Status(InstancePtr));
return XST_FAILURE;
}
/*
* Connect the Axi Streaming FIFO to the interrupt subsystem such
* that interrupts can occur. This function is application specific.
*/
Status = SetupInterruptSystem(&Intc, InstancePtr, FIFO_INTR_ID);
if (Status != XST_SUCCESS) {
xil_printf("Failed intr setup\r\n");
return XST_FAILURE;
}
XLlFifo_IntEnable(InstancePtr, XLLF_INT_ALL_MASK);
Done = 0;
/* Transmit the Data Stream */
Status = TxSend(InstancePtr, SourceBuffer);
if (Status != XST_SUCCESS){
xil_printf("Transmission of Data failed\n\r");
return XST_FAILURE;
}
while(!Done);
/* Check for errors */
if(Error) {
xil_printf("Errors in the FIFO\n\r");
return XST_FAILURE;
}
err = 0;
/* Compare the data sent with the data received */
xil_printf("Comparing data...\n\r");
for( i=0 ; i<MAX_DATA_BUFFER_SIZE ; i++ ){
if ( *(SourceBuffer + i) != *(DestinationBuffer + i) ){
err = 1;
break;
}
}
if (err != 0){
return XST_FAILURE;
}
DisableIntrSystem(&Intc, FIFO_INTR_ID);
return Status;
}
/**
*
* This function demonstrates the usage Traffic Generator
* It does the following:
* - Set up the output terminal if UART16550 is in the hardware build
* - Initialize the AXI Traffic Generator device
* - Initialize the Streaming FIFO device
* - Set the Desired Transfer Count and Transfer Length
* - Enable the Traffic Genration on the Core
* - Check for the Streaming data on the FIFO
* - Return test status and exit
*
* @param InstancePtr is a pointer to the instance of the
* XTrafGen component.
* @param DeviceId is Device ID of the Axi Traffic Generator Device,
*
*
* @param InstancePtr is a pointer to the instance of the
* XTrafGen component.
* @param DeviceId is Device ID of the Axi Traffic Generator Device,
* typically XPAR_<TRAFGEN_instance>_DEVICE_ID value from
* xparameters.h.
*
* @return -XST_SUCCESS to indicate success
* -XST_FAILURE to indicate failure
*
******************************************************************************/
int XTrafGenStremingModeMasterExample(XTrafGen *InstancePtr, u16 DeviceId)
{
XTrafGen_Config *Config;
int Status = XST_SUCCESS;
u32 Len;
u32 TransferCnt;
u32 AtgPacket;
u32 FifoOcy;
u32 FifoLen;
/* Initial setup for Uart16550 */
#ifdef XPAR_UARTNS550_0_BASEADDR
Uart550_Setup();
#endif
/* Initialize the Device Configuration Interface driver */
Config = XTrafGen_LookupConfig(DeviceId);
if (!Config) {
xil_printf("No config found for %d\r\n", DeviceId);
return XST_FAILURE;
}
/*
* This is where the virtual address would be used, this example
* uses physical address.
*/
Status = XTrafGen_CfgInitialize(InstancePtr, Config,
Config->BaseAddress);
if (Status != XST_SUCCESS) {
xil_printf("Initialization failed\n\r");
return Status;
}
/* Check for the Streaming Mode */
if(InstancePtr->OperatingMode != XTG_MODE_STREAMING) {
return XST_FAILURE;
}
/* Initialize the Fifo Instance */
XLlFifo_Initialize(&XLlFifoInstance , STR_FIFO0_ADDR);
Status = XLlFifo_Status(&XLlFifoInstance);
XLlFifo_IntClear(&XLlFifoInstance,0xffffffff);
Status = XLlFifo_Status(&XLlFifoInstance);
if(Status != 0x0) {
xil_printf("\n ERROR : Reset value of ISR0 : 0x%x\t"
"Expected : 0x0\n\r",
XLlFifo_Status(&XLlFifoInstance));
return XST_FAILURE;
}
/*
* Set the Required trasaction length
* and required transaction count
*/
XTrafGen_ResetStreamingRandomLen(InstancePtr);
XTrafGen_SetStreamingTransLen(InstancePtr , 3);
XTrafGen_SetStreamingTransCnt(InstancePtr , 2);
Len = XTrafGen_GetStreamingTransLen(InstancePtr);
TransferCnt = XTrafGen_GetStreamingTransCnt(InstancePtr);
/*
* Calculate the ATG data that is sent on the
* CORE when Streaming is Enabled
*/
AtgPacket = (Len +1) * TransferCnt;
/* Enable the traffic genration */
XTrafGen_StreamEnable(InstancePtr);
FifoOcy = XLlFifo_iRxOccupancy(&XLlFifoInstance);
if(FifoOcy != AtgPacket) {
xil_printf("\n ERROR : Not received complete packets : 0x%x \t"
"Expected : 0x%x \n\r",
XLlFifo_iRxOccupancy(&XLlFifoInstance), AtgPacket);
return XST_FAILURE;
}
FifoLen = XLlFifo_iRxGetLen(&XLlFifoInstance);
if(FifoLen != (AtgPacket*4/TransferCnt)) {
xil_printf("\n ERROR : Not received complete bytes : 0x%x \t"
"Expected : 0x%x \n\n\r",
XLlFifo_iRxGetLen(&XLlFifoInstance),Len);
return XST_FAILURE;
}
while(XLlFifo_iRxGetLen(&XLlFifoInstance)) {
xil_printf("Recived packet DATA: 0x%x \n\r",
XLlFifo_RxGetWord(&XLlFifoInstance));
}
if(XLlFifo_iRxOccupancy(&XLlFifoInstance) != 0) {
xil_printf("\n ERROR : RDFO is not becoming Empty : 0x%x \t"
"Expected : 0x0 \n\n\r",
XLlFifo_iRxOccupancy(&XLlFifoInstance));
return XST_FAILURE;
}
if(XLlFifo_iRxGetLen(&XLlFifoInstance) != 0) {
xil_printf("\n ERROR : RLR is not becoming Empty : 0x%x \t"
"Expected : 0x0 \n\n\r",
XLlFifo_iRxGetLen(&XLlFifoInstance));
return XST_FAILURE;
}
return XST_SUCCESS;
}
