sysbus_init_mmio(dev, &tb->iomem); } return 0; } static const VMStateDescription vmstate_timerblock = { .name = "arm_mptimer_timerblock", .version_id = 2, .minimum_version_id = 2, .fields = (VMStateField[]) { VMSTATE_UINT32(count, TimerBlock), VMSTATE_UINT32(load, TimerBlock), VMSTATE_UINT32(control, TimerBlock), VMSTATE_UINT32(status, TimerBlock), VMSTATE_INT64(tick, TimerBlock), VMSTATE_TIMER(timer, TimerBlock), VMSTATE_END_OF_LIST() } }; static const VMStateDescription vmstate_arm_mptimer = { .name = "arm_mptimer", .version_id = 2, .minimum_version_id = 2, .fields = (VMStateField[]) { VMSTATE_STRUCT_VARRAY_UINT32(timerblock, ARMMPTimerState, num_cpu, 2, vmstate_timerblock, TimerBlock), VMSTATE_END_OF_LIST() } };
VMSTATE_MEMORY_HOTPLUG(acpi_memory_hotplug, ICH9LPCPMRegs), VMSTATE_END_OF_LIST() } }; const VMStateDescription vmstate_ich9_pm = { .name = "ich9_pm", .version_id = 1, .minimum_version_id = 1, .post_load = ich9_pm_post_load, .fields = (VMStateField[]) { VMSTATE_UINT16(acpi_regs.pm1.evt.sts, ICH9LPCPMRegs), VMSTATE_UINT16(acpi_regs.pm1.evt.en, ICH9LPCPMRegs), VMSTATE_UINT16(acpi_regs.pm1.cnt.cnt, ICH9LPCPMRegs), VMSTATE_TIMER_PTR(acpi_regs.tmr.timer, ICH9LPCPMRegs), VMSTATE_INT64(acpi_regs.tmr.overflow_time, ICH9LPCPMRegs), VMSTATE_GPE_ARRAY(acpi_regs.gpe.sts, ICH9LPCPMRegs), VMSTATE_GPE_ARRAY(acpi_regs.gpe.en, ICH9LPCPMRegs), VMSTATE_UINT32(smi_en, ICH9LPCPMRegs), VMSTATE_UINT32(smi_sts, ICH9LPCPMRegs), VMSTATE_END_OF_LIST() }, .subsections = (VMStateSubsection[]) { { .vmsd = &vmstate_memhp_state, .needed = vmstate_test_use_memhp, }, VMSTATE_END_OF_LIST() } };
#endif return 0; } static const VMStateDescription vmstate_rtc = { .name = "mc146818rtc", .version_id = 3, .minimum_version_id = 1, .minimum_version_id_old = 1, .post_load = rtc_post_load, .fields = (VMStateField []) { VMSTATE_BUFFER(cmos_data, RTCState), VMSTATE_UINT8(cmos_index, RTCState), VMSTATE_UNUSED(7*4), VMSTATE_TIMER(periodic_timer, RTCState), VMSTATE_INT64(next_periodic_time, RTCState), VMSTATE_UNUSED(3*8), VMSTATE_UINT32_V(irq_coalesced, RTCState, 2), VMSTATE_UINT32_V(period, RTCState, 2), VMSTATE_UINT64_V(base_rtc, RTCState, 3), VMSTATE_UINT64_V(last_update, RTCState, 3), VMSTATE_INT64_V(offset, RTCState, 3), VMSTATE_TIMER_V(update_timer, RTCState, 3), VMSTATE_UINT64_V(next_alarm_time, RTCState, 3), VMSTATE_END_OF_LIST() } }; static void rtc_notify_clock_reset(Notifier *notifier, void *data) { RTCState *s = container_of(notifier, RTCState, clock_reset_notifier);
expire_time = qemu_get_be64(f); if (expire_time != -1) { qemu_mod_timer_ns(ts, expire_time); } else { qemu_del_timer(ts); } } static const VMStateDescription vmstate_timers = { .name = "timer", .version_id = 2, .minimum_version_id = 1, .minimum_version_id_old = 1, .fields = (VMStateField []) { VMSTATE_INT64(cpu_ticks_offset, TimersState), VMSTATE_INT64(dummy, TimersState), VMSTATE_INT64_V(cpu_clock_offset, TimersState, 2), VMSTATE_END_OF_LIST() } }; void configure_icount(const char *option) { vmstate_register(NULL, 0, &vmstate_timers, &timers_state); if (!option) return; #ifdef CONFIG_IOTHREAD vm_clock->warp_timer = qemu_new_timer_ns(rt_clock, icount_warp_rt, NULL); #endif
#include "migration/cpu.h" #ifdef TARGET_SPARC64 static const VMStateDescription vmstate_cpu_timer = { .name = "cpu_timer", .version_id = 1, .minimum_version_id = 1, .minimum_version_id_old = 1, .fields = (VMStateField[]) { VMSTATE_UINT32(frequency, CPUTimer), VMSTATE_UINT32(disabled, CPUTimer), VMSTATE_UINT64(disabled_mask, CPUTimer), VMSTATE_UINT32(npt, CPUTimer), VMSTATE_UINT64(npt_mask, CPUTimer), VMSTATE_INT64(clock_offset, CPUTimer), VMSTATE_TIMER_PTR(qtimer, CPUTimer), VMSTATE_END_OF_LIST() } }; #define VMSTATE_CPU_TIMER(_f, _s) \ VMSTATE_STRUCT_POINTER(_f, _s, vmstate_cpu_timer, CPUTimer) static const VMStateDescription vmstate_trap_state = { .name = "trap_state", .version_id = 1, .minimum_version_id = 1, .minimum_version_id_old = 1, .fields = (VMStateField[]) { VMSTATE_UINT64(tpc, trap_state),
sysbus_init_mmio(dev, &tb->iomem); } return 0; } static const VMStateDescription vmstate_timerblock = { .name = "arm_mptimer_timerblock", .version_id = 1, .minimum_version_id = 1, .fields = (VMStateField[]) { VMSTATE_UINT32(count, timerblock), VMSTATE_UINT32(load, timerblock), VMSTATE_UINT32(control, timerblock), VMSTATE_UINT32(status, timerblock), VMSTATE_INT64(tick, timerblock), VMSTATE_END_OF_LIST() } }; static const VMStateDescription vmstate_arm_mptimer = { .name = "arm_mptimer", .version_id = 1, .minimum_version_id = 1, .fields = (VMStateField[]) { VMSTATE_STRUCT_ARRAY(timerblock, arm_mptimer_state, (MAX_CPUS * 2), 1, vmstate_timerblock, timerblock), VMSTATE_END_OF_LIST() } };
VMSTATE_UINT8(id, APICCommonState), VMSTATE_UINT8(arb_id, APICCommonState), VMSTATE_UINT8(tpr, APICCommonState), VMSTATE_UINT32(spurious_vec, APICCommonState), VMSTATE_UINT8(log_dest, APICCommonState), VMSTATE_UINT8(dest_mode, APICCommonState), VMSTATE_UINT32_ARRAY(isr, APICCommonState, 8), VMSTATE_UINT32_ARRAY(tmr, APICCommonState, 8), VMSTATE_UINT32_ARRAY(irr, APICCommonState, 8), VMSTATE_UINT32_ARRAY(lvt, APICCommonState, APIC_LVT_NB), VMSTATE_UINT32(esr, APICCommonState), VMSTATE_UINT32_ARRAY(icr, APICCommonState, 2), VMSTATE_UINT32(divide_conf, APICCommonState), VMSTATE_INT32(count_shift, APICCommonState), VMSTATE_UINT32(initial_count, APICCommonState), VMSTATE_INT64(initial_count_load_time, APICCommonState), VMSTATE_INT64(next_time, APICCommonState), VMSTATE_INT64(timer_expiry, APICCommonState), /* open-coded timer state */ VMSTATE_END_OF_LIST() }, .subsections = (const VMStateDescription*[]) { &vmstate_apic_common_sipi, NULL } }; static Property apic_properties_common[] = { DEFINE_PROP_UINT8("id", APICCommonState, id, -1), DEFINE_PROP_UINT8("version", APICCommonState, version, 0x14), DEFINE_PROP_BIT("vapic", APICCommonState, vapic_control, VAPIC_ENABLE_BIT,
s->tick_offset = stm32f2xx_ns_to_ticks(s, now) - timer_val; stm32f2xx_timer_set_alarm(s, now); } static const MemoryRegionOps stm32f2xx_timer_ops = { .read = stm32f2xx_timer_read, .write = stm32f2xx_timer_write, .endianness = DEVICE_NATIVE_ENDIAN, }; static const VMStateDescription vmstate_stm32f2xx_timer = { .name = TYPE_STM32F2XX_TIMER, .version_id = 1, .minimum_version_id = 1, .fields = (VMStateField[]) { VMSTATE_INT64(tick_offset, STM32F2XXTimerState), VMSTATE_UINT32(tim_cr1, STM32F2XXTimerState), VMSTATE_UINT32(tim_cr2, STM32F2XXTimerState), VMSTATE_UINT32(tim_smcr, STM32F2XXTimerState), VMSTATE_UINT32(tim_dier, STM32F2XXTimerState), VMSTATE_UINT32(tim_sr, STM32F2XXTimerState), VMSTATE_UINT32(tim_egr, STM32F2XXTimerState), VMSTATE_UINT32(tim_ccmr1, STM32F2XXTimerState), VMSTATE_UINT32(tim_ccmr2, STM32F2XXTimerState), VMSTATE_UINT32(tim_ccer, STM32F2XXTimerState), VMSTATE_UINT32(tim_psc, STM32F2XXTimerState), VMSTATE_UINT32(tim_arr, STM32F2XXTimerState), VMSTATE_UINT32(tim_ccr1, STM32F2XXTimerState), VMSTATE_UINT32(tim_ccr2, STM32F2XXTimerState), VMSTATE_UINT32(tim_ccr3, STM32F2XXTimerState), VMSTATE_UINT32(tim_ccr4, STM32F2XXTimerState),