.version_id = 1, .minimum_version_id = 1, .fields = (VMStateField[]) { VMSTATE_PCI_DEVICE(dev, PCISerialState), VMSTATE_STRUCT(state, PCISerialState, 0, vmstate_serial, SerialState), VMSTATE_END_OF_LIST() } }; static const VMStateDescription vmstate_pci_multi_serial = { .name = "pci-serial-multi", .version_id = 1, .minimum_version_id = 1, .fields = (VMStateField[]) { VMSTATE_PCI_DEVICE(dev, PCIMultiSerialState), VMSTATE_STRUCT_ARRAY(state, PCIMultiSerialState, PCI_SERIAL_MAX_PORTS, 0, vmstate_serial, SerialState), VMSTATE_UINT32_ARRAY(level, PCIMultiSerialState, PCI_SERIAL_MAX_PORTS), VMSTATE_END_OF_LIST() } }; static Property serial_pci_properties[] = { DEFINE_PROP_CHR("chardev", PCISerialState, state.chr), DEFINE_PROP_UINT8("prog_if", PCISerialState, prog_if, 0x02), DEFINE_PROP_END_OF_LIST(), }; static Property multi_2x_serial_pci_properties[] = { DEFINE_PROP_CHR("chardev1", PCIMultiSerialState, state[0].chr), DEFINE_PROP_CHR("chardev2", PCIMultiSerialState, state[1].chr), DEFINE_PROP_UINT8("prog_if", PCIMultiSerialState, prog_if, 0x02),
.minimum_version_id = 2, .post_load = stellaris_enet_post_load, .fields = (VMStateField[]) { VMSTATE_UINT32(ris, stellaris_enet_state), VMSTATE_UINT32(im, stellaris_enet_state), VMSTATE_UINT32(rctl, stellaris_enet_state), VMSTATE_UINT32(tctl, stellaris_enet_state), VMSTATE_UINT32(thr, stellaris_enet_state), VMSTATE_UINT32(mctl, stellaris_enet_state), VMSTATE_UINT32(mdv, stellaris_enet_state), VMSTATE_UINT32(mtxd, stellaris_enet_state), VMSTATE_UINT32(mrxd, stellaris_enet_state), VMSTATE_UINT32(np, stellaris_enet_state), VMSTATE_UINT32(tx_fifo_len, stellaris_enet_state), VMSTATE_UINT8_ARRAY(tx_fifo, stellaris_enet_state, 2048), VMSTATE_STRUCT_ARRAY(rx, stellaris_enet_state, 31, 1, vmstate_rx_frame, StellarisEnetRxFrame), VMSTATE_UINT32(rx_fifo_offset, stellaris_enet_state), VMSTATE_UINT32(next_packet, stellaris_enet_state), VMSTATE_END_OF_LIST() } }; static void stellaris_enet_update(stellaris_enet_state *s) { qemu_set_irq(s->irq, (s->ris & s->im) != 0); } /* Return the data length of the packet currently being assembled * in the TX fifo. */ static inline int stellaris_txpacket_datalen(stellaris_enet_state *s)
.fields = (VMStateField[]) { VMSTATE_UINT32(count, timerblock), VMSTATE_UINT32(load, timerblock), VMSTATE_UINT32(control, timerblock), VMSTATE_UINT32(status, timerblock), VMSTATE_INT64(tick, timerblock), VMSTATE_END_OF_LIST() } }; static const VMStateDescription vmstate_arm_mptimer = { .name = "arm_mptimer", .version_id = 1, .minimum_version_id = 1, .fields = (VMStateField[]) { VMSTATE_STRUCT_ARRAY(timerblock, arm_mptimer_state, (MAX_CPUS * 2), 1, vmstate_timerblock, timerblock), VMSTATE_END_OF_LIST() } }; static void arm_mptimer_class_init(ObjectClass *klass, void *data) { SysBusDeviceClass *sbc = SYS_BUS_DEVICE_CLASS(klass); sbc->init = arm_mptimer_init; } static DeviceInfo arm_mptimer_info = { .name = "arm_mptimer", .size = sizeof(arm_mptimer_state), .vmsd = &vmstate_arm_mptimer,
static bool pxa2xx_timer_has_tm4_test(void *opaque, int version_id) { return pxa2xx_timer_has_tm4(opaque); } static const VMStateDescription vmstate_pxa2xx_timer_regs = { .name = "pxa2xx_timer", .version_id = 1, .minimum_version_id = 1, .minimum_version_id_old = 1, .post_load = pxa25x_timer_post_load, .fields = (VMStateField[]) { VMSTATE_INT32(clock, PXA2xxTimerInfo), VMSTATE_INT32(oldclock, PXA2xxTimerInfo), VMSTATE_UINT64(lastload, PXA2xxTimerInfo), VMSTATE_STRUCT_ARRAY(timer, PXA2xxTimerInfo, 4, 1, vmstate_pxa2xx_timer0_regs, PXA2xxTimer0), VMSTATE_UINT32(events, PXA2xxTimerInfo), VMSTATE_UINT32(irq_enabled, PXA2xxTimerInfo), VMSTATE_UINT32(reset3, PXA2xxTimerInfo), VMSTATE_UINT32(snapshot, PXA2xxTimerInfo), VMSTATE_STRUCT_ARRAY_TEST(tm4, PXA2xxTimerInfo, 8, pxa2xx_timer_has_tm4_test, 0, vmstate_pxa2xx_timer4_regs, PXA2xxTimer4), VMSTATE_END_OF_LIST(), } }; static Property pxa25x_timer_dev_properties[] = { DEFINE_PROP_UINT32("freq", PXA2xxTimerInfo, freq, PXA25X_FREQ), DEFINE_PROP_BIT("tm4", PXA2xxTimerInfo, flags, PXA2XX_TIMER_HAVE_TM4, false),
VMSTATE_INT32(env.CP0_Config1, MIPSCPU), VMSTATE_INT32(env.CP0_Config2, MIPSCPU), VMSTATE_INT32(env.CP0_Config3, MIPSCPU), VMSTATE_INT32(env.CP0_Config6, MIPSCPU), VMSTATE_INT32(env.CP0_Config7, MIPSCPU), VMSTATE_UINTTL(env.lladdr, MIPSCPU), VMSTATE_UINTTL_ARRAY(env.CP0_WatchLo, MIPSCPU, 8), VMSTATE_INT32_ARRAY(env.CP0_WatchHi, MIPSCPU, 8), VMSTATE_UINTTL(env.CP0_XContext, MIPSCPU), VMSTATE_INT32(env.CP0_Framemask, MIPSCPU), VMSTATE_INT32(env.CP0_Debug, MIPSCPU), VMSTATE_UINTTL(env.CP0_DEPC, MIPSCPU), VMSTATE_INT32(env.CP0_Performance0, MIPSCPU), VMSTATE_INT32(env.CP0_TagLo, MIPSCPU), VMSTATE_INT32(env.CP0_DataLo, MIPSCPU), VMSTATE_INT32(env.CP0_TagHi, MIPSCPU), VMSTATE_INT32(env.CP0_DataHi, MIPSCPU), VMSTATE_UINTTL(env.CP0_ErrorEPC, MIPSCPU), VMSTATE_INT32(env.CP0_DESAVE, MIPSCPU), VMSTATE_UINTTL_ARRAY(env.CP0_KScratch, MIPSCPU, MIPS_KSCRATCH_NUM), /* Inactive TC */ VMSTATE_STRUCT_ARRAY(env.tcs, MIPSCPU, MIPS_SHADOW_SET_MAX, 1, vmstate_inactive_tc, TCState), VMSTATE_STRUCT_ARRAY(env.fpus, MIPSCPU, MIPS_FPU_MAX, 1, vmstate_inactive_fpu, CPUMIPSFPUContext), VMSTATE_END_OF_LIST() }, };
VMSTATE_BOOL(edge_trigger, gic_irq_state), VMSTATE_UINT8(group, gic_irq_state), VMSTATE_END_OF_LIST() } }; static const VMStateDescription vmstate_gic = { .name = "arm_gic", .version_id = 12, .minimum_version_id = 12, .pre_save = gic_pre_save, .post_load = gic_post_load, .fields = (VMStateField[]) { VMSTATE_UINT32(ctlr, GICState), VMSTATE_UINT32_ARRAY(cpu_ctlr, GICState, GIC_NCPU), VMSTATE_STRUCT_ARRAY(irq_state, GICState, GIC_MAXIRQ, 1, vmstate_gic_irq_state, gic_irq_state), VMSTATE_UINT8_ARRAY(irq_target, GICState, GIC_MAXIRQ), VMSTATE_UINT8_2DARRAY(priority1, GICState, GIC_INTERNAL, GIC_NCPU), VMSTATE_UINT8_ARRAY(priority2, GICState, GIC_MAXIRQ - GIC_INTERNAL), VMSTATE_UINT8_2DARRAY(sgi_pending, GICState, GIC_NR_SGIS, GIC_NCPU), VMSTATE_UINT16_ARRAY(priority_mask, GICState, GIC_NCPU), VMSTATE_UINT16_ARRAY(running_priority, GICState, GIC_NCPU), VMSTATE_UINT16_ARRAY(current_pending, GICState, GIC_NCPU), VMSTATE_UINT8_ARRAY(bpr, GICState, GIC_NCPU), VMSTATE_UINT8_ARRAY(abpr, GICState, GIC_NCPU), VMSTATE_UINT32_2DARRAY(apr, GICState, GIC_NR_APRS, GIC_NCPU), VMSTATE_UINT32_2DARRAY(nsapr, GICState, GIC_NR_APRS, GIC_NCPU), VMSTATE_END_OF_LIST() } };
VMSTATE_UINT32(count, BCM2835Mbox), VMSTATE_UINT32(status, BCM2835Mbox), VMSTATE_UINT32(config, BCM2835Mbox), VMSTATE_END_OF_LIST() } }; /* vmstate of the entire device */ static const VMStateDescription vmstate_bcm2835_mbox = { .name = TYPE_BCM2835_MBOX, .version_id = 1, .minimum_version_id = 1, .minimum_version_id_old = 1, .fields = (VMStateField[]) { VMSTATE_BOOL_ARRAY(available, BCM2835MboxState, MBOX_CHAN_COUNT), VMSTATE_STRUCT_ARRAY(mbox, BCM2835MboxState, 2, 1, vmstate_bcm2835_mbox_box, BCM2835Mbox), VMSTATE_END_OF_LIST() } }; static void bcm2835_mbox_init(Object *obj) { BCM2835MboxState *s = BCM2835_MBOX(obj); memory_region_init_io(&s->iomem, obj, &bcm2835_mbox_ops, s, TYPE_BCM2835_MBOX, 0x400); sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->iomem); sysbus_init_irq(SYS_BUS_DEVICE(s), &s->arm_irq); qdev_init_gpio_in(DEVICE(s), bcm2835_mbox_set_irq, MBOX_CHAN_COUNT); }
VMSTATE_UINT32(intr_ctrl, AspeedI2CBus), VMSTATE_UINT32(intr_status, AspeedI2CBus), VMSTATE_UINT32(cmd, AspeedI2CBus), VMSTATE_UINT32(buf, AspeedI2CBus), VMSTATE_END_OF_LIST() } }; static const VMStateDescription aspeed_i2c_vmstate = { .name = TYPE_ASPEED_I2C, .version_id = 1, .minimum_version_id = 1, .fields = (VMStateField[]) { VMSTATE_UINT32(intr_status, AspeedI2CState), VMSTATE_STRUCT_ARRAY(busses, AspeedI2CState, ASPEED_I2C_NR_BUSSES, 1, aspeed_i2c_bus_vmstate, AspeedI2CBus), VMSTATE_END_OF_LIST() } }; static void aspeed_i2c_reset(DeviceState *dev) { int i; AspeedI2CState *s = ASPEED_I2C(dev); s->intr_status = 0; for (i = 0; i < ASPEED_I2C_NR_BUSSES; i++) { s->busses[i].intr_ctrl = 0; s->busses[i].intr_status = 0;