void MACvSetMISCFifo(void __iomem *dwIoBase, unsigned short wOffset, unsigned long dwData)
{
if (wOffset > 273)
return;
VNSvOutPortW(dwIoBase + MAC_REG_MISCFFNDEX, wOffset);
VNSvOutPortD(dwIoBase + MAC_REG_MISCFFDATA, dwData);
VNSvOutPortW(dwIoBase + MAC_REG_MISCFFCTL, MISCFFCTL_WRITE);
}
VOID
PSvEnablePowerSaving(
IN HANDLE hDeviceContext,
IN WORD wListenInterval
)
{
PSDevice pDevice = (PSDevice)hDeviceContext;
PSMgmtObject pMgmt = pDevice->pMgmt;
WORD wAID = pMgmt->wCurrAID | BIT14 | BIT15;
VNSvOutPortW(pDevice->PortOffset + MAC_REG_PWBT, C_PWBT);
if (pDevice->eOPMode != OP_MODE_ADHOC) {
VNSvOutPortW(pDevice->PortOffset + MAC_REG_AIDATIM, wAID);
} else {
MACvWriteATIMW(pDevice->PortOffset, pMgmt->wCurrATIMWindow);
}
MACvRegBitsOn(pDevice->PortOffset, MAC_REG_PSCFG, PSCFG_AUTOSLEEP);
MACvRegBitsOn(pDevice->PortOffset, MAC_REG_TFTCTL, TFTCTL_HWUTSF);
if (wListenInterval >= 2) {
MACvRegBitsOff(pDevice->PortOffset, MAC_REG_PSCTL, PSCTL_ALBCN);
MACvRegBitsOn(pDevice->PortOffset, MAC_REG_PSCTL, PSCTL_LNBCN);
pMgmt->wCountToWakeUp = wListenInterval;
}
else {
MACvRegBitsOn(pDevice->PortOffset, MAC_REG_PSCTL, PSCTL_ALBCN);
pMgmt->wCountToWakeUp = 0;
}
MACvRegBitsOn(pDevice->PortOffset, MAC_REG_PSCTL, PSCTL_PSEN);
pDevice->bEnablePSMode = TRUE;
if (pDevice->eOPMode == OP_MODE_ADHOC) {
}
else if (pDevice->eOPMode == OP_MODE_INFRASTRUCTURE) {
PSbSendNullPacket(pDevice);
}
pDevice->bPWBitOn = TRUE;
DBG_PRT(MSG_LEVEL_DEBUG, KERN_INFO "PS:Power Saving Mode Enable... \n");
return;
}
/*
* Description:
* Disable the Key Entry by MISCFIFO
*
* Parameters:
* In:
* dwIoBase - Base Address for MAC
*
* Out:
* none
*
* Return Value: none
*
*/
void MACvDisableKeyEntry(void __iomem *dwIoBase, unsigned int uEntryIdx)
{
unsigned short wOffset;
wOffset = MISCFIFO_KEYETRY0;
wOffset += (uEntryIdx * MISCFIFO_KEYENTRYSIZE);
VNSvOutPortW(dwIoBase + MAC_REG_MISCFFNDEX, wOffset);
VNSvOutPortD(dwIoBase + MAC_REG_MISCFFDATA, 0);
VNSvOutPortW(dwIoBase + MAC_REG_MISCFFCTL, MISCFFCTL_WRITE);
}
VOID
PSvEnablePowerSaving(
IN HANDLE hDeviceContext,
IN WORD wListenInterval
)
{
PSDevice pDevice = (PSDevice)hDeviceContext;
PSMgmtObject pMgmt = pDevice->pMgmt;
WORD wAID = pMgmt->wCurrAID | BIT14 | BIT15;
// set period of power up before TBTT
VNSvOutPortW(pDevice->PortOffset + MAC_REG_PWBT, C_PWBT);
if (pDevice->eOPMode != OP_MODE_ADHOC) {
// set AID
VNSvOutPortW(pDevice->PortOffset + MAC_REG_AIDATIM, wAID);
} else {
// set ATIM Window
MACvWriteATIMW(pDevice->PortOffset, pMgmt->wCurrATIMWindow);
}
// Set AutoSleep
MACvRegBitsOn(pDevice->PortOffset, MAC_REG_PSCFG, PSCFG_AUTOSLEEP);
// Set HWUTSF
MACvRegBitsOn(pDevice->PortOffset, MAC_REG_TFTCTL, TFTCTL_HWUTSF);
if (wListenInterval >= 2) {
// clear always listen beacon
MACvRegBitsOff(pDevice->PortOffset, MAC_REG_PSCTL, PSCTL_ALBCN);
//pDevice->wCFG &= ~CFG_ALB;
// first time set listen next beacon
MACvRegBitsOn(pDevice->PortOffset, MAC_REG_PSCTL, PSCTL_LNBCN);
pMgmt->wCountToWakeUp = wListenInterval;
}
else {
// always listen beacon
MACvRegBitsOn(pDevice->PortOffset, MAC_REG_PSCTL, PSCTL_ALBCN);
//pDevice->wCFG |= CFG_ALB;
pMgmt->wCountToWakeUp = 0;
}
// enable power saving hw function
MACvRegBitsOn(pDevice->PortOffset, MAC_REG_PSCTL, PSCTL_PSEN);
pDevice->bEnablePSMode = TRUE;
if (pDevice->eOPMode == OP_MODE_ADHOC) {
// bMgrPrepareBeaconToSend((HANDLE)pDevice, pMgmt);
}
// We don't send null pkt in ad hoc mode since beacon will handle this.
else if (pDevice->eOPMode == OP_MODE_INFRASTRUCTURE) {
PSbSendNullPacket(pDevice);
}
pDevice->bPWBitOn = TRUE;
DEVICE_PRT(MSG_LEVEL_DEBUG, KERN_INFO "PS:Power Saving Mode Enable... \n");
return;
}
VOID GMACvSetVCAM(DWORD dwIoBase, BYTE byAddress, WORD wVID)
{
BYTE byOrgCAMCR, byData;
/* modify CAMCR to select CAM DATA regs */
VNSvInPortB(dwIoBase + MAC_REG_CAMCR, &byOrgCAMCR);
byData = (BYTE)((byOrgCAMCR | CAMCR_PS1) & ~CAMCR_PS0);
VNSvOutPortB(dwIoBase + MAC_REG_CAMCR, byData);
/* enable/select VCAM */
VNSvOutPortB(dwIoBase + MAC_REG_CAMADDR, (BYTE)(CAMADDR_CAMEN | CAMADDR_VCAMSL | byAddress));
/* set VCAM data */
VNSvOutPortW(dwIoBase + MAC_REG_CAM, wVID);
/* issue write command */
MACvRegBitsOn(dwIoBase, MAC_REG_CAMCR, CAMCR_CAMWR);
/* Wait for CAMWR self clear */
while (TRUE) {
if (GMACbIsRegBitsOff(dwIoBase, MAC_REG_CAMCR, CAMCR_CAMWR))
break;
}
/* disable CAMEN */
VNSvOutPortB(dwIoBase + MAC_REG_CAMADDR, 0);
/* restore to original CAMCR */
VNSvOutPortB(dwIoBase + MAC_REG_CAMCR, byOrgCAMCR);
}
VOID GMACvTimer0MiniSDelay(DWORD dwIoBase, BYTE byRevId, UINT udelay)
{
BYTE byData;
/* Disable Timer0 Interrupt */
MACvRegBitsOff(dwIoBase, MAC_REG_IMR + 2, (BYTE)(ISR_TMR0I >> 16));
/* Set resolution to mini second */
MACvRegBitsOff(dwIoBase, MAC_REG_CHIPGCR, CHIPGCR_TM0US);
/* set delay time to udelay, unit is mini-second */
VNSvOutPortW(dwIoBase + MAC_REG_SOFT_TIMER0, (WORD)udelay);
/* enable timer0 */
VNSvOutPortB(dwIoBase + MAC_REG_CR1_SET, CR1_TM0EN);
/* wait for TM0EN self clear */
while (TRUE) {
if (GMACbIsRegBitsOff(dwIoBase, MAC_REG_CR1_SET, CR1_TM0EN)) {
/* clear TMR0I */
VNSvInPortB(dwIoBase + MAC_REG_ISR + 2, &byData);
VNSvOutPortB(dwIoBase + MAC_REG_ISR + 2, byData);
break;
}
}
/* Enable Timer0 Interrupt */
MACvRegBitsOn(dwIoBase, MAC_REG_IMR + 2, (BYTE)(ISR_TMR0I >> 16));
}
VOID GMACvSetMCAM(DWORD dwIoBase, BYTE byAddress, PBYTE pbyData)
{
BYTE byOrgCAMCR, byData;
/* DWORD dwData; */
/* modify CAMCR to select CAM DATA regs */
VNSvInPortB(dwIoBase + MAC_REG_CAMCR, &byOrgCAMCR);
byData = (BYTE)((byOrgCAMCR | CAMCR_PS1) & ~CAMCR_PS0);
VNSvOutPortB(dwIoBase + MAC_REG_CAMCR, byData);
/* enable/select MCAM */
VNSvOutPortB(dwIoBase + MAC_REG_CAMADDR, (BYTE)(CAMADDR_CAMEN | byAddress));
/* set MCAM Data */
VNSvOutPortD(dwIoBase + MAC_REG_CAM, *(PDWORD)pbyData);
/* VNSvInPortD(dwIoBase + MAC_REG_CAM, &dwData); */
VNSvOutPortW(dwIoBase + MAC_REG_CAM + 4, *(PWORD)(pbyData + 4));
/* VNSvInPortW(dwIoBase + MAC_REG_CAM + 4, (PWORD)(&dwData)); */
/* issue write command */
MACvRegBitsOn(dwIoBase, MAC_REG_CAMCR, CAMCR_CAMWR);
/* Wait for CAMWR self clear */
while (TRUE) {
if (GMACbIsRegBitsOff(dwIoBase, MAC_REG_CAMCR, CAMCR_CAMWR))
break;
}
/* disable CAMEN */
VNSvOutPortB(dwIoBase + MAC_REG_CAMADDR, 0);
/* restore to original CAMCR */
VNSvOutPortB(dwIoBase + MAC_REG_CAMCR, byOrgCAMCR);
}
void PSvEnablePowerSaving(struct vnt_private *priv,
unsigned short wListenInterval)
{
u16 wAID = priv->current_aid | BIT(14) | BIT(15);
/* set period of power up before TBTT */
VNSvOutPortW(priv->PortOffset + MAC_REG_PWBT, C_PWBT);
if (priv->op_mode != NL80211_IFTYPE_ADHOC) {
/* set AID */
VNSvOutPortW(priv->PortOffset + MAC_REG_AIDATIM, wAID);
} else {
/* set ATIM Window */
#if 0 /* TODO atim window */
MACvWriteATIMW(priv->PortOffset, pMgmt->wCurrATIMWindow);
#endif
}
/* Set AutoSleep */
MACvRegBitsOn(priv->PortOffset, MAC_REG_PSCFG, PSCFG_AUTOSLEEP);
/* Set HWUTSF */
MACvRegBitsOn(priv->PortOffset, MAC_REG_TFTCTL, TFTCTL_HWUTSF);
if (wListenInterval >= 2) {
/* clear always listen beacon */
MACvRegBitsOff(priv->PortOffset, MAC_REG_PSCTL, PSCTL_ALBCN);
/* first time set listen next beacon */
MACvRegBitsOn(priv->PortOffset, MAC_REG_PSCTL, PSCTL_LNBCN);
} else {
/* always listen beacon */
MACvRegBitsOn(priv->PortOffset, MAC_REG_PSCTL, PSCTL_ALBCN);
}
/* enable power saving hw function */
MACvRegBitsOn(priv->PortOffset, MAC_REG_PSCTL, PSCTL_PSEN);
priv->bEnablePSMode = true;
priv->bPWBitOn = true;
pr_debug("PS:Power Saving Mode Enable...\n");
}
VOID GMACvTimer0MicroSDelay(DWORD dwIoBase, BYTE byRevId, UINT udelay)
{
BYTE byData;
/* Notice!!! */
/* Disable Timer0 Interrupt */
MACvRegBitsOff(dwIoBase, MAC_REG_IMR + 2, (BYTE)(ISR_TMR0I >> 16));
/* Set resolution to micro second */
MACvRegBitsOn(dwIoBase, MAC_REG_CHIPGCR, CHIPGCR_TM0US);
/* set delay time to udelay, unit is micro-second */
VNSvOutPortW(dwIoBase + MAC_REG_SOFT_TIMER0, (WORD)udelay);
/* enable timer0 */
VNSvOutPortB(dwIoBase + MAC_REG_CR1_SET, CR1_TM0EN);
/* wait for TM0EN self clear */
while (TRUE) {
/* Method 1 -> OK, and safe */
if (GMACbIsRegBitsOff(dwIoBase, MAC_REG_CR1_SET, CR1_TM0EN)) {
/* clear TMR0I */
VNSvInPortB(dwIoBase + MAC_REG_ISR + 2, &byData);
VNSvOutPortB(dwIoBase + MAC_REG_ISR + 2, byData);
break;
}
/*
// Method 2 -> OK, but not safe
VNSvInPortB(dwIoBase + MAC_REG_ISR + 2, &byData);
if (BITbIsBitOn(byData, (BYTE)(ISR_TMR0I >> 16))) {
VNSvOutPortB(dwIoBase + MAC_REG_ISR + 2, byData);
break;
}
*/
/*
// Method 3 -> OK, but not safe
if (MACbIsRegBitsOn(dwIoBase, MAC_REG_ISR + 2, (BYTE)(ISR_TMR0I >> 16))) {
// clear TMR0I
VNSvOutPortB(dwIoBase + MAC_REG_ISR + 2, (BYTE)(ISR_TMR0I >> 16));
break;
}
*/
}
/* Notice !!! */
/* Enable Timer0 Interrupt */
MACvRegBitsOn(dwIoBase, MAC_REG_IMR + 2, (BYTE)(ISR_TMR0I >> 16));
}
void MACvSetKeyEntry(void __iomem *dwIoBase, unsigned short wKeyCtl,
unsigned int uEntryIdx, unsigned int uKeyIdx,
unsigned char *pbyAddr, u32 *pdwKey,
unsigned char byLocalID)
{
unsigned short wOffset;
u32 dwData;
int ii;
if (byLocalID <= 1)
return;
pr_debug("MACvSetKeyEntry\n");
wOffset = MISCFIFO_KEYETRY0;
wOffset += (uEntryIdx * MISCFIFO_KEYENTRYSIZE);
dwData = 0;
dwData |= wKeyCtl;
dwData <<= 16;
dwData |= MAKEWORD(*(pbyAddr+4), *(pbyAddr+5));
pr_debug("1. wOffset: %d, Data: %X, KeyCtl:%X\n",
wOffset, dwData, wKeyCtl);
VNSvOutPortW(dwIoBase + MAC_REG_MISCFFNDEX, wOffset);
VNSvOutPortD(dwIoBase + MAC_REG_MISCFFDATA, dwData);
VNSvOutPortW(dwIoBase + MAC_REG_MISCFFCTL, MISCFFCTL_WRITE);
wOffset++;
dwData = 0;
dwData |= *(pbyAddr+3);
dwData <<= 8;
dwData |= *(pbyAddr+2);
dwData <<= 8;
dwData |= *(pbyAddr+1);
dwData <<= 8;
dwData |= *(pbyAddr+0);
pr_debug("2. wOffset: %d, Data: %X\n", wOffset, dwData);
VNSvOutPortW(dwIoBase + MAC_REG_MISCFFNDEX, wOffset);
VNSvOutPortD(dwIoBase + MAC_REG_MISCFFDATA, dwData);
VNSvOutPortW(dwIoBase + MAC_REG_MISCFFCTL, MISCFFCTL_WRITE);
wOffset++;
wOffset += (uKeyIdx * 4);
for (ii = 0; ii < 4; ii++) {
/* always push 128 bits */
pr_debug("3.(%d) wOffset: %d, Data: %X\n",
ii, wOffset+ii, *pdwKey);
VNSvOutPortW(dwIoBase + MAC_REG_MISCFFNDEX, wOffset+ii);
VNSvOutPortD(dwIoBase + MAC_REG_MISCFFDATA, *pdwKey++);
VNSvOutPortW(dwIoBase + MAC_REG_MISCFFCTL, MISCFFCTL_WRITE);
}
}
VOID GMACvSetTqIndex(DWORD dwIoBase, BYTE byTxQue, WORD wTdIdx)
{
BYTE byData;
/* Clear RUN */
VNSvOutPortB(dwIoBase + MAC_REG_TDCSR_CLR + (byTxQue / 2), (BYTE)(TRDCSR_RUN << ((byTxQue % 2)*4)));
/* Wait for RUN clear */
while (TRUE) {
VNSvInPortB(dwIoBase + MAC_REG_TDCSR_SET + (byTxQue / 2), &byData);
if (BITbIsBitOff(byData, TRDCSR_RUN << ((byTxQue % 2)*4)))
break;
}
/* Set TdIdx */
VNSvOutPortW(dwIoBase + MAC_REG_TDINDX + byTxQue*2, wTdIdx);
/* Set RUN */
VNSvOutPortB(dwIoBase + MAC_REG_TDCSR_SET + (byTxQue / 2), (BYTE)(TRDCSR_RUN << ((byTxQue % 2)*4)));
}
BOOL GMACbSafeTxOff(DWORD dwIoBase, BYTE byRevId)
{
WORD ww;
/* clear RUN Tx */
VNSvOutPortW(dwIoBase + MAC_REG_TDCSR_CLR, 0x1111);
/* try to safe shutdown TX */
MACvTxOff(dwIoBase);
/* safe delay time */
PCAvDelayByIO(CB_DELAY_SOFT_RESET);
/* W_MAX_TIMEOUT is the timeout period */
for (ww = 0; ww < W_MAX_TIMEOUT; ww++) {
if (GMACbIsRegBitsOff(dwIoBase, MAC_REG_CR0_SET, (BYTE)CR0_TXON))
break;
}
if (ww == W_MAX_TIMEOUT)
return FALSE;
return TRUE;
}
static irqreturn_t device_intr(int irq, void *dev_instance)
{
struct vnt_private *pDevice = dev_instance;
int max_count = 0;
unsigned long dwMIBCounter = 0;
unsigned char byOrgPageSel = 0;
int handled = 0;
unsigned long flags;
MACvReadISR(pDevice->PortOffset, &pDevice->dwIsr);
if (pDevice->dwIsr == 0)
return IRQ_RETVAL(handled);
if (pDevice->dwIsr == 0xffffffff) {
pr_debug("dwIsr = 0xffff\n");
return IRQ_RETVAL(handled);
}
handled = 1;
MACvIntDisable(pDevice->PortOffset);
spin_lock_irqsave(&pDevice->lock, flags);
//Make sure current page is 0
VNSvInPortB(pDevice->PortOffset + MAC_REG_PAGE1SEL, &byOrgPageSel);
if (byOrgPageSel == 1)
MACvSelectPage0(pDevice->PortOffset);
else
byOrgPageSel = 0;
MACvReadMIBCounter(pDevice->PortOffset, &dwMIBCounter);
// TBD....
// Must do this after doing rx/tx, cause ISR bit is slow
// than RD/TD write back
// update ISR counter
STAvUpdate802_11Counter(&pDevice->s802_11Counter, &pDevice->scStatistic, dwMIBCounter);
while (pDevice->dwIsr != 0) {
STAvUpdateIsrStatCounter(&pDevice->scStatistic, pDevice->dwIsr);
MACvWriteISR(pDevice->PortOffset, pDevice->dwIsr);
if (pDevice->dwIsr & ISR_FETALERR) {
pr_debug(" ISR_FETALERR\n");
VNSvOutPortB(pDevice->PortOffset + MAC_REG_SOFTPWRCTL, 0);
VNSvOutPortW(pDevice->PortOffset + MAC_REG_SOFTPWRCTL, SOFTPWRCTL_SWPECTI);
device_error(pDevice, pDevice->dwIsr);
}
if (pDevice->dwIsr & ISR_TBTT) {
if (pDevice->vif &&
pDevice->op_mode != NL80211_IFTYPE_ADHOC)
vnt_check_bb_vga(pDevice);
pDevice->bBeaconSent = false;
if (pDevice->bEnablePSMode)
PSbIsNextTBTTWakeUp((void *)pDevice);
if ((pDevice->op_mode == NL80211_IFTYPE_AP ||
pDevice->op_mode == NL80211_IFTYPE_ADHOC) &&
pDevice->vif->bss_conf.enable_beacon) {
MACvOneShotTimer1MicroSec(pDevice->PortOffset,
(pDevice->vif->bss_conf.beacon_int - MAKE_BEACON_RESERVED) << 10);
}
/* TODO: adhoc PS mode */
}
if (pDevice->dwIsr & ISR_BNTX) {
if (pDevice->op_mode == NL80211_IFTYPE_ADHOC) {
pDevice->bIsBeaconBufReadySet = false;
pDevice->cbBeaconBufReadySetCnt = 0;
}
pDevice->bBeaconSent = true;
}
if (pDevice->dwIsr & ISR_RXDMA0)
max_count += device_rx_srv(pDevice, TYPE_RXDMA0);
if (pDevice->dwIsr & ISR_RXDMA1)
max_count += device_rx_srv(pDevice, TYPE_RXDMA1);
if (pDevice->dwIsr & ISR_TXDMA0)
max_count += device_tx_srv(pDevice, TYPE_TXDMA0);
if (pDevice->dwIsr & ISR_AC0DMA)
max_count += device_tx_srv(pDevice, TYPE_AC0DMA);
if (pDevice->dwIsr & ISR_SOFTTIMER1) {
if (pDevice->vif) {
if (pDevice->vif->bss_conf.enable_beacon)
vnt_beacon_make(pDevice, pDevice->vif);
}
}
/* If both buffers available wake the queue */
if (pDevice->vif) {
if (AVAIL_TD(pDevice, TYPE_TXDMA0) &&
AVAIL_TD(pDevice, TYPE_AC0DMA) &&
ieee80211_queue_stopped(pDevice->hw, 0))
ieee80211_wake_queues(pDevice->hw);
}
MACvReadISR(pDevice->PortOffset, &pDevice->dwIsr);
MACvReceive0(pDevice->PortOffset);
MACvReceive1(pDevice->PortOffset);
if (max_count > pDevice->sOpts.int_works)
break;
}
if (byOrgPageSel == 1)
MACvSelectPage1(pDevice->PortOffset);
spin_unlock_irqrestore(&pDevice->lock, flags);
MACvIntEnable(pDevice->PortOffset, IMR_MASK_VALUE);
return IRQ_RETVAL(handled);
}
static void vnt_interrupt_process(struct vnt_private *priv)
{
struct ieee80211_low_level_stats *low_stats = &priv->low_stats;
int max_count = 0;
u32 mib_counter;
u32 isr;
unsigned long flags;
MACvReadISR(priv->PortOffset, &isr);
if (isr == 0)
return;
if (isr == 0xffffffff) {
pr_debug("isr = 0xffff\n");
return;
}
MACvIntDisable(priv->PortOffset);
spin_lock_irqsave(&priv->lock, flags);
/* Read low level stats */
MACvReadMIBCounter(priv->PortOffset, &mib_counter);
low_stats->dot11RTSSuccessCount += mib_counter & 0xff;
low_stats->dot11RTSFailureCount += (mib_counter >> 8) & 0xff;
low_stats->dot11ACKFailureCount += (mib_counter >> 16) & 0xff;
low_stats->dot11FCSErrorCount += (mib_counter >> 24) & 0xff;
/*
* TBD....
* Must do this after doing rx/tx, cause ISR bit is slow
* than RD/TD write back
* update ISR counter
*/
while (isr && priv->vif) {
MACvWriteISR(priv->PortOffset, isr);
if (isr & ISR_FETALERR) {
pr_debug(" ISR_FETALERR\n");
VNSvOutPortB(priv->PortOffset + MAC_REG_SOFTPWRCTL, 0);
VNSvOutPortW(priv->PortOffset +
MAC_REG_SOFTPWRCTL, SOFTPWRCTL_SWPECTI);
device_error(priv, isr);
}
if (isr & ISR_TBTT) {
if (priv->op_mode != NL80211_IFTYPE_ADHOC)
vnt_check_bb_vga(priv);
priv->bBeaconSent = false;
if (priv->bEnablePSMode)
PSbIsNextTBTTWakeUp((void *)priv);
if ((priv->op_mode == NL80211_IFTYPE_AP ||
priv->op_mode == NL80211_IFTYPE_ADHOC) &&
priv->vif->bss_conf.enable_beacon) {
MACvOneShotTimer1MicroSec(priv->PortOffset,
(priv->vif->bss_conf.beacon_int - MAKE_BEACON_RESERVED) << 10);
}
/* TODO: adhoc PS mode */
}
if (isr & ISR_BNTX) {
if (priv->op_mode == NL80211_IFTYPE_ADHOC) {
priv->bIsBeaconBufReadySet = false;
priv->cbBeaconBufReadySetCnt = 0;
}
priv->bBeaconSent = true;
}
if (isr & ISR_RXDMA0)
max_count += device_rx_srv(priv, TYPE_RXDMA0);
if (isr & ISR_RXDMA1)
max_count += device_rx_srv(priv, TYPE_RXDMA1);
if (isr & ISR_TXDMA0)
max_count += device_tx_srv(priv, TYPE_TXDMA0);
if (isr & ISR_AC0DMA)
max_count += device_tx_srv(priv, TYPE_AC0DMA);
if (isr & ISR_SOFTTIMER1) {
if (priv->vif->bss_conf.enable_beacon)
vnt_beacon_make(priv, priv->vif);
}
/* If both buffers available wake the queue */
if (AVAIL_TD(priv, TYPE_TXDMA0) &&
AVAIL_TD(priv, TYPE_AC0DMA) &&
ieee80211_queue_stopped(priv->hw, 0))
ieee80211_wake_queues(priv->hw);
MACvReadISR(priv->PortOffset, &isr);
MACvReceive0(priv->PortOffset);
MACvReceive1(priv->PortOffset);
if (max_count > priv->sOpts.int_works)
break;
}
spin_unlock_irqrestore(&priv->lock, flags);
MACvIntEnable(priv->PortOffset, IMR_MASK_VALUE);
}
/*
* Description: Write WakeProgSyn
*
* Parameters:
* In:
* dwIoBase - I/O base address
* uChannel - channel number
* bySleepCnt - SleepProgSyn count
*
* Return Value: None.
*
*/
BOOL RFvWriteWakeProgSyn (DWORD_PTR dwIoBase, BYTE byRFType, UINT uChannel)
{
int ii;
BYTE byInitCount = 0;
BYTE bySleepCount = 0;
VNSvOutPortW(dwIoBase + MAC_REG_MISCFFNDEX, 0);
switch (byRFType) {
case RF_AIROHA:
case RF_AL2230S:
if (uChannel > CB_MAX_CHANNEL_24G)
return FALSE;
byInitCount = CB_AL2230_INIT_SEQ + 2; // Init Reg + Channel Reg (2)
bySleepCount = 0;
if (byInitCount > (MISCFIFO_SYNDATASIZE - bySleepCount)) {
return FALSE;
}
for (ii = 0; ii < CB_AL2230_INIT_SEQ; ii++ ) {
MACvSetMISCFifo(dwIoBase, (WORD)(MISCFIFO_SYNDATA_IDX + ii), dwAL2230InitTable[ii]);
}
MACvSetMISCFifo(dwIoBase, (WORD)(MISCFIFO_SYNDATA_IDX + ii), dwAL2230ChannelTable0[uChannel-1]);
ii ++;
MACvSetMISCFifo(dwIoBase, (WORD)(MISCFIFO_SYNDATA_IDX + ii), dwAL2230ChannelTable1[uChannel-1]);
break;
//{{ RobertYu: 20050104
// Need to check, PLLON need to be low for channel setting
case RF_AIROHA7230:
byInitCount = CB_AL7230_INIT_SEQ + 3; // Init Reg + Channel Reg (3)
bySleepCount = 0;
if (byInitCount > (MISCFIFO_SYNDATASIZE - bySleepCount)) {
return FALSE;
}
if (uChannel <= CB_MAX_CHANNEL_24G)
{
for (ii = 0; ii < CB_AL7230_INIT_SEQ; ii++ ) {
MACvSetMISCFifo(dwIoBase, (WORD)(MISCFIFO_SYNDATA_IDX + ii), dwAL7230InitTable[ii]);
}
}
else
{
for (ii = 0; ii < CB_AL7230_INIT_SEQ; ii++ ) {
MACvSetMISCFifo(dwIoBase, (WORD)(MISCFIFO_SYNDATA_IDX + ii), dwAL7230InitTableAMode[ii]);
}
}
MACvSetMISCFifo(dwIoBase, (WORD)(MISCFIFO_SYNDATA_IDX + ii), dwAL7230ChannelTable0[uChannel-1]);
ii ++;
MACvSetMISCFifo(dwIoBase, (WORD)(MISCFIFO_SYNDATA_IDX + ii), dwAL7230ChannelTable1[uChannel-1]);
ii ++;
MACvSetMISCFifo(dwIoBase, (WORD)(MISCFIFO_SYNDATA_IDX + ii), dwAL7230ChannelTable2[uChannel-1]);
break;
//}} RobertYu
case RF_NOTHING :
return TRUE;
break;
default:
return FALSE;
break;
}
MACvSetMISCFifo(dwIoBase, MISCFIFO_SYNINFO_IDX, (DWORD)MAKEWORD(bySleepCount, byInitCount));
return TRUE;
}
/*
* Description: Write WakeProgSyn
*
* Parameters:
* In:
* iobase - I/O base address
* uChannel - channel number
* bySleepCnt - SleepProgSyn count
*
* Return Value: None.
*
*/
bool RFvWriteWakeProgSyn(struct vnt_private *priv, unsigned char byRFType,
u16 uChannel)
{
void __iomem *iobase = priv->PortOffset;
int ii;
unsigned char byInitCount = 0;
unsigned char bySleepCount = 0;
VNSvOutPortW(iobase + MAC_REG_MISCFFNDEX, 0);
switch (byRFType) {
case RF_AIROHA:
case RF_AL2230S:
if (uChannel > CB_MAX_CHANNEL_24G)
return false;
/* Init Reg + Channel Reg (2) */
byInitCount = CB_AL2230_INIT_SEQ + 2;
bySleepCount = 0;
if (byInitCount > (MISCFIFO_SYNDATASIZE - bySleepCount))
return false;
for (ii = 0; ii < CB_AL2230_INIT_SEQ; ii++)
MACvSetMISCFifo(priv, (unsigned short)(MISCFIFO_SYNDATA_IDX + ii), dwAL2230InitTable[ii]);
MACvSetMISCFifo(priv, (unsigned short)(MISCFIFO_SYNDATA_IDX + ii), dwAL2230ChannelTable0[uChannel-1]);
ii++;
MACvSetMISCFifo(priv, (unsigned short)(MISCFIFO_SYNDATA_IDX + ii), dwAL2230ChannelTable1[uChannel-1]);
break;
/* Need to check, PLLON need to be low for channel setting */
case RF_AIROHA7230:
/* Init Reg + Channel Reg (3) */
byInitCount = CB_AL7230_INIT_SEQ + 3;
bySleepCount = 0;
if (byInitCount > (MISCFIFO_SYNDATASIZE - bySleepCount))
return false;
if (uChannel <= CB_MAX_CHANNEL_24G) {
for (ii = 0; ii < CB_AL7230_INIT_SEQ; ii++)
MACvSetMISCFifo(priv, (unsigned short)(MISCFIFO_SYNDATA_IDX + ii), dwAL7230InitTable[ii]);
} else {
for (ii = 0; ii < CB_AL7230_INIT_SEQ; ii++)
MACvSetMISCFifo(priv, (unsigned short)(MISCFIFO_SYNDATA_IDX + ii), dwAL7230InitTableAMode[ii]);
}
MACvSetMISCFifo(priv, (unsigned short)(MISCFIFO_SYNDATA_IDX + ii), dwAL7230ChannelTable0[uChannel-1]);
ii++;
MACvSetMISCFifo(priv, (unsigned short)(MISCFIFO_SYNDATA_IDX + ii), dwAL7230ChannelTable1[uChannel-1]);
ii++;
MACvSetMISCFifo(priv, (unsigned short)(MISCFIFO_SYNDATA_IDX + ii), dwAL7230ChannelTable2[uChannel-1]);
break;
case RF_NOTHING:
return true;
default:
return false;
}
MACvSetMISCFifo(priv, MISCFIFO_SYNINFO_IDX, (unsigned long)MAKEWORD(bySleepCount, byInitCount));
return true;
}
VOID GMACvInitialize(PSAdapterInfo pAdapter, DWORD dwIoBase, BYTE byRevId)
{
BYTE byTemp;
BYTE check;
/* clear sticky bits */
MACvClearStckDS(dwIoBase);
/* disable force PME-enable */
VNSvOutPortB(dwIoBase + MAC_REG_WOLCFG_CLR, WOLCFG_PMEOVR);
/* disable power-event config bit */
MACvPwrEvntDisable(dwIoBase);
/* clear power status */
VNSvOutPortW(dwIoBase + MAC_REG_WOLSR0_CLR, 0xFFFF);
/* do reset */
GMACbSoftwareReset(dwIoBase, byRevId);
/* for AUTOLD be effect, safe delay time */
PCAvDelayByIO(CB_DELAY_SOFT_RESET);
VNSvInPortB(dwIoBase + MAC_REG_JMPSR1, &check);
/* VNSvInPortB(pAdapter->dwIoBase+Gmac_Jumper_Strapping3, &check) */
/* if (!(check & JMPSR1_J_VEESEL))
GMACLoadVEE(dwIoBase);
else { */
if (check & JMPSR1_J_VEESEL) {
/* issue RELOAD in EECSR to reload eeprom */
MACvRegBitsOn(dwIoBase, MAC_REG_EECSR, EECSR_RELOAD);
/* wait until EEPROM loading complete */
while (TRUE) {
if (GMACbIsRegBitsOff(dwIoBase, MAC_REG_EECSR, EECSR_RELOAD))
break;
}
}
/* EEPROM reloaded will cause bit 0 in MAC_REG_CFGA turned on. */
/* it makes MAC receive magic packet automatically. So, driver turn it off. */
MACvRegBitsOff(dwIoBase, MAC_REG_CFGA, CFGA_PACPI);
/* set rx-FIFO/DMA threshold */
/* set rx threshold, 128 bytes */
/*GMACvSetRxThreshold(dwIoBase, 3);*/
/* set DMA length, 16 DWORDs = 64 bytes */
/*GMACvSetDmaLength(dwIoBase, 1);*/
/* suspend-well accept broadcast, multicast */
VNSvOutPortB(dwIoBase + MAC_REG_WOLCFG_SET, WOLCFG_SAM | WOLCFG_SAB);
/* back off algorithm use original IEEE standard */
MACvRegBitsOff(dwIoBase, MAC_REG_CFGB, CFGB_CRANDOM | CFGB_CAP | CFGB_MBA | CFGB_BAKOPT);
/* set packet filter */
/* receive directed and broadcast address */
GMACvSetPacketFilter(dwIoBase, PKT_TYPE_DIRECTED | PKT_TYPE_BROADCAST);
/* Eric */
#if defined(__USE_GMASK1__)
VNSvOutPortD(dwIoBase + MAC_REG_IMR, IMR_MASK_VALUE);
#else
/* Turn on GenIntMask1 */
VNSvOutPortB(dwIoBase + MAC_REG_CR3_SET, CR3_GINTMSK1);
#endif
#if 0
VNSvInPortB(dwIoBase, &byTemp);
printf("address0 = %x\n ", byTemp);
VNSvInPortB(dwIoBase + 1, &byTemp);
printf("address1 = %x\n ", byTemp);
VNSvInPortB(dwIoBase + 2, &byTemp);
printf("address2 = %x\n ", byTemp);
VNSvInPortB(dwIoBase + 3, &byTemp);
printf("address3 = %x\n ", byTemp);
VNSvInPortB(dwIoBase + 4, &byTemp);
printf("address4 = %x\n ", byTemp);
VNSvInPortB(dwIoBase + 5, &byTemp);
printf("address6 = %x\n ", byTemp);
#endif
/* Adaptive Interrupt: Init is disabled */
/* Select page to interrupt hold timer */
VNSvInPortB(dwIoBase + MAC_REG_CAMCR, &byTemp);
byTemp &= ~(CAMCR_PS0 | CAMCR_PS1);
VNSvOutPortB(dwIoBase + MAC_REG_CAMCR, byTemp);
/* Set Interrupt hold timer = 0 */
VNSvOutPortB(dwIoBase + MAC_REG_ISR_HOTMR, 0x00);
/* Select Page to Tx-sup threshold */
VNSvInPortB(dwIoBase + MAC_REG_CAMCR, &byTemp);
byTemp = (BYTE)((byTemp | CAMCR_PS0) & ~CAMCR_PS1);
VNSvOutPortB(dwIoBase + MAC_REG_CAMCR, byTemp);
/* Set Tx interrupt suppression threshold = 0 */
VNSvOutPortB(dwIoBase + MAC_REG_ISR_TSUPTHR, 0x00);
/* Select Page to Rx-sup threshold */
VNSvInPortB(dwIoBase + MAC_REG_CAMCR, &byTemp);
byTemp = (BYTE)((byTemp | CAMCR_PS1) & ~CAMCR_PS0);
VNSvOutPortB(dwIoBase + MAC_REG_CAMCR, byTemp);
/* Set Rx interrupt suppression threshold = 0 */
VNSvOutPortB(dwIoBase + MAC_REG_ISR_RSUPTHR, 0x00);
/* Select page to interrupt hold timer */
VNSvInPortB(dwIoBase + MAC_REG_CAMCR, &byTemp);
byTemp &= ~(CAMCR_PS0 | CAMCR_PS1);
VNSvOutPortB(dwIoBase + MAC_REG_CAMCR, byTemp);
/* enable MIICR_MAUTO */
GMACvEnableMiiAutoPoll(dwIoBase);
}
