/**Function*************************************************************
Synopsis [Starts the simulation manager.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
Sym_Man_t * Sym_ManStart( Abc_Ntk_t * pNtk, int fVerbose )
{
Sym_Man_t * p;
int i, v;
// start the manager
p = ALLOC( Sym_Man_t, 1 );
memset( p, 0, sizeof(Sym_Man_t) );
p->pNtk = pNtk;
p->vNodes = Abc_NtkDfs( pNtk, 0 );
p->nInputs = Abc_NtkCiNum(p->pNtk);
p->nOutputs = Abc_NtkCoNum(p->pNtk);
// internal simulation information
p->nSimWords = SIM_NUM_WORDS(p->nInputs);
p->vSim = Sim_UtilInfoAlloc( Abc_NtkObjNumMax(pNtk), p->nSimWords, 0 );
// symmetry info for each output
p->vMatrSymms = Vec_PtrStart( p->nOutputs );
p->vMatrNonSymms = Vec_PtrStart( p->nOutputs );
p->vPairsTotal = Vec_IntStart( p->nOutputs );
p->vPairsSym = Vec_IntStart( p->nOutputs );
p->vPairsNonSym = Vec_IntStart( p->nOutputs );
for ( i = 0; i < p->nOutputs; i++ )
{
p->vMatrSymms->pArray[i] = Extra_BitMatrixStart( p->nInputs );
p->vMatrNonSymms->pArray[i] = Extra_BitMatrixStart( p->nInputs );
}
// temporary patterns
p->uPatRand = ALLOC( unsigned, p->nSimWords );
p->uPatCol = ALLOC( unsigned, p->nSimWords );
p->uPatRow = ALLOC( unsigned, p->nSimWords );
p->vVarsU = Vec_IntStart( 100 );
p->vVarsV = Vec_IntStart( 100 );
// compute supports
p->vSuppFun = Sim_ComputeFunSupp( pNtk, fVerbose );
p->vSupports = Vec_VecStart( p->nOutputs );
for ( i = 0; i < p->nOutputs; i++ )
for ( v = 0; v < p->nInputs; v++ )
if ( Sim_SuppFunHasVar( p->vSuppFun, i, v ) )
Vec_VecPush( p->vSupports, i, (void *)v );
return p;
}
/**Function*************************************************************
Synopsis [Returns the array of constraint candidates.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
void Llb_ManComputeIndCase( Aig_Man_t * p, DdManager * dd, Vec_Int_t * vNodes )
{
Vec_Ptr_t * vBdds;
Aig_Obj_t * pObj;
DdNode * bFunc;
int i, Entry;
vBdds = Vec_PtrStart( Aig_ManObjNumMax(p) );
bFunc = Cudd_ReadOne(dd); Cudd_Ref( bFunc );
Vec_PtrWriteEntry( vBdds, Aig_ObjId(Aig_ManConst1(p)), bFunc );
Saig_ManForEachPi( p, pObj, i )
{
bFunc = Cudd_bddIthVar( dd, Aig_ManPiNum(p) + i ); Cudd_Ref( bFunc );
Vec_PtrWriteEntry( vBdds, Aig_ObjId(pObj), bFunc );
}
/**Function*************************************************************
Synopsis [Transforms sequential AIG into dual-rail miter.]
Description [Transforms sequential AIG into a miter encoding ternary
problem formulated as follows "none of the POs has a ternary value".
Interprets the first nDualPis as having ternary value. Sets flops
to have ternary intial value when fDualFfs is set to 1.]
SideEffects []
SeeAlso []
***********************************************************************/
Aig_Man_t * Saig_ManDupDual( Aig_Man_t * pAig, Vec_Int_t * vDcFlops, int nDualPis, int fDualFfs, int fMiterFfs, int fComplPo, int fCheckZero, int fCheckOne )
{
Vec_Ptr_t * vCopies;
Aig_Man_t * pAigNew;
Aig_Obj_t * pObj, * pTemp0, * pTemp1, * pTemp2, * pTemp3, * pCare, * pMiter;
int i;
assert( Saig_ManPoNum(pAig) > 0 );
assert( nDualPis >= 0 && nDualPis <= Saig_ManPiNum(pAig) );
assert( vDcFlops == NULL || Vec_IntSize(vDcFlops) == Aig_ManRegNum(pAig) );
vCopies = Vec_PtrStart( 2*Aig_ManObjNum(pAig) );
// start the new manager
pAigNew = Aig_ManStart( Aig_ManNodeNum(pAig) );
pAigNew->pName = Abc_UtilStrsav( pAig->pName );
// map the constant node
Saig_ObjSetDual( vCopies, 0, 0, Aig_ManConst0(pAigNew) );
Saig_ObjSetDual( vCopies, 0, 1, Aig_ManConst1(pAigNew) );
// create variables for PIs
Aig_ManForEachCi( pAig, pObj, i )
{
if ( i < nDualPis )
{
pTemp0 = Aig_ObjCreateCi( pAigNew );
pTemp1 = Aig_ObjCreateCi( pAigNew );
}
else if ( i < Saig_ManPiNum(pAig) )
{
pTemp1 = Aig_ObjCreateCi( pAigNew );
pTemp0 = Aig_Not( pTemp1 );
}
else
{
pTemp0 = Aig_ObjCreateCi( pAigNew );
pTemp1 = Aig_ObjCreateCi( pAigNew );
if ( vDcFlops )
pTemp0 = Aig_NotCond( pTemp0, !Vec_IntEntry(vDcFlops, i-Saig_ManPiNum(pAig)) );
else
pTemp0 = Aig_NotCond( pTemp0, !fDualFfs );
}
Saig_ObjSetDual( vCopies, Aig_ObjId(pObj), 0, Aig_And(pAigNew, pTemp0, Aig_Not(pTemp1)) );
Saig_ObjSetDual( vCopies, Aig_ObjId(pObj), 1, Aig_And(pAigNew, pTemp1, Aig_Not(pTemp0)) );
}
// create internal nodes
Aig_ManForEachNode( pAig, pObj, i )
{
Saig_ObjDualFanin( pAigNew, vCopies, pObj, 0, &pTemp0, &pTemp1 );
Saig_ObjDualFanin( pAigNew, vCopies, pObj, 1, &pTemp2, &pTemp3 );
Saig_ObjSetDual( vCopies, Aig_ObjId(pObj), 0, Aig_Or (pAigNew, pTemp0, pTemp2) );
Saig_ObjSetDual( vCopies, Aig_ObjId(pObj), 1, Aig_And(pAigNew, pTemp1, pTemp3) );
}
ABC_NAMESPACE_IMPL_START
////////////////////////////////////////////////////////////////////////
/// DECLARATIONS ///
////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////
/// FUNCTION DEFINITIONS ///
////////////////////////////////////////////////////////////////////////
/**Function*************************************************************
Synopsis [Allocates sequential AIG manager.]
Description [The manager contains all the data structures needed to
represent sequential AIG and compute stand-alone retiming as well as
the integrated mapping/retiming of the sequential AIG.]
SideEffects []
SeeAlso []
***********************************************************************/
Abc_Seq_t * Seq_Create( Abc_Ntk_t * pNtk )
{
Abc_Seq_t * p;
// start the manager
p = ALLOC( Abc_Seq_t, 1 );
memset( p, 0, sizeof(Abc_Seq_t) );
p->pNtk = pNtk;
p->nSize = 1000;
p->nMaxIters = 15;
p->pMmInits = Extra_MmFixedStart( sizeof(Seq_Lat_t) );
p->fEpsilon = (float)0.001;
// create internal data structures
p->vNums = Vec_IntStart( 2 * p->nSize );
p->vInits = Vec_PtrStart( 2 * p->nSize );
p->vLValues = Vec_IntStart( p->nSize );
p->vLags = Vec_StrStart( p->nSize );
p->vLValuesN = Vec_IntStart( p->nSize );
p->vAFlows = Vec_IntStart( p->nSize );
p->vLagsN = Vec_StrStart( p->nSize );
p->vUses = Vec_StrStart( p->nSize );
return p;
}
/**Fnction*************************************************************
Synopsis [Constructs AIG in ABC from the manager.]
Description [The ABC network is started, as well as the array vCopy,
which will map the new ID of each object in the BBLIF manager into
the ponter ot the corresponding AIG object in the ABC. For each internal
node in a topological oder the AIG representation is created
by factoring the SOP representation of the BBLIF object. Finally,
the CO objects are created, and the dummy names are assigned because
ABC requires each CI/CO to have a name.]
SideEffects []
SeeAlso []
***********************************************************************/
Abc_Ntk_t * Bbl_ManToAig( Bbl_Man_t * p )
{
extern int Bbl_ManFncSize( Bbl_Man_t * p );
extern int Bbl_ObjFncHandle( Bbl_Obj_t * p );
extern Abc_Obj_t * Dec_GraphToAig( Abc_Ntk_t * pNtk, Dec_Graph_t * pFForm, Vec_Ptr_t * vFaninAigs );
int fVerbose = 0;
Abc_Ntk_t * pNtk;
Abc_Obj_t * pObjNew;
Bbl_Obj_t * pObj, * pFanin;
Vec_Ptr_t * vCopy, * vNodes, * vFaninAigs;
Dec_Graph_t ** pFForms;
int i;
clock_t clk;
clk = clock();
// map SOP handles into factored forms
pFForms = ABC_CALLOC( Dec_Graph_t *, Bbl_ManFncSize(p) );
Bbl_ManForEachObj( p, pObj )
if ( pFForms[Bbl_ObjFncHandle(pObj)] == NULL )
pFForms[Bbl_ObjFncHandle(pObj)] = Dec_Factor( Bbl_ObjSop(p, pObj) );
if ( fVerbose )
ABC_PRT( "Fct", clock() - clk );
// start the network
pNtk = Abc_NtkAlloc( ABC_NTK_STRASH, ABC_FUNC_AIG, 1 );
pNtk->pName = Extra_UtilStrsav( Bbl_ManName(p) );
vCopy = Vec_PtrStart( 1000 );
// create CIs
Bbl_ManForEachObj( p, pObj )
{
if ( !Bbl_ObjIsInput(pObj) )
continue;
Vec_PtrSetEntry( vCopy, Bbl_ObjId(pObj), Abc_NtkCreatePi(pNtk) );
}
clk = clock();
// create internal nodes
vNodes = Bbl_ManDfs( p );
vFaninAigs = Vec_PtrAlloc( 100 );
Vec_PtrForEachEntry( Bbl_Obj_t *, vNodes, pObj, i )
{
// collect fanin AIGs
Vec_PtrClear( vFaninAigs );
Bbl_ObjForEachFanin( pObj, pFanin )
Vec_PtrPush( vFaninAigs, Vec_PtrEntry( vCopy, Bbl_ObjId(pFanin) ) );
// create the new node
pObjNew = Dec_GraphToAig( pNtk, pFForms[Bbl_ObjFncHandle(pObj)], vFaninAigs );
Vec_PtrSetEntry( vCopy, Bbl_ObjId(pObj), pObjNew );
}
Vec_Ptr_t * Cba_ManCollectGateNamesByTruth( Mio_Library_t * pLib )
{
static word uTruths6[3] = {
ABC_CONST(0xAAAAAAAAAAAAAAAA),
ABC_CONST(0xCCCCCCCCCCCCCCCC),
ABC_CONST(0xF0F0F0F0F0F0F0F0),
};
Vec_Ptr_t * vGateNames = Vec_PtrStart( PTR_GATE_UNKNOWN );
Cba_ManCollectGateNameOne( pLib, PTR_GATE_C0, 0, vGateNames );
Cba_ManCollectGateNameOne( pLib, PTR_GATE_C1, ~(word)0, vGateNames );
Cba_ManCollectGateNameOne( pLib, PTR_GATE_BUF, uTruths6[0], vGateNames );
Cba_ManCollectGateNameOne( pLib, PTR_GATE_INV, ~uTruths6[0], vGateNames );
Cba_ManCollectGateNameOne( pLib, PTR_GATE_AND, (uTruths6[0] & uTruths6[1]), vGateNames );
Cba_ManCollectGateNameOne( pLib, PTR_GATE_NAND, ~(uTruths6[0] & uTruths6[1]), vGateNames );
Cba_ManCollectGateNameOne( pLib, PTR_GATE_OR, (uTruths6[0] | uTruths6[1]), vGateNames );
Cba_ManCollectGateNameOne( pLib, PTR_GATE_NOR, ~(uTruths6[0] | uTruths6[1]), vGateNames );
Cba_ManCollectGateNameOne( pLib, PTR_GATE_XOR, (uTruths6[0] ^ uTruths6[1]), vGateNames );
Cba_ManCollectGateNameOne( pLib, PTR_GATE_XNOR, ~(uTruths6[0] ^ uTruths6[1]), vGateNames );
return vGateNames;
}
/**Function*************************************************************
Synopsis []
Description []
SideEffects []
SeeAlso []
***********************************************************************/
Nwk_Man_t * Nwk_ManFromIf( If_Man_t * pIfMan, Aig_Man_t * p, Vec_Ptr_t * vAigToIf )
{
Vec_Ptr_t * vIfToAig;
Nwk_Man_t * pNtk;
Nwk_Obj_t * pObjNew;
Aig_Obj_t * pObj, * pObjRepr;
If_Obj_t * pIfObj;
If_Cut_t * pCutBest;
int i, k, nLeaves, * ppLeaves;
assert( Aig_ManCiNum(p) == If_ManCiNum(pIfMan) );
assert( Aig_ManCoNum(p) == If_ManCoNum(pIfMan) );
assert( Aig_ManNodeNum(p) == If_ManAndNum(pIfMan) );
Aig_ManCleanData( p );
If_ManCleanCutData( pIfMan );
// create mapping of IF to AIG
vIfToAig = Vec_PtrStart( If_ManObjNum(pIfMan) );
Aig_ManForEachObj( p, pObj, i )
{
pIfObj = (If_Obj_t *)Vec_PtrEntry( vAigToIf, i );
Vec_PtrWriteEntry( vIfToAig, pIfObj->Id, pObj );
}
/**Function*************************************************************
Synopsis [Creates a new Ntk.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
Abc_Ntk_t * Abc_NtkAlloc( Abc_NtkType_t Type, Abc_NtkFunc_t Func, int fUseMemMan )
{
Abc_Ntk_t * pNtk;
pNtk = ALLOC( Abc_Ntk_t, 1 );
memset( pNtk, 0, sizeof(Abc_Ntk_t) );
pNtk->ntkType = Type;
pNtk->ntkFunc = Func;
// start the object storage
pNtk->vObjs = Vec_PtrAlloc( 100 );
pNtk->vAsserts = Vec_PtrAlloc( 100 );
pNtk->vPios = Vec_PtrAlloc( 100 );
pNtk->vPis = Vec_PtrAlloc( 100 );
pNtk->vPos = Vec_PtrAlloc( 100 );
pNtk->vCis = Vec_PtrAlloc( 100 );
pNtk->vCos = Vec_PtrAlloc( 100 );
pNtk->vBoxes = Vec_PtrAlloc( 100 );
// start the memory managers
pNtk->pMmObj = fUseMemMan? Extra_MmFixedStart( sizeof(Abc_Obj_t) ) : NULL;
pNtk->pMmStep = fUseMemMan? Extra_MmStepStart( ABC_NUM_STEPS ) : NULL;
// get ready to assign the first Obj ID
pNtk->nTravIds = 1;
// start the functionality manager
if ( Abc_NtkIsStrash(pNtk) )
pNtk->pManFunc = Abc_AigAlloc( pNtk );
else if ( Abc_NtkHasSop(pNtk) || Abc_NtkHasBlifMv(pNtk) )
pNtk->pManFunc = Extra_MmFlexStart();
else if ( Abc_NtkHasBdd(pNtk) )
pNtk->pManFunc = Cudd_Init( 20, 0, CUDD_UNIQUE_SLOTS, CUDD_CACHE_SLOTS, 0 );
else if ( Abc_NtkHasAig(pNtk) )
pNtk->pManFunc = Hop_ManStart();
else if ( Abc_NtkHasMapping(pNtk) )
pNtk->pManFunc = Abc_FrameReadLibGen();
else if ( !Abc_NtkHasBlackbox(pNtk) )
assert( 0 );
// name manager
pNtk->pManName = Nm_ManCreate( 200 );
// attribute manager
pNtk->vAttrs = Vec_PtrStart( VEC_ATTR_TOTAL_NUM );
return pNtk;
}
/**Function*************************************************************
Synopsis [Derive BDD of the characteristic function.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
DdNode * Abc_ResBuildBdd( Abc_Ntk_t * pNtk, DdManager * dd )
{
Vec_Ptr_t * vNodes, * vBdds, * vLocals;
Abc_Obj_t * pObj, * pFanin;
DdNode * bFunc, * bPart, * bTemp, * bVar;
int i, k;
assert( Abc_NtkIsSopLogic(pNtk) );
assert( Abc_NtkCoNum(pNtk) <= 3 );
vBdds = Vec_PtrStart( Abc_NtkObjNumMax(pNtk) );
Abc_NtkForEachCi( pNtk, pObj, i )
Vec_PtrWriteEntry( vBdds, Abc_ObjId(pObj), Cudd_bddIthVar(dd, i) );
// create internal node BDDs
vNodes = Abc_NtkDfs( pNtk, 0 );
vLocals = Vec_PtrAlloc( 6 );
Vec_PtrForEachEntry( Abc_Obj_t *, vNodes, pObj, i )
{
if ( Abc_ObjFaninNum(pObj) == 0 )
{
bFunc = Cudd_NotCond( Cudd_ReadOne(dd), Abc_SopIsConst0((char *)pObj->pData) ); Cudd_Ref( bFunc );
Vec_PtrWriteEntry( vBdds, Abc_ObjId(pObj), bFunc );
continue;
}
Vec_PtrClear( vLocals );
Abc_ObjForEachFanin( pObj, pFanin, k )
Vec_PtrPush( vLocals, Vec_PtrEntry(vBdds, Abc_ObjId(pFanin)) );
bFunc = Abc_ConvertSopToBdd( dd, (char *)pObj->pData, (DdNode **)Vec_PtrArray(vLocals) ); Cudd_Ref( bFunc );
Vec_PtrWriteEntry( vBdds, Abc_ObjId(pObj), bFunc );
}
Vec_PtrFree( vLocals );
// create char function
bFunc = Cudd_ReadOne( dd ); Cudd_Ref( bFunc );
Abc_NtkForEachCo( pNtk, pObj, i )
{
bVar = Cudd_bddIthVar( dd, i + Abc_NtkCiNum(pNtk) );
bTemp = (DdNode *)Vec_PtrEntry( vBdds, Abc_ObjFaninId0(pObj) );
bPart = Cudd_bddXnor( dd, bTemp, bVar ); Cudd_Ref( bPart );
bFunc = Cudd_bddAnd( dd, bTemp = bFunc, bPart ); Cudd_Ref( bFunc );
Cudd_RecursiveDeref( dd, bTemp );
Cudd_RecursiveDeref( dd, bPart );
}
/**Function*************************************************************
Synopsis [Constructs the ABC network after mapping.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
Abc_Ntk_t * Ivy_ManFpgaToAbc( Abc_Ntk_t * pNtk, Ivy_Man_t * pMan )
{
Abc_Ntk_t * pNtkNew;
Abc_Obj_t * pObjAbc, * pObj;
Ivy_Obj_t * pObjIvy;
Vec_Int_t * vNodes;
int i;
// start mapping from Ivy into Abc
pMan->pCopy = Vec_PtrStart( Ivy_ManObjIdMax(pMan) + 1 );
// start the new ABC network
pNtkNew = Abc_NtkStartFrom( pNtk, ABC_NTK_LOGIC, ABC_FUNC_AIG );
// transfer the pointers to the basic nodes
Abc_ObjSetIvy2Abc( pMan, Ivy_ManConst1(pMan)->Id, Abc_NtkCreateNodeConst1(pNtkNew) );
Abc_NtkForEachCi( pNtkNew, pObjAbc, i )
Abc_ObjSetIvy2Abc( pMan, Ivy_ManPi(pMan, i)->Id, pObjAbc );
// recursively construct the network
vNodes = Vec_IntAlloc( 100 );
Ivy_ManForEachPo( pMan, pObjIvy, i )
{
// get the new ABC node corresponding to the old fanin of the PO in IVY
pObjAbc = Ivy_ManToAbcFast_rec( pNtkNew, pMan, Ivy_ObjFanin0(pObjIvy), vNodes );
// consider the case of complemented fanin of the PO
if ( Ivy_ObjFaninC0(pObjIvy) ) // complement
{
if ( Abc_ObjIsCi(pObjAbc) )
pObjAbc = Abc_NtkCreateNodeInv( pNtkNew, pObjAbc );
else
{
// clone the node
pObj = Abc_NtkCloneObj( pObjAbc );
// set complemented functions
pObj->pData = Hop_Not( pObjAbc->pData );
// return the new node
pObjAbc = pObj;
}
}
Abc_ObjAddFanin( Abc_NtkCo(pNtkNew, i), pObjAbc );
}
ABC_NAMESPACE_IMPL_START
////////////////////////////////////////////////////////////////////////
/// DECLARATIONS ///
////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////
/// FUNCTION DEFINITIONS ///
////////////////////////////////////////////////////////////////////////
/**Function*************************************************************
Synopsis [Inserts the given mapping into the netlist.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
Ntl_Man_t * Ntl_ManInsertMapping( Ntl_Man_t * p, Vec_Ptr_t * vMapping, Aig_Man_t * pAig )
{
char Buffer[1000];
Vec_Ptr_t * vCopies;
Vec_Int_t * vCover;
Ntl_Mod_t * pRoot;
Ntl_Obj_t * pNode;
Ntl_Net_t * pNet, * pNetCo;
Ntl_Lut_t * pLut;
int i, k, nDigits;
assert( Vec_PtrSize(p->vCis) == Aig_ManPiNum(pAig) );
assert( Vec_PtrSize(p->vCos) == Aig_ManPoNum(pAig) );
p = Ntl_ManStartFrom( p );
pRoot = Ntl_ManRootModel( p );
assert( Ntl_ModelNodeNum(pRoot) == 0 );
// map the AIG back onto the design
Ntl_ManForEachCiNet( p, pNet, i )
pNet->pCopy = Aig_ManPi( pAig, i );
// start mapping of AIG nodes into their copies
vCopies = Vec_PtrStart( Aig_ManObjNumMax(pAig) );
Ntl_ManForEachCiNet( p, pNet, i )
Vec_PtrWriteEntry( vCopies, ((Aig_Obj_t *)pNet->pCopy)->Id, pNet );
// create a new node for each LUT
vCover = Vec_IntAlloc( 1 << 16 );
nDigits = Aig_Base10Log( Vec_PtrSize(vMapping) );
Vec_PtrForEachEntry( Ntl_Lut_t *, vMapping, pLut, i )
{
pNode = Ntl_ModelCreateNode( pRoot, pLut->nFanins );
pNode->pSop = Kit_PlaFromTruth( p->pMemSops, pLut->pTruth, pLut->nFanins, vCover );
if ( !Kit_TruthIsConst0(pLut->pTruth, pLut->nFanins) && !Kit_TruthIsConst1(pLut->pTruth, pLut->nFanins) )
{
for ( k = 0; k < pLut->nFanins; k++ )
{
pNet = (Ntl_Net_t *)Vec_PtrEntry( vCopies, pLut->pFanins[k] );
if ( pNet == NULL )
{
printf( "Ntl_ManInsert(): Internal error: Net not found.\n" );
return 0;
}
Ntl_ObjSetFanin( pNode, pNet, k );
}
}
else
pNode->nFanins = 0;
sprintf( Buffer, "lut%0*d", nDigits, i );
if ( (pNet = Ntl_ModelFindNet( pRoot, Buffer )) )
{
printf( "Ntl_ManInsert(): Internal error: Intermediate net name is not unique.\n" );
return 0;
}
pNet = Ntl_ModelFindOrCreateNet( pRoot, Buffer );
if ( !Ntl_ModelSetNetDriver( pNode, pNet ) )
{
printf( "Ntl_ManInsert(): Internal error: Net has more than one fanin.\n" );
return 0;
}
Vec_PtrWriteEntry( vCopies, pLut->Id, pNet );
}
ABC_NAMESPACE_IMPL_START
////////////////////////////////////////////////////////////////////////
/// DECLARATIONS ///
////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////
/// FUNCTION DEFINITIONS ///
////////////////////////////////////////////////////////////////////////
/**Function*************************************************************
Synopsis [Starts the simulation manager.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
Sym_Man_t * Sym_ManStart( Abc_Ntk_t * pNtk, int fVerbose )
{
Sym_Man_t * p;
int i, v;
// start the manager
p = ABC_ALLOC( Sym_Man_t, 1 );
memset( p, 0, sizeof(Sym_Man_t) );
p->pNtk = pNtk;
p->vNodes = Abc_NtkDfs( pNtk, 0 );
p->nInputs = Abc_NtkCiNum(p->pNtk);
p->nOutputs = Abc_NtkCoNum(p->pNtk);
// internal simulation information
p->nSimWords = SIM_NUM_WORDS(p->nInputs);
p->vSim = Sim_UtilInfoAlloc( Abc_NtkObjNumMax(pNtk), p->nSimWords, 0 );
// symmetry info for each output
p->vMatrSymms = Vec_PtrStart( p->nOutputs );
p->vMatrNonSymms = Vec_PtrStart( p->nOutputs );
p->vPairsTotal = Vec_IntStart( p->nOutputs );
p->vPairsSym = Vec_IntStart( p->nOutputs );
p->vPairsNonSym = Vec_IntStart( p->nOutputs );
for ( i = 0; i < p->nOutputs; i++ )
{
p->vMatrSymms->pArray[i] = Extra_BitMatrixStart( p->nInputs );
p->vMatrNonSymms->pArray[i] = Extra_BitMatrixStart( p->nInputs );
}
// temporary patterns
p->uPatRand = ABC_ALLOC( unsigned, p->nSimWords );
p->uPatCol = ABC_ALLOC( unsigned, p->nSimWords );
p->uPatRow = ABC_ALLOC( unsigned, p->nSimWords );
p->vVarsU = Vec_IntStart( 100 );
p->vVarsV = Vec_IntStart( 100 );
// compute supports
p->vSuppFun = Sim_ComputeFunSupp( pNtk, fVerbose );
p->vSupports = Vec_VecStart( p->nOutputs );
for ( i = 0; i < p->nOutputs; i++ )
for ( v = 0; v < p->nInputs; v++ )
if ( Sim_SuppFunHasVar( p->vSuppFun, i, v ) )
Vec_VecPush( p->vSupports, i, (void *)(ABC_PTRUINT_T)v );
return p;
}
ABC_NAMESPACE_IMPL_START
// For description of Binary BLIF format, refer to "abc/src/aig/bbl/bblif.h"
////////////////////////////////////////////////////////////////////////
/// DECLARATIONS ///
////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////
/// FUNCTION DEFINITIONS ///
////////////////////////////////////////////////////////////////////////
/**Fnction*************************************************************
Synopsis [Constructs ABC network from the manager.]
Description [The ABC network is started, as well as the array vCopy,
which will map the new ID of each object in the BBLIF manager into
the ponter ot the corresponding object in the ABC. For each internal
node, determined by Bbl_ObjIsLut(), the SOP representation is created
by retrieving the SOP representation of the BBLIF object. Finally,
the objects are connected using fanin/fanout creation, and the dummy
names are assigned because ABC requires each CI/CO to have a name.]
SideEffects []
SeeAlso []
***********************************************************************/
Abc_Ntk_t * Bbl_ManToAbc( Bbl_Man_t * p )
{
Abc_Ntk_t * pNtk;
Abc_Obj_t * pObjNew;
Bbl_Obj_t * pObj, * pFanin;
Vec_Ptr_t * vCopy;
// start the network
pNtk = Abc_NtkAlloc( ABC_NTK_LOGIC, ABC_FUNC_SOP, 1 );
pNtk->pName = Extra_UtilStrsav( Bbl_ManName(p) );
// create objects
vCopy = Vec_PtrStart( 1000 );
Bbl_ManForEachObj( p, pObj )
{
if ( Bbl_ObjIsInput(pObj) )
pObjNew = Abc_NtkCreatePi( pNtk );
else if ( Bbl_ObjIsOutput(pObj) )
pObjNew = Abc_NtkCreatePo( pNtk );
else if ( Bbl_ObjIsLut(pObj) )
pObjNew = Abc_NtkCreateNode( pNtk );
else assert( 0 );
if ( Bbl_ObjIsLut(pObj) )
pObjNew->pData = Abc_SopRegister( (Mem_Flex_t *)pNtk->pManFunc, Bbl_ObjSop(p, pObj) );
Vec_PtrSetEntry( vCopy, Bbl_ObjId(pObj), pObjNew );
}
// connect objects
Bbl_ManForEachObj( p, pObj )
Bbl_ObjForEachFanin( pObj, pFanin )
Abc_ObjAddFanin( (Abc_Obj_t *)Vec_PtrEntry(vCopy, Bbl_ObjId(pObj)), (Abc_Obj_t *)Vec_PtrEntry(vCopy, Bbl_ObjId(pFanin)) );
// finalize
Vec_PtrFree( vCopy );
Abc_NtkAddDummyPiNames( pNtk );
Abc_NtkAddDummyPoNames( pNtk );
if ( !Abc_NtkCheck( pNtk ) )
printf( "Bbl_ManToAbc(): Network check has failed.\n" );
return pNtk;
}
