//! Target power has been externally cycled. Holds BKPT/BKGD low while Vdd rises //! //! @return //! \ref BDM_RC_OK => Success \n //! \ref BDM_RC_VDD_NOT_PRESENT => various errors // U8 bdmCF_powerOnReset(void) { U8 rc = 0; #if (HW_CAPABILITY&CAP_VDDSENSE) bdmcf_interfaceIdle(); // Make sure BDM interface is idle BKPT_LOW(); // Wait for Vdd to rise within 50% of 3V and RESET to return high // RESET rise may be delayed by target POR WAIT_WITH_TIMEOUT_MS( 250 /* ms */, (bdm_targetVddMeasure()>75)&& (!bdm_option.useResetSignal)||RESET_IS_HIGH); // Let signals settle & CPU to finish reset (with BKGD held low) WAIT_MS(BKGD_WAITus); if (bdm_targetVddMeasure()<=70) // Vpp didn't turn on! rc = BDM_RC_VDD_NOT_PRESENT; if (bdm_option.useResetSignal && (!RESET_IS_HIGH)) // RESET didn't rise rc = BDM_RC_RESET_TIMEOUT_RISE; bdmcf_interfaceIdle(); // Make sure BDM interface is idle (BKGD now high) // Let signals settle WAIT_MS(RESET_SETTLEms); cable_status.reset = RESET_DETECTED; // Record the fact that reset was asserted #endif // (HW_CAPABILITY&CAP_VDDSENSE) return(rc); }
void init() { // In case disabled by boot-loader __enable_irq(); initPorts(); initTimers(); bdm_interfaceOff(); initUSB(); #ifdef VDD_ON_INITIALLY // For compatibility with original board s/w // The board is powered when initially plugged in #if (VDD_ON_INITIALLY == 3) bdm_option.targetVdd = BDM_TARGET_VDD_3V3; #elif (VDD_ON_INITIALLY == 5) bdm_option.targetVdd = BDM_TARGET_VDD_5; #else bdm_option.targetVdd = BDM_TARGET_VDD_OFF; #endif bdm_setTargetVdd(); RESET_LOW(); WAIT_MS(100); RESET_3STATE(); #endif }
//write a value to kbc without resending int write_to_kbc_no_resend(port_t port,unsigned long value, unsigned char read_response) { int attempts = 0; unsigned long stat; unsigned long response=0; while(1) { if(attempts >= MAX_ATTEMPTS){ printf("write_to_kbc_no_resend() failed, max attempts reached: %d\n", attempts); return -1; } if(sys_inb(STAT_REG, &stat)!= OK){ printf("write_to_kbc_no_resend() failed, failure reading status\n"); return -1; } if( (stat & IN_BUF_STATUS) == 0 ) { if(sys_outb(port, value) != OK){ printf("write_to_kbc_no_resend() failed, failure writing value 0x%x, at port 0x%x\n", value, port); return -1; } if(read_response) read_kbd_value(&response); break; } attempts++; WAIT_MS(WAIT_TIME); } return response; }
//! Cycle power to target //! //! @param mode //! - \ref RESET_SPECIAL => Power on in special mode, //! - \ref RESET_NORMAL => Power on in normal mode //! //! BKGD/BKPT is held low when power is re-applied to start //! target with BDM active if RESET_SPECIAL //! //! @return //! \ref BDM_RC_OK => No error \n //! \ref BDM_RC_VDD_WRONG_MODE => Target Vdd not controlled by BDM interface \n //! \ref BDM_RC_VDD_NOT_REMOVED => Target Vdd failed to fall \n //! \ref BDM_RC_VDD_NOT_PRESENT => Target Vdd failed to rise \n //! \ref BDM_RC_RESET_TIMEOUT_RISE => RESET signal failed to rise \n //! uint8_t bdm_cycleTargetVdd(uint8_t mode) { uint8_t rc; // This may take a while setBDMBusy(); rc = bdm_cycleTargetVddOff(); if (rc != BDM_RC_OK) { return rc; } WAIT_MS(1000); rc = bdm_cycleTargetVddOn(mode); return rc; }
static bool before(atf_suite * suite) { if ( ! udf_put(LUA_FILE) ) { error("failure while uploading: %s", LUA_FILE); return false; } WAIT_MS(100); if ( ! udf_exists(LUA_FILE) ) { error("lua file does not exist: %s", LUA_FILE); return false; } return true; }
bool udf_remove(const char * filename) { as_error err; as_error_reset(&err); as_string filename_string; const char * base = as_basename(&filename_string, filename); if ( aerospike_udf_remove(as, &err, NULL, base) != AEROSPIKE_OK ) { error("error caused by aerospike_udf_remove(): (%d) %s @ %s[%s:%d]", err.code, err.message, err.func, err.file, err.line); } as_string_destroy(&filename_string); WAIT_MS(100); return err.code == AEROSPIKE_OK; }
static void testMode() { // In case disabled by boot-loader __enable_irq(); initPorts(); initTimers(); bdm_interfaceOff(); initUSB(); ledEnable(); testEnable(); bootInputEnable(); for(;;) { WAIT_MS(100); ledToggle(); testToggle(); if (bootInputActive() == 0) { reboot(); } } }
int read_mouse_value(unsigned long* data) { int attempts = 0; unsigned long stat; while( 1 ) { if(attempts >= MAX_ATTEMPTS) return 1; if(sys_inb(STAT_REG, &stat)!= OK) return 1; if( stat & OUT_BUF_STATUS ) { if(sys_inb(OUT_BUF, data)!= OK) return 1; if ( (stat &(PARITY_ERROR | TIMEOUT)) == 0 )//no error { return 0; } } attempts++;//not ready WAIT_MS(WAIT_TIME); } }
uint8_t m0110_recv(void) { uint8_t data = 0; m0110_error = 0; WAIT_MS(clock_lo, 250, 1); // keyboard may block long time for (uint8_t i = 0; i < 8; i++) { data <<= 1; WAIT_US(clock_lo, 200, 2); WAIT_US(clock_hi, 200, 3); if (data_in()) { data |= 1; } } idle(); return data; ERROR: print("m0110_recv err: "); phex(m0110_error); print("\n"); _delay_ms(500); idle(); return 0xFF; }
uint8_t m0110_send(uint8_t data) { m0110_error = 0; request(); WAIT_MS(clock_lo, 250, 1); // keyboard may block long time for (uint8_t bit = 0x80; bit; bit >>= 1) { WAIT_US(clock_lo, 250, 3); if (data&bit) { data_hi(); } else { data_lo(); } WAIT_US(clock_hi, 200, 4); } _delay_us(100); // hold last bit for 80us idle(); return 1; ERROR: print("m0110_send err: "); phex(m0110_error); print("\n"); _delay_ms(500); idle(); return 0; }
//! Cycle power ON to target //! //! @param mode //! - \ref RESET_SPECIAL => Power on in special mode, //! - \ref RESET_NORMAL => Power on in normal mode //! //! BKGD/BKPT is held low when power is re-applied to start //! target with BDM active if RESET_SPECIAL //! //! @return //! \ref BDM_RC_OK => Target Vdd confirmed on target \n //! \ref BDM_RC_VDD_WRONG_MODE => Target Vdd not controlled by BDM interface \n //! \ref BDM_RC_VDD_NOT_PRESENT => Target Vdd failed to rise \n //! \ref BDM_RC_RESET_TIMEOUT_RISE => RESET signal failed to rise \n //! \ref BDM_RC_BKGD_TIMEOUT => BKGD signal failed to rise //! uint8_t bdm_cycleTargetVddOn(uint8_t mode) { uint8_t rc = BDM_RC_OK; mode &= RESET_MODE_MASK; #if (HW_CAPABILITY&CAP_VDDCONTROL) switch(cable_status.target_type) { #if (HW_CAPABILITY&CAP_CFVx_HW) case T_CFVx: bdmcf_interfaceIdle(); // Make sure BDM interface is idle if (mode == RESET_SPECIAL) BKPT_LOW(); break; #endif #if (HW_CAPABILITY&CAP_BDM) case T_HC12: case T_HCS08: case T_RS08: case T_CFV1: bdmHCS_interfaceIdle(); // Make sure BDM interface is idle if (mode == RESET_SPECIAL) { BDM_LOW(); // BKGD pin=L } break; #endif #if (HW_CAPABILITY&CAP_JTAG_HW) case T_JTAG: case T_MC56F80xx: case T_ARM_JTAG: jtag_interfaceIdle(); // Make sure BDM interface is idle #endif break; default: swd_interfaceIdle(); break; } #if (DEBUG&CYCLE_DEBUG) DEBUG_PIN = 0; DEBUG_PIN = 1; DEBUG_PIN = 0; DEBUG_PIN = 1; #endif // (DEBUG&CYCLE_DEBUG) // Power on with TargetVdd monitoring off rc = bdm_setTargetVdd(); if (rc != BDM_RC_OK) // No target Vdd goto cleanUp; #if (DEBUG&CYCLE_DEBUG) DEBUG_PIN = 1; DEBUG_PIN = 0; #endif // (DEBUG&CYCLE_DEBUG) #if (HW_CAPABILITY&CAP_RST_IN) // RESET rise may be delayed by target POR if (bdm_option.useResetSignal) { WAIT_WITH_TIMEOUT_S( 2 /* s */, (RESET_IN!=0) ); } #endif #if (DEBUG&CYCLE_DEBUG) DEBUG_PIN = 0; DEBUG_PIN = 1; #endif // (DEBUG&CYCLE_DEBUG) // Let signals settle & CPU to finish reset (with BKGD held low) WAIT_US(BKGD_WAITus); #if (HW_CAPABILITY&CAP_RST_IN) if (bdm_option.useResetSignal && (RESET_IN==0)) { // RESET didn't rise rc = BDM_RC_RESET_TIMEOUT_RISE; goto cleanUp; } #endif //(HW_CAPABILITY&CAP_RST_IO) #if (DEBUG&CYCLE_DEBUG) DEBUG_PIN = 1; DEBUG_PIN = 0; #endif // (DEBUG&CYCLE_DEBUG) #if (HW_CAPABILITY&CAP_CFVx_HW) if (cable_status.target_type == T_CFVx) bdmcf_interfaceIdle(); // Release BKPT etc else #endif #if (HW_CAPABILITY&CAP_BDM) bdmHCS_interfaceIdle(); // Release BKGD #endif // Let processor start up WAIT_MS(RESET_RECOVERYms); #if 0 // Removed - some targets may be holding BKGD low (e.g. used as port pin) // This situation is handled elsewhere (requires power cycle) if (BDM_IN==0) { // BKGD didn't rise! rc = BDM_RC_BKGD_TIMEOUT; goto cleanUp; } #endif // 0 cable_status.reset = RESET_DETECTED; // Cycling the power should have reset it! cleanUp: #if (HW_CAPABILITY&CAP_CFVx_HW) if (cable_status.target_type == T_CFVx) bdmcf_interfaceIdle(); // Release BKPT etc else #endif #if (HW_CAPABILITY&CAP_BDM) bdmHCS_interfaceIdle(); // Release BKGD #endif WAIT_MS( 250 /* ms */); // EnableInterrupts; #endif // CAP_VDDCONTROL (void)bdm_checkTargetVdd(); // Update Target Vdd LED & power status return(rc); }