示例#1
0
//!  Cycle power OFF to target
//!
//!  @return
//!   \ref BDM_RC_OK                => No error  \n
//!   \ref BDM_RC_VDD_WRONG_MODE    => Target Vdd not controlled by BDM interface \n
//!   \ref BDM_RC_VDD_NOT_REMOVED   => Target Vdd failed to fall \n
//!
uint8_t bdm_cycleTargetVddOff(void) {
uint8_t rc = BDM_RC_OK;

#if (HW_CAPABILITY&CAP_VDDCONTROL)

   (void)bdm_checkTargetVdd();

   if (bdm_option.targetVdd == BDM_TARGET_VDD_OFF)
      return BDM_RC_VDD_WRONG_MODE;

#if (HW_CAPABILITY&CAP_CFVx_HW)
   if  (cable_status.target_type == T_CFVx)
      bdmcf_interfaceIdle();  // Make sure BDM interface is idle
   else
#endif 
   {
#if (HW_CAPABILITY&CAP_BDM)    	  
	  bdmHCS_interfaceIdle();  // Make sure BDM interface is idle
#endif
   }
#if (DEBUG&CYCLE_DEBUG)
   DEBUG_PIN     = 0;
   DEBUG_PIN     = 1;
#endif

   // Power off & wait for Vdd to fall to ~5%
   VDD_OFF();
   WAIT_WITH_TIMEOUT_S( 5 /* s */, (bdm_targetVddMeasure()<10) );

#if (DEBUG&CYCLE_DEBUG)
   DEBUG_PIN   = 1;
   DEBUG_PIN   = 0;
#endif

   if (bdm_targetVddMeasure()>=15) // Vdd didn't turn off!
      rc = BDM_RC_VDD_NOT_REMOVED;

#if (DEBUG&CYCLE_DEBUG)
   DEBUG_PIN     = 0;
   DEBUG_PIN     = 1;
#endif

   (void)bdm_checkTargetVdd(); // Update Target Vdd LED

   // Wait a while with power off
   WAIT_US(RESET_SETTLEms);

   // Clear Vdd monitoring interrupt
#if (HW_CAPABILITY&CAP_VDDSENSE)
   CLEAR_VDD_SENSE_FLAG();  // Clear Vdd monitoring flag
#endif
   (void)bdm_checkTargetVdd();    // Update Target Vdd LED

#endif // CAP_VDDCONTROL

   return(rc);
}
示例#2
0
//! Turns on Target Vdd if enabled.
//!
//!  @return
//!   \ref BDM_RC_OK                => Target Vdd confirmed on target \n
//!   \ref BDM_RC_VDD_NOT_PRESENT   => Target Vdd not present
//!
uint8_t bdm_setTargetVdd( void ) {
uint8_t rc = BDM_RC_OK;

#if (HW_CAPABILITY&CAP_VDDSENSE)
   DISABLE_VDD_SENSE_INT();
#endif
   
   switch (bdm_option.targetVdd) {
   case BDM_TARGET_VDD_OFF :
	   VDD_OFF();
	   // Check for externally supplied target Vdd (> 2 V)
	   WAIT_US(VDD_RISE_TIMEus); // Wait for Vdd to rise & stabilise
	   if (bdm_targetVddMeasure()<VDD_2v)
		   rc = BDM_RC_VDD_NOT_PRESENT;
	   break;
   case BDM_TARGET_VDD_3V3 :
	   VDD3_ON();
	   // Wait for Vdd to rise to 90% of 3V
	   WAIT_WITH_TIMEOUT_MS( 100 /* ms */, (bdm_targetVddMeasure()>VDD_3v3));
	   WAIT_US(VDD_RISE_TIMEus); // Wait for Vdd to rise & stabilise
	   if (bdm_targetVddMeasure()<VDD_3v3) {
		   VDD_OFF(); // In case of Vdd overload
		   rc = BDM_RC_VDD_NOT_PRESENT;
	   }
	   break;
   case BDM_TARGET_VDD_5V  :
	   VDD5_ON();
	   // Wait for Vdd to rise to 90% of 5V
	   WAIT_WITH_TIMEOUT_MS( 100 /* ms */, (bdm_targetVddMeasure()>VDD_5v));
	   WAIT_US(VDD_RISE_TIMEus); // Wait for Vdd to rise & stabilise
	   if (bdm_targetVddMeasure()<VDD_5v) {
		   VDD_OFF(); // In case of Vdd overload
		   rc = BDM_RC_VDD_NOT_PRESENT;
	   }
	   break;
   }
#if (HW_CAPABILITY&CAP_VDDSENSE)
   CLEAR_VDD_SENSE_FLAG(); // Clear Vdd Change Event
   ENABLE_VDD_SENSE_INT();
#endif

   (void)bdm_checkTargetVdd(); // Update Target Vdd LED & status
   return (rc);
}
示例#3
0
uint8_t m0110_recv(void)
{
    uint8_t data = 0;
    m0110_error = 0;

    WAIT_MS(clock_lo, 250, 1);  // keyboard may block long time
    for (uint8_t i = 0; i < 8; i++) {
        data <<= 1;
        WAIT_US(clock_lo, 200, 2);
        WAIT_US(clock_hi, 200, 3);
        if (data_in()) {
            data |= 1;
        }
    }
    idle();
    return data;
ERROR:
    print("m0110_recv err: "); phex(m0110_error); print("\n");
    _delay_ms(500);
    idle();
    return 0xFF;
}
示例#4
0
uint8_t m0110_send(uint8_t data)
{
    m0110_error = 0;

    request();
    WAIT_MS(clock_lo, 250, 1);  // keyboard may block long time
    for (uint8_t bit = 0x80; bit; bit >>= 1) {
        WAIT_US(clock_lo, 250, 3);
        if (data&bit) {
            data_hi();
        } else {
            data_lo();
        }
        WAIT_US(clock_hi, 200, 4);
    }
    _delay_us(100); // hold last bit for 80us
    idle();
    return 1;
ERROR:
    print("m0110_send err: "); phex(m0110_error); print("\n");
    _delay_ms(500);
    idle();
    return 0;
}
示例#5
0
//!  Cycle power ON to target
//!
//! @param mode
//!    - \ref RESET_SPECIAL => Power on in special mode,
//!    - \ref RESET_NORMAL  => Power on in normal mode
//!
//!  BKGD/BKPT is held low when power is re-applied to start
//!  target with BDM active if RESET_SPECIAL
//!
//!  @return
//!   \ref BDM_RC_OK                	=> Target Vdd confirmed on target \n
//!   \ref BDM_RC_VDD_WRONG_MODE    	=> Target Vdd not controlled by BDM interface \n
//!   \ref BDM_RC_VDD_NOT_PRESENT   	=> Target Vdd failed to rise 		\n
//!   \ref BDM_RC_RESET_TIMEOUT_RISE    => RESET signal failed to rise 		\n
//!   \ref BDM_RC_BKGD_TIMEOUT      	=> BKGD signal failed to rise
//!
uint8_t bdm_cycleTargetVddOn(uint8_t mode) {
uint8_t rc = BDM_RC_OK;

   mode &= RESET_MODE_MASK;

#if (HW_CAPABILITY&CAP_VDDCONTROL)

   switch(cable_status.target_type) {
#if (HW_CAPABILITY&CAP_CFVx_HW)
   case T_CFVx:
      bdmcf_interfaceIdle();  // Make sure BDM interface is idle
      if (mode == RESET_SPECIAL)
         BKPT_LOW();
      break;
#endif
#if (HW_CAPABILITY&CAP_BDM)     
   case T_HC12:
   case T_HCS08:
   case T_RS08:
   case T_CFV1:
      bdmHCS_interfaceIdle();  // Make sure BDM interface is idle
      if (mode == RESET_SPECIAL) {
         BDM_LOW();  // BKGD pin=L
      }
      break;
#endif      
#if (HW_CAPABILITY&CAP_JTAG_HW)     
   case T_JTAG:
   case T_MC56F80xx:
   case T_ARM_JTAG:
      jtag_interfaceIdle();  // Make sure BDM interface is idle
#endif      
      break;
   default:
      swd_interfaceIdle();
      break;
   }
#if (DEBUG&CYCLE_DEBUG)
   DEBUG_PIN     = 0;
   DEBUG_PIN     = 1;
   DEBUG_PIN     = 0;
   DEBUG_PIN     = 1;
#endif //  (DEBUG&CYCLE_DEBUG)

   // Power on with TargetVdd monitoring off
   rc = bdm_setTargetVdd();
   if (rc != BDM_RC_OK) // No target Vdd
      goto cleanUp;

#if (DEBUG&CYCLE_DEBUG)
   DEBUG_PIN     = 1;
   DEBUG_PIN     = 0;
#endif //  (DEBUG&CYCLE_DEBUG)
#if (HW_CAPABILITY&CAP_RST_IN)
   // RESET rise may be delayed by target POR
   if (bdm_option.useResetSignal) {
      WAIT_WITH_TIMEOUT_S( 2 /* s */, (RESET_IN!=0) );
   }
#endif
#if (DEBUG&CYCLE_DEBUG)
   DEBUG_PIN   = 0;
   DEBUG_PIN   = 1;
#endif // (DEBUG&CYCLE_DEBUG)

   // Let signals settle & CPU to finish reset (with BKGD held low)
   WAIT_US(BKGD_WAITus);

#if (HW_CAPABILITY&CAP_RST_IN)
   if (bdm_option.useResetSignal && (RESET_IN==0)) {
      // RESET didn't rise
      rc = BDM_RC_RESET_TIMEOUT_RISE;
      goto cleanUp;
      }
#endif //(HW_CAPABILITY&CAP_RST_IO)

#if (DEBUG&CYCLE_DEBUG)
   DEBUG_PIN     = 1;
   DEBUG_PIN     = 0;
#endif // (DEBUG&CYCLE_DEBUG)

#if (HW_CAPABILITY&CAP_CFVx_HW)
   if  (cable_status.target_type == T_CFVx)
      bdmcf_interfaceIdle();  // Release BKPT etc
   else
#endif
#if (HW_CAPABILITY&CAP_BDM)     
      bdmHCS_interfaceIdle();  // Release BKGD
#endif
   // Let processor start up
   WAIT_MS(RESET_RECOVERYms);

#if 0
// Removed - some targets may be holding BKGD low (e.g. used as port pin)
// This situation is handled elsewhere (requires power cycle)
   if (BDM_IN==0) { // BKGD didn't rise!
      rc = BDM_RC_BKGD_TIMEOUT;
      goto cleanUp;
      }
#endif // 0

   cable_status.reset  = RESET_DETECTED; // Cycling the power should have reset it!

cleanUp:
#if (HW_CAPABILITY&CAP_CFVx_HW)
   if  (cable_status.target_type == T_CFVx)
      bdmcf_interfaceIdle();  // Release BKPT etc
   else
#endif
#if (HW_CAPABILITY&CAP_BDM)     
      bdmHCS_interfaceIdle();  // Release BKGD
#endif
   
   WAIT_MS( 250 /* ms */);

//   EnableInterrupts;
#endif // CAP_VDDCONTROL

   (void)bdm_checkTargetVdd(); // Update Target Vdd LED & power status

   return(rc);
}