UINT32 wmt_plat_force_trigger_assert(ENUM_FORCE_TRG_ASSERT_T type)
{
UINT8 * p_virtual_addr = NULL;
switch(type){
case STP_FORCE_TRG_ASSERT_EMI:
WMT_PLAT_INFO_FUNC("[Force Assert] stp_trigger_firmware_assert_via_emi -->\n");
p_virtual_addr = wmt_plat_get_emi_virt_add(EXP_APMEM_CTRL_HOST_OUTBAND_ASSERT_W1);
if(!p_virtual_addr)
{
WMT_PLAT_ERR_FUNC("get virtual address fail\n");
return -1;
}
CONSYS_REG_WRITE(p_virtual_addr, EXP_APMEM_HOST_OUTBAND_ASSERT_MAGIC_W1);
WMT_PLAT_INFO_FUNC("[Force Assert] stp_trigger_firmware_assert_via_emi <--\n");
break;
case STP_FORCE_TRG_ASSERT_DEBUG_PIN:
CONSYS_REG_WRITE(CONSYS_AP2CONN_OSC_EN_REG,CONSYS_REG_READ(CONSYS_AP2CONN_OSC_EN_REG) & ~CONSYS_AP2CONN_WAKEUP_BIT);
WMT_PLAT_INFO_FUNC("enable:dump CONSYS_AP2CONN_OSC_EN_REG(0x%x)\n",CONSYS_REG_READ(CONSYS_AP2CONN_OSC_EN_REG));
usleep_range(64, 96);
CONSYS_REG_WRITE(CONSYS_AP2CONN_OSC_EN_REG,CONSYS_REG_READ(CONSYS_AP2CONN_OSC_EN_REG) | CONSYS_AP2CONN_WAKEUP_BIT);
WMT_PLAT_INFO_FUNC("disable:dump CONSYS_AP2CONN_OSC_EN_REG(0x%x)\n",CONSYS_REG_READ(CONSYS_AP2CONN_OSC_EN_REG));
break;
default:
WMT_PLAT_ERR_FUNC("unknow force trigger assert type\n");
break;
}
return 0;
}
INT32 mtk_wcn_consys_hw_vcn28_ctrl(UINT32 enable)
{
if (enable) {
/*in co-clock mode,need to turn on vcn28 when fm on */
#if CONSYS_PMIC_CTRL_ENABLE
#if defined(CONFIG_MTK_PMIC_LEGACY)
hwPowerOn(MT6328_POWER_LDO_VCN28, VOL_2800, "wcn_drv");
#else
if (reg_VCN28) {
regulator_set_voltage(reg_VCN28, VOL_2800, VOL_2800);
if (regulator_enable(reg_VCN28))
WMT_PLAT_ERR_FUNC("WMT do VCN28 PMIC on fail!\n");
}
#endif
#endif
WMT_PLAT_INFO_FUNC("turn on vcn28 for fm/gps usage in co-clock mode\n");
} else {
/*in co-clock mode,need to turn off vcn28 when fm off */
#if CONSYS_PMIC_CTRL_ENABLE
#if defined(CONFIG_MTK_PMIC_LEGACY)
hwPowerDown(MT6328_POWER_LDO_VCN28, "wcn_drv");
#else
if (reg_VCN28)
regulator_disable(reg_VCN28);
#endif
#endif
WMT_PLAT_INFO_FUNC("turn off vcn28 for fm/gps usage in co-clock mode\n");
}
return 0;
}
INT32 wmt_plat_get_tdm_antsel_index(VOID)
{
INT32 ret = -1;
#ifdef GPIO_TDM_REQ
UINT32 i;
UINT32 tbl_num = sizeof(mtk_wcn_tdm_req_info_tbls) / sizeof(mtk_wcn_tdm_req_info_tbls[0]);
UINT32 gpio_num = GPIO_TDM_REQ & 0x7fffffff;
for(i = 0; i < tbl_num; i++)
{
if(gpio_num == mtk_wcn_tdm_req_info_tbls[i].gpio_number)
break;
}
if(i == tbl_num)
{
WMT_PLAT_WARN_FUNC("can not get antsel index of GPIO_TDM_REQ(GPIO%d)\n",
gpio_num);
ret = -2;
}else
{
ret = mtk_wcn_tdm_req_info_tbls[i].ant_sel_index;
WMT_PLAT_INFO_FUNC("current GPIO_TDM_REQ(GPIO%d) antsel index is %d\n",
gpio_num,ret);
}
#else
WMT_PLAT_INFO_FUNC("GPIO_TDM_REQ is not defined\n");
#endif
return ret;
}
INT32 mtk_wcn_consys_hw_restore(struct device *device)
{
UINT32 addrPhy = 0;
if (gConEmiPhyBase) {
#if CONSYS_EMI_MPU_SETTING
/*set MPU for EMI share Memory */
WMT_PLAT_INFO_FUNC("setting MPU for EMI share memory\n");
#if defined(CONFIG_ARCH_MT6735)
emi_mpu_set_region_protection(gConEmiPhyBase + SZ_1M / 2,
gConEmiPhyBase + SZ_1M - 1,
13,
SET_ACCESS_PERMISSON(FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
FORBIDDEN, NO_PROTECTION, FORBIDDEN, NO_PROTECTION));
#elif defined(CONFIG_ARCH_MT6735M)
emi_mpu_set_region_protection(gConEmiPhyBase,
gConEmiPhyBase + SZ_1M - 1,
6,
SET_ACCESS_PERMISSON(FORBIDDEN, NO_PROTECTION, FORBIDDEN,
NO_PROTECTION));
#elif defined(CONFIG_ARCH_MT6753)
emi_mpu_set_region_protection(gConEmiPhyBase + SZ_1M / 2,
gConEmiPhyBase + SZ_1M - 1,
13,
SET_ACCESS_PERMISSON(FORBIDDEN, FORBIDDEN, FORBIDDEN,
FORBIDDEN, FORBIDDEN, NO_PROTECTION, FORBIDDEN, NO_PROTECTION));
#else
WMT_PLAT_WARN_FUNC("not define platform config\n");
#endif
#endif
/*consys to ap emi remapping register:10000320, cal remapping address */
addrPhy = (gConEmiPhyBase & 0xFFF00000) >> 20;
/*enable consys to ap emi remapping bit12 */
addrPhy = addrPhy | 0x1000;
CONSYS_REG_WRITE(conn_reg.topckgen_base + CONSYS_EMI_MAPPING_OFFSET,
CONSYS_REG_READ(conn_reg.topckgen_base + CONSYS_EMI_MAPPING_OFFSET) | addrPhy);
WMT_PLAT_INFO_FUNC("CONSYS_EMI_MAPPING dump in restore cb(0x%08x)\n",
CONSYS_REG_READ(conn_reg.topckgen_base + CONSYS_EMI_MAPPING_OFFSET));
#if 1
pEmibaseaddr = ioremap_nocache(gConEmiPhyBase + SZ_1M / 2, CONSYS_EMI_MEM_SIZE);
#else
pEmibaseaddr = ioremap_nocache(CONSYS_EMI_AP_PHY_BASE, CONSYS_EMI_MEM_SIZE);
#endif
if (pEmibaseaddr) {
WMT_PLAT_WARN_FUNC("EMI mapping OK(0x%p)\n", pEmibaseaddr);
memset_io(pEmibaseaddr, 0, CONSYS_EMI_MEM_SIZE);
} else {
WMT_PLAT_ERR_FUNC("EMI mapping fail\n");
}
} else {
static INT32 wmt_plat_dump_pin_conf(VOID)
{
WMT_PLAT_DBG_FUNC("[WMT-PLAT]=>dump wmt pin configuration start<=\n");
#if defined(CONFIG_MTK_GPIO_LEGACY)
#ifdef GPIO_COMBO_BGF_EINT_PIN
WMT_PLAT_DBG_FUNC("BGF_EINT(GPIO%d)\n", GPIO_COMBO_BGF_EINT_PIN);
#else
WMT_PLAT_DBG_FUNC("BGF_EINT(not defined)\n");
#endif
#ifdef CUST_EINT_COMBO_BGF_NUM
WMT_PLAT_DBG_FUNC("BGF_EINT_NUM(%d)\n", CUST_EINT_COMBO_BGF_NUM);
#else
WMT_PLAT_DBG_FUNC("BGF_EINT_NUM(not defined)\n");
#endif
#ifdef GPIO_COMBO_URXD_PIN
WMT_PLAT_DBG_FUNC("UART_RX(GPIO%d)\n", GPIO_COMBO_URXD_PIN);
#else
WMT_PLAT_DBG_FUNC("UART_RX(not defined)\n");
#endif
#if defined(FM_DIGITAL_INPUT) || defined(FM_DIGITAL_OUTPUT)
#ifdef GPIO_COMBO_I2S_CK_PIN
WMT_PLAT_DBG_FUNC("I2S_CK(GPIO%d)\n", GPIO_COMBO_I2S_CK_PIN);
#else
WMT_PLAT_DBG_FUNC("I2S_CK(not defined)\n");
#endif
#ifdef GPIO_COMBO_I2S_WS_PIN
WMT_PLAT_DBG_FUNC("I2S_WS(GPIO%d)\n", GPIO_COMBO_I2S_WS_PIN);
#else
WMT_PLAT_DBG_FUNC("I2S_WS(not defined)\n");
#endif
#ifdef GPIO_COMBO_I2S_DAT_PIN
WMT_PLAT_DBG_FUNC("I2S_DAT(GPIO%d)\n", GPIO_COMBO_I2S_DAT_PIN);
#else
WMT_PLAT_DBG_FUNC("I2S_DAT(not defined)\n");
#endif
#else /* FM_ANALOG_INPUT || FM_ANALOG_OUTPUT */
WMT_PLAT_DBG_FUNC("FM digital mode is not set, no need for I2S GPIOs\n");
#endif
#ifdef GPIO_GPS_SYNC_PIN
WMT_PLAT_DBG_FUNC("GPS_SYNC(GPIO%d)\n", GPIO_GPS_SYNC_PIN);
#else
WMT_PLAT_DBG_FUNC("GPS_SYNC(not defined)\n");
#endif
#ifdef GPIO_GPS_LNA_PIN
WMT_PLAT_INFO_FUNC("GPS_LNA(GPIO%d)\n", GPIO_GPS_LNA_PIN);
#else
WMT_PLAT_INFO_FUNC("GPS_LNA(not defined)\n");
#endif
#else /* #if defined(CONFIG_MTK_GPIO_LEGACY) */
#endif
WMT_PLAT_DBG_FUNC("[WMT-PLAT]=>dump wmt pin configuration emds<=\n");
return 0;
}
/*!
* \brief audio control callback function for CMB_STUB on ALPS
*
* A platform function required for dynamic binding with CMB_STUB on ALPS.
*
* \param state desired audio interface state to use
* \param flag audio interface control options
*
* \retval 0 operation success
* \retval -1 invalid parameters
* \retval < 0 error for operation fail
*/
INT32 wmt_plat_audio_ctrl(CMB_STUB_AIF_X state, CMB_STUB_AIF_CTRL ctrl)
{
INT32 iRet = 0;
/* input sanity check */
if ((CMB_STUB_AIF_MAX <= state)
|| (CMB_STUB_AIF_CTRL_MAX <= ctrl)) {
return -1;
}
iRet = 0;
/* set host side first */
switch (state) {
case CMB_STUB_AIF_0:
/* BT_PCM_OFF & FM line in/out */
iRet += wmt_plat_gpio_ctrl(PIN_I2S_GRP, PIN_STA_DEINIT);
break;
case CMB_STUB_AIF_1:
iRet += wmt_plat_gpio_ctrl(PIN_I2S_GRP, PIN_STA_DEINIT);
break;
case CMB_STUB_AIF_2:
iRet += wmt_plat_gpio_ctrl(PIN_I2S_GRP, PIN_STA_INIT);
break;
case CMB_STUB_AIF_3:
iRet += wmt_plat_gpio_ctrl(PIN_I2S_GRP, PIN_STA_INIT);
break;
default:
/* FIXME: move to cust folder? */
WMT_PLAT_ERR_FUNC("invalid state [%d]\n", state);
iRet = -1;
break;
}
if (CMB_STUB_AIF_CTRL_EN == ctrl) {
WMT_PLAT_INFO_FUNC("call chip aif setting\n");
/* need to control chip side GPIO */
if (NULL != wmt_plat_audio_if_cb) {
iRet += (*wmt_plat_audio_if_cb) (state, MTK_WCN_BOOL_FALSE);
} else {
WMT_PLAT_WARN_FUNC("wmt_plat_audio_if_cb is not registered\n");
iRet -= 1;
}
} else {
WMT_PLAT_INFO_FUNC("skip chip aif setting\n");
}
return iRet;
}
INT32
mtk_wcn_consys_hw_gpio_ctrl (UINT32 on)
{
INT32 iRet = 0;
WMT_PLAT_INFO_FUNC("CONSYS-HW-GPIO-CTRL(0x%08x), start\n",on);
if(on)
{
/*if external modem used,GPS_SYNC still needed to control*/
iRet += wmt_plat_gpio_ctrl(PIN_GPS_SYNC, PIN_STA_INIT);
iRet += wmt_plat_gpio_ctrl(PIN_GPS_LNA, PIN_STA_INIT);
iRet += wmt_plat_gpio_ctrl(PIN_I2S_GRP,PIN_STA_INIT);
/*set EINT< -ommited-> move this to WMT-IC module, where common sdio interface will be identified and do proper operation*/
// TODO: [FixMe][GeorgeKuo] double check if BGF_INT is implemented ok
//iRet += wmt_plat_gpio_ctrl(PIN_BGF_EINT, PIN_STA_MUX);
#if CFG_WMT_DUMP_INT_STATUS
wmt_plat_BGF_irq_dump_status();
#endif
iRet += wmt_plat_eirq_ctrl(PIN_BGF_EINT, PIN_STA_INIT);
#if CFG_WMT_DUMP_INT_STATUS
wmt_plat_BGF_irq_dump_status();
#endif
iRet += wmt_plat_eirq_ctrl(PIN_BGF_EINT, PIN_STA_EINT_DIS);
#if CFG_WMT_DUMP_INT_STATUS
wmt_plat_BGF_irq_dump_status();
#endif
WMT_PLAT_INFO_FUNC("CONSYS-HW, BGF IRQ registered and disabled \n");
}else{
/* set bgf eint/all eint to deinit state, namely input low state*/
iRet += wmt_plat_eirq_ctrl(PIN_BGF_EINT, PIN_STA_EINT_DIS);
iRet += wmt_plat_eirq_ctrl(PIN_BGF_EINT, PIN_STA_DEINIT);
#if CFG_WMT_DUMP_INT_STATUS
wmt_plat_BGF_irq_dump_status();
#endif
WMT_PLAT_INFO_FUNC("CONSYS-HW, BGF IRQ unregistered and disabled\n");
//iRet += wmt_plat_gpio_ctrl(PIN_BGF_EINT, PIN_STA_DEINIT);
/*if external modem used,GPS_SYNC still needed to control*/
iRet += wmt_plat_gpio_ctrl(PIN_GPS_SYNC, PIN_STA_DEINIT);
iRet += wmt_plat_gpio_ctrl(PIN_I2S_GRP,PIN_STA_DEINIT);
/* deinit gps_lna*/
iRet += wmt_plat_gpio_ctrl(PIN_GPS_LNA, PIN_STA_DEINIT);
}
WMT_PLAT_INFO_FUNC("CONSYS-HW-GPIO-CTRL(0x%08x), finish\n",on);
return iRet;
}
INT32 mtk_wcn_consys_hw_pwr_off (VOID)
{
INT32 iRet = 0;
WMT_PLAT_INFO_FUNC("CONSYS-HW-PWR-OFF, start\n");
iRet += mtk_wcn_consys_hw_reg_ctrl(0,0);
iRet += mtk_wcn_consys_hw_gpio_ctrl(0);
WMT_PLAT_INFO_FUNC("CONSYS-HW-PWR-OFF, finish(%d)\n",iRet);
return iRet;
}
INT32
mtk_wcn_consys_hw_rst (UINT32 co_clock_en)
{
INT32 iRet = 0;
WMT_PLAT_INFO_FUNC("CONSYS-HW, hw_rst start, eirq should be disabled before this step\n");
/*1. do whole hw power off flow*/
iRet += mtk_wcn_consys_hw_reg_ctrl(0,co_clock_en);
/*2. do whole hw power on flow*/
iRet += mtk_wcn_consys_hw_reg_ctrl(1,co_clock_en);
WMT_PLAT_INFO_FUNC("CONSYS-HW, hw_rst finish, eirq should be enabled after this step\n");
return iRet;
}
INT32 mtk_wcn_consys_hw_pwr_on(UINT32 co_clock_type)
{
INT32 iRet = 0;
WMT_PLAT_INFO_FUNC("CONSYS-HW-PWR-ON, start\n");
iRet += mtk_wcn_consys_hw_reg_ctrl(1, co_clock_type);
iRet += mtk_wcn_consys_hw_gpio_ctrl(1);
#if CONSYS_ENALBE_SET_JTAG
if (gJtagCtrl)
mtk_wcn_consys_jtag_set_for_mcu();
#endif
WMT_PLAT_INFO_FUNC("CONSYS-HW-PWR-ON, finish(%d)\n", iRet);
return iRet;
}
UINT32 mtk_wcn_consys_jtag_flag_ctrl(UINT32 en)
{
WMT_PLAT_INFO_FUNC("%s jtag set for MCU\n",en ? "enable" : "disable");
gJtagCtrl = en;
return 0;
}
UINT32 wmt_plat_get_soc_chipid(void)
{
UINT32 chipId = mtk_wcn_consys_soc_chipid();
WMT_PLAT_INFO_FUNC("current SOC chip:0x%x\n", chipId);
return chipId;
}
UINT32 mtk_wcn_consys_hw_osc_en_ctrl(UINT32 en)
{
if(en)
{
WMT_PLAT_INFO_FUNC("enable consys sleep mode(turn off 26M)\n");
CONSYS_REG_WRITE(CONSYS_AP2CONN_OSC_EN_REG, CONSYS_REG_READ(CONSYS_AP2CONN_OSC_EN_REG) & ~CONSYS_AP2CONN_OSC_EN_BIT);
}else
{
WMT_PLAT_INFO_FUNC("disable consys sleep mode\n");
CONSYS_REG_WRITE(CONSYS_AP2CONN_OSC_EN_REG, CONSYS_REG_READ(CONSYS_AP2CONN_OSC_EN_REG) | CONSYS_AP2CONN_OSC_EN_BIT);
}
WMT_PLAT_INFO_FUNC("dump CONSYS_AP2CONN_OSC_EN_REG(0x%x)\n",CONSYS_REG_READ(CONSYS_AP2CONN_OSC_EN_REG));
return 0;
}
INT32 mtk_wcn_consys_hw_vcn28_ctrl(UINT32 enable)
{
if(enable){
/*in co-clock mode,need to turn on vcn28 when fm on*/
#if CONSYS_PMIC_CTRL_ENABLE
hwPowerOn(MT6323_POWER_LDO_VCN28,VOL_DEFAULT,"MOD_WMT");
#endif
WMT_PLAT_INFO_FUNC("turn on vcn28 for fm/gps usage in co-clock mode\n");
}else{
/*in co-clock mode,need to turn off vcn28 when fm off*/
#if CONSYS_PMIC_CTRL_ENABLE
hwPowerDown(MT6323_POWER_LDO_VCN28,"MOD_WMT");
#endif
WMT_PLAT_INFO_FUNC("turn off vcn28 for fm/gps usage in co-clock mode\n");
}
return 0;
}
INT32 mtk_wcn_consys_hw_vcn28_ctrl(UINT32 enable)
{
if(enable){
/*in co-clock mode,need to turn on vcn28 when fm on*/
#if CONSYS_PMIC_CTRL_ENABLE
pmic_set_register_value(PMIC_VCN28_ON_CTRL,1);
#endif
WMT_PLAT_INFO_FUNC("turn on vcn28 for fm/gps usage in co-clock mode\n");
}else{
/*in co-clock mode,need to turn off vcn28 when fm off*/
#if CONSYS_PMIC_CTRL_ENABLE
pmic_set_register_value(PMIC_VCN28_ON_CTRL,0);
#endif
WMT_PLAT_INFO_FUNC("turn off vcn28 for fm/gps usage in co-clock mode\n");
}
return 0;
}
INT32 mtk_wcn_regulator_get(void)
{
INT32 iRet = -1;
if(!(IS_ERR(wmt_dev))){
reg_V18 = regulator_get(wmt_dev,"VCN_1V8");
if(reg_V18)
WMT_PLAT_INFO_FUNC("Regulator_get VCN_1V8 sucess\n");
reg_V33_BT = regulator_get(wmt_dev,"VCN33_BT");
if(reg_V33_BT)
WMT_PLAT_INFO_FUNC("Regulator_get VCN33_BT sucess\n");
reg_V33_WIFI = regulator_get(wmt_dev,"VCN33_WIFI");
if(reg_V33_WIFI)
WMT_PLAT_INFO_FUNC("Regulator_get VCN33_WIFI sucess\n");
iRet = 0;
}else
WMT_PLAT_ERR_FUNC("wmt_dev device pointer error, cannot do VCN18 power on!\n");
return iRet;
}
irqreturn_t wmt_plat_bgf_irq_isr(INT32 i,VOID *arg)
{
#if CFG_WMT_PS_SUPPORT
wmt_plat_eirq_ctrl(PIN_BGF_EINT, PIN_STA_EINT_DIS);
wmt_plat_bgf_eirq_cb();
#else
WMT_PLAT_INFO_FUNC("skip irq handing becasue psm is disable");
#endif
return IRQ_HANDLED;
}
INT32 mtk_wcn_consys_hw_bt_paldo_ctrl(UINT32 enable)
{
/* spin_lock_irqsave(&gBtWifiV33.lock,gBtWifiV33.flags); */
if (enable) {
if (1 == gBtWifiV33.counter) {
gBtWifiV33.counter++;
WMT_PLAT_DBG_FUNC("V33 has been enabled,counter(%d)\n", gBtWifiV33.counter);
} else if (2 == gBtWifiV33.counter) {
WMT_PLAT_DBG_FUNC("V33 has been enabled,counter(%d)\n", gBtWifiV33.counter);
} else {
#if CONSYS_PMIC_CTRL_ENABLE
/*do BT PMIC on,depenency PMIC API ready */
/*switch BT PALDO control from SW mode to HW mode:0x416[5]-->0x1 */
/* VOL_DEFAULT, VOL_3300, VOL_3400, VOL_3500, VOL_3600 */
hwPowerOn(MT6325_POWER_LDO_VCN33, VOL_3300, "wcn_drv");
mt6325_upmu_set_rg_vcn33_on_ctrl(1);
#endif
WMT_PLAT_INFO_FUNC("WMT do BT/WIFI v3.3 on\n");
gBtWifiV33.counter++;
}
} else {
if (1 == gBtWifiV33.counter) {
/*do BT PMIC off */
/*switch BT PALDO control from HW mode to SW mode:0x416[5]-->0x0 */
#if CONSYS_PMIC_CTRL_ENABLE
mt6325_upmu_set_rg_vcn33_on_ctrl(0);
hwPowerDown(MT6325_POWER_LDO_VCN33, "wcn_drv");
#endif
WMT_PLAT_INFO_FUNC("WMT do BT/WIFI v3.3 off\n");
gBtWifiV33.counter--;
} else if (2 == gBtWifiV33.counter) {
gBtWifiV33.counter--;
WMT_PLAT_DBG_FUNC("V33 no need disabled,counter(%d)\n", gBtWifiV33.counter);
} else {
WMT_PLAT_DBG_FUNC("V33 has been disabled,counter(%d)\n", gBtWifiV33.counter);
}
}
/* spin_unlock_irqrestore(&gBtWifiV33.lock,gBtWifiV33.flags); */
return 0;
}
INT32 mtk_wcn_consys_hw_init()
{
INT32 iRet = -1;
UINT32 addrPhy = 0;
/*set MPU for EMI share Memory*/
WMT_PLAT_INFO_FUNC("setting MPU for EMI share memory\n");
emi_mpu_set_region_protection(gConEmiPhyBase + SZ_1M/2,
gConEmiPhyBase + SZ_1M,
5,
SET_ACCESS_PERMISSON(FORBIDDEN,NO_PROTECTION,FORBIDDEN,NO_PROTECTION));
WMT_PLAT_INFO_FUNC("get consys start phy address(0x%x)\n",gConEmiPhyBase);
/*consys to ap emi remapping register:10001310, cal remapping address*/
addrPhy = (gConEmiPhyBase & 0xFFF00000) >> 20;
/*enable consys to ap emi remapping bit12*/
addrPhy = addrPhy | 0x1000;
CONSYS_REG_WRITE(CONSYS_EMI_MAPPING,CONSYS_REG_READ(CONSYS_EMI_MAPPING) | addrPhy);
WMT_PLAT_INFO_FUNC("CONSYS_EMI_MAPPING dump(0x%08x)\n",CONSYS_REG_READ(CONSYS_EMI_MAPPING));
#if 1
pEmibaseaddr = ioremap_nocache(gConEmiPhyBase + CONSYS_EMI_AP_PHY_OFFSET,CONSYS_EMI_MEM_SIZE);
#else
pEmibaseaddr = ioremap_nocache(CONSYS_EMI_AP_PHY_BASE,CONSYS_EMI_MEM_SIZE);
#endif
//pEmibaseaddr = ioremap_nocache(0x80090400,270*KBYTE);
if(pEmibaseaddr)
{
WMT_PLAT_INFO_FUNC("EMI mapping OK(0x%p)\n",pEmibaseaddr);
memset(pEmibaseaddr,0,CONSYS_EMI_MEM_SIZE);
iRet = 0;
}else{
WMT_PLAT_ERR_FUNC("EMI mapping fail\n");
}
WMT_PLAT_INFO_FUNC("register connsys restore cb for complying with IPOH function\n");
register_swsusp_restore_noirq_func(ID_M_CONNSYS,mtk_wcn_consys_hw_restore,NULL);
return iRet;
}
VOID __init mtk_wcn_consys_memory_reserve(VOID)
{
gConEmiPhyBase = arm_memblock_steal(SZ_1M,SZ_1M);
if(gConEmiPhyBase)
{
WMT_PLAT_INFO_FUNC("memblock done: 0x%x\n",gConEmiPhyBase);
}else
{
WMT_PLAT_ERR_FUNC("memblock fail\n");
}
}
INT32 mtk_wcn_consys_hw_bt_paldo_ctrl(UINT32 enable)
{
if(enable){
/*do BT PMIC on,depenency PMIC API ready*/
/*switch BT PALDO control from SW mode to HW mode:0x416[5]-->0x1*/
#if CONSYS_PMIC_CTRL_ENABLE
if(reg_V33_BT)
regulator_enable(reg_V33_BT);
#endif
WMT_PLAT_INFO_FUNC("WMT do BT PMIC on\n");
}else{
/*do BT PMIC off*/
/*switch BT PALDO control from HW mode to SW mode:0x416[5]-->0x0*/
#if CONSYS_PMIC_CTRL_ENABLE
if(reg_V33_BT)
regulator_disable(reg_V33_BT);
#endif
WMT_PLAT_INFO_FUNC("WMT do BT PMIC off\n");
}
return 0;
}
INT32 mtk_wcn_consys_hw_wifi_paldo_ctrl(UINT32 enable)
{
if(enable){
/*do WIFI PMIC on,depenency PMIC API ready*/
/*switch WIFI PALDO control from SW mode to HW mode:0x418[14]-->0x1*/
#if CONSYS_PMIC_CTRL_ENABLE
hwPowerOn(MT6323_POWER_LDO_VCN33_WIFI,VOL_3300,"MOD_WMT");
upmu_set_vcn33_on_ctrl_wifi(1);
#endif
WMT_PLAT_INFO_FUNC("WMT do WIFI PMIC on\n");
}else{
/*do WIFI PMIC off*/
/*switch WIFI PALDO control from HW mode to SW mode:0x418[14]-->0x0*/
#if CONSYS_PMIC_CTRL_ENABLE
upmu_set_vcn33_on_ctrl_wifi(0);
hwPowerDown(MT6323_POWER_LDO_VCN33_WIFI,"MOD_WMT");
#endif
WMT_PLAT_INFO_FUNC("WMT do WIFI PMIC off\n");
}
return 0;
}
INT32 mtk_wcn_consys_hw_bt_paldo_ctrl(UINT32 enable)
{
if (enable) {
/*do BT PMIC on,depenency PMIC API ready */
/*switch BT PALDO control from SW mode to HW mode:0x416[5]-->0x1 */
#if CONSYS_PMIC_CTRL_ENABLE
/* VOL_DEFAULT, VOL_3300, VOL_3400, VOL_3500, VOL_3600 */
#if defined(CONFIG_MTK_PMIC_LEGACY)
hwPowerOn(MT6328_POWER_LDO_VCN33_BT, VOL_3300, "wcn_drv");
#else
if (reg_VCN33_BT) {
regulator_set_voltage(reg_VCN33_BT, VOL_3300, VOL_3300);
if (regulator_enable(reg_VCN33_BT))
WMT_PLAT_ERR_FUNC("WMT do BT PMIC on fail!\n");
}
#endif
pmic_set_register_value(PMIC_RG_VCN33_ON_CTRL_BT, 1);
#endif
WMT_PLAT_INFO_FUNC("WMT do BT PMIC on\n");
} else {
/*do BT PMIC off */
/*switch BT PALDO control from HW mode to SW mode:0x416[5]-->0x0 */
#if CONSYS_PMIC_CTRL_ENABLE
pmic_set_register_value(PMIC_RG_VCN33_ON_CTRL_BT, 0);
#if defined(CONFIG_MTK_PMIC_LEGACY)
hwPowerDown(MT6328_POWER_LDO_VCN33_BT, "wcn_drv");
#else
if (reg_VCN33_BT)
regulator_disable(reg_VCN33_BT);
#endif
#endif
WMT_PLAT_INFO_FUNC("WMT do BT PMIC off\n");
}
return 0;
}
INT32 mtk_wcn_consys_hw_bt_paldo_ctrl(UINT32 enable)
{
if(enable){
/*do BT PMIC on,depenency PMIC API ready*/
/*switch BT PALDO control from SW mode to HW mode:0x416[5]-->0x1*/
#if CONSYS_PMIC_CTRL_ENABLE
/* VOL_DEFAULT, VOL_3300, VOL_3400, VOL_3500, VOL_3600*/
hwPowerOn(MT6325_POWER_LDO_VCN33, VOL_3300, "wcn_drv");
mt6325_upmu_set_rg_vcn33_on_ctrl(1);
#endif
WMT_PLAT_INFO_FUNC("WMT do BT PMIC on\n");
}else{
/*do BT PMIC off*/
/*switch BT PALDO control from HW mode to SW mode:0x416[5]-->0x0*/
#if CONSYS_PMIC_CTRL_ENABLE
mt6325_upmu_set_rg_vcn33_on_ctrl(0);
hwPowerDown(MT6325_POWER_LDO_VCN33,"wcn_drv");
#endif
WMT_PLAT_INFO_FUNC("WMT do BT PMIC off\n");
}
return 0;
}
INT32 wmt_plat_i2s_ctrl(ENUM_PIN_STATE state)
{
/* TODO: [NewFeature][GeorgeKuo]: GPIO_I2Sx is changed according to different project. */
/* TODO: provide a translation table in board_custom.h for different ALPS project customization. */
#if defined(CONFIG_MTK_GPIO_LEGACY)
#if defined(FM_DIGITAL_INPUT) || defined(FM_DIGITAL_OUTPUT)
#if defined(GPIO_COMBO_I2S_CK_PIN)
switch (state) {
case PIN_STA_INIT:
case PIN_STA_MUX:
mt_set_gpio_mode(GPIO_COMBO_I2S_CK_PIN, GPIO_COMBO_I2S_CK_PIN_M_I2S0_CK);
mt_set_gpio_mode(GPIO_COMBO_I2S_WS_PIN, GPIO_COMBO_I2S_WS_PIN_M_I2S0_WS);
mt_set_gpio_mode(GPIO_COMBO_I2S_DAT_PIN, GPIO_COMBO_I2S_DAT_PIN_M_I2S0_DAT);
WMT_PLAT_DBG_FUNC("WMT-PLAT:I2S init (I2S0 system)\n");
break;
case PIN_STA_IN_L:
case PIN_STA_DEINIT:
mt_set_gpio_mode(GPIO_COMBO_I2S_CK_PIN, GPIO_COMBO_I2S_CK_PIN_M_GPIO);
mt_set_gpio_dir(GPIO_COMBO_I2S_CK_PIN, GPIO_DIR_OUT);
mt_set_gpio_out(GPIO_COMBO_I2S_CK_PIN, GPIO_OUT_ZERO);
mt_set_gpio_mode(GPIO_COMBO_I2S_WS_PIN, GPIO_COMBO_I2S_WS_PIN_M_GPIO);
mt_set_gpio_dir(GPIO_COMBO_I2S_WS_PIN, GPIO_DIR_OUT);
mt_set_gpio_out(GPIO_COMBO_I2S_WS_PIN, GPIO_OUT_ZERO);
mt_set_gpio_mode(GPIO_COMBO_I2S_DAT_PIN, GPIO_COMBO_I2S_DAT_PIN_M_GPIO);
mt_set_gpio_dir(GPIO_COMBO_I2S_DAT_PIN, GPIO_DIR_OUT);
mt_set_gpio_out(GPIO_COMBO_I2S_DAT_PIN, GPIO_OUT_ZERO);
WMT_PLAT_DBG_FUNC("WMT-PLAT:I2S deinit (out 0)\n");
break;
default:
WMT_PLAT_WARN_FUNC("WMT-PLAT:Warnning, invalid state(%d) on I2S Group\n", state);
break;
}
#else
WMT_PLAT_ERR_FUNC("[MT6620]Error:FM digital mode set, but no I2S GPIOs defined\n");
#endif
#else
WMT_PLAT_INFO_FUNC
("[MT6620]warnning:FM digital mode is not set, no I2S GPIO settings should be modified by combo driver\n");
#endif
#else /* #if defined(CONFIG_MTK_GPIO_LEGACY) */
#endif
return 0;
}
INT32
wmt_plat_bgf_eint_ctrl (
ENUM_PIN_STATE state
)
{
#ifdef GPIO_COMBO_BGF_EINT_PIN
switch(state)
{
case PIN_STA_INIT:
/*set to gpio input low, pull down enable*/
mt_set_gpio_mode(GPIO_COMBO_BGF_EINT_PIN, GPIO_COMBO_BGF_EINT_PIN_M_GPIO);
mt_set_gpio_dir(GPIO_COMBO_BGF_EINT_PIN, GPIO_DIR_IN);
mt_set_gpio_pull_select(GPIO_COMBO_BGF_EINT_PIN, GPIO_PULL_DOWN);
mt_set_gpio_pull_enable(GPIO_COMBO_BGF_EINT_PIN, GPIO_PULL_ENABLE);
WMT_PLAT_DBG_FUNC("WMT-PLAT:BGFInt init(in pd) \n");
break;
case PIN_STA_MUX:
mt_set_gpio_mode(GPIO_COMBO_BGF_EINT_PIN, GPIO_COMBO_BGF_EINT_PIN_M_GPIO);
mt_set_gpio_pull_enable(GPIO_COMBO_BGF_EINT_PIN, GPIO_PULL_ENABLE);
mt_set_gpio_pull_select(GPIO_COMBO_BGF_EINT_PIN, GPIO_PULL_UP);
mt_set_gpio_mode(GPIO_COMBO_BGF_EINT_PIN, GPIO_COMBO_BGF_EINT_PIN_M_EINT);
WMT_PLAT_DBG_FUNC("WMT-PLAT:BGFInt mux (eint) \n");
break;
case PIN_STA_IN_L:
case PIN_STA_DEINIT:
/*set to gpio input low, pull down enable*/
mt_set_gpio_mode(GPIO_COMBO_BGF_EINT_PIN, GPIO_COMBO_BGF_EINT_PIN_M_GPIO);
mt_set_gpio_dir(GPIO_COMBO_BGF_EINT_PIN, GPIO_DIR_IN);
mt_set_gpio_pull_select(GPIO_COMBO_BGF_EINT_PIN, GPIO_PULL_DOWN);
mt_set_gpio_pull_enable(GPIO_COMBO_BGF_EINT_PIN, GPIO_PULL_ENABLE);
WMT_PLAT_DBG_FUNC("WMT-PLAT:BGFInt deinit(in pd) \n");
break;
default:
WMT_PLAT_WARN_FUNC("WMT-PLAT:Warnning, invalid state(%d) on BGF EINT\n", state);
break;
}
#else
WMT_PLAT_INFO_FUNC("WMT-PLAT:BGF EINT not defined\n");
#endif
return 0;
}
VOID wmt_plat_BGF_irq_dump_status(VOID)
{
WMT_PLAT_INFO_FUNC("this function is null in MT6572\n");
}
INT32
wmt_plat_eirq_ctrl (
ENUM_PIN_ID id,
ENUM_PIN_STATE state
)
{
INT32 iret;
// TODO: [ChangeFeature][GeorgeKuo]: use another function to handle this, as done in gpio_ctrls
if ( (PIN_STA_INIT != state )
&& (PIN_STA_DEINIT != state )
&& (PIN_STA_EINT_EN != state )
&& (PIN_STA_EINT_DIS != state ) ) {
WMT_PLAT_WARN_FUNC("WMT-PLAT:invalid PIN_STATE(%d) in eirq_ctrl for PIN(%d)\n", state, id);
return -1;
}
iret = -2;
switch (id) {
case PIN_BGF_EINT:
#if 1
if (PIN_STA_INIT == state) {
iret = request_irq(MT_CONN2AP_BTIF_WAKEUP_IRQ_ID,
(irq_handler_t)wmt_plat_bgf_irq_isr,
IRQF_TRIGGER_LOW,
"BTIF_WAKEUP_IRQ",
NULL);
if(iret)
{
WMT_PLAT_ERR_FUNC("request_irq fail,irq_no(%d),iret(%d)\n",MT_CONN2AP_BTIF_WAKEUP_IRQ_ID,iret);
return iret;
}
gbgfIrqBle.counter = 1;
}
else if (PIN_STA_EINT_EN == state) {
spin_lock_irqsave(&gbgfIrqBle.lock,gbgfIrqBle.flags);
if(gbgfIrqBle.counter)
{
WMT_PLAT_DBG_FUNC("BGF INT has been enabled,counter(%d)\n",gbgfIrqBle.counter);;
}
else
{
enable_irq(MT_CONN2AP_BTIF_WAKEUP_IRQ_ID);
gbgfIrqBle.counter++;
}
WMT_PLAT_DBG_FUNC("WMT-PLAT:BGFInt (en) \n");
spin_unlock_irqrestore(&gbgfIrqBle.lock,gbgfIrqBle.flags);
}
else if (PIN_STA_EINT_DIS == state) {
spin_lock_irqsave(&gbgfIrqBle.lock,gbgfIrqBle.flags);
if(!gbgfIrqBle.counter)
{
WMT_PLAT_INFO_FUNC("BGF INT has been disabled,counter(%d)\n",gbgfIrqBle.counter);;
}
else
{
disable_irq_nosync(MT_CONN2AP_BTIF_WAKEUP_IRQ_ID);
gbgfIrqBle.counter--;
}
WMT_PLAT_DBG_FUNC("WMT-PLAT:BGFInt (dis) \n");
spin_unlock_irqrestore(&gbgfIrqBle.lock,gbgfIrqBle.flags);
}
else {
free_irq(MT_CONN2AP_BTIF_WAKEUP_IRQ_ID,NULL);
/* de-init: nothing to do in ALPS, such as un-registration... */
}
#else
WMT_PLAT_INFO_FUNC("WMT-PLAT:BGF EINT not defined\n", state);
#endif
iret = 0;
break;
default:
WMT_PLAT_WARN_FUNC("WMT-PLAT:unsupported EIRQ(PIN_ID:%d) in eirq_ctrl\n", id);
iret = -1;
break;
}
return iret;
}
INT32 mtk_wcn_consys_hw_reg_ctrl(UINT32 on, UINT32 co_clock_type)
{
INT32 iRet = -1;
UINT32 retry = 10;
UINT32 consysHwChipId = 0;
WMT_PLAT_WARN_FUNC("CONSYS-HW-REG-CTRL(0x%08x),start\n", on);
if (on) {
WMT_PLAT_DBG_FUNC("++\n");
/*step1.PMIC ctrl*/
#if CONSYS_PMIC_CTRL_ENABLE
/*need PMIC driver provide new API protocol */
/*1.AP power on VCN_1V8 LDO (with PMIC_WRAP API) VCN_1V8 */
pmic_set_register_value(PMIC_RG_VCN18_ON_CTRL, 0);
/* VOL_DEFAULT, VOL_1200, VOL_1300, VOL_1500, VOL_1800... */
#if defined(CONFIG_MTK_PMIC_LEGACY)
hwPowerOn(MT6328_POWER_LDO_VCN18, VOL_1800, "wcn_drv");
#else
if (reg_VCN18) {
regulator_set_voltage(reg_VCN18, VOL_1800, VOL_1800);
if (regulator_enable(reg_VCN18))
WMT_PLAT_ERR_FUNC("enable VCN18 fail\n");
else
WMT_PLAT_DBG_FUNC("enable VCN18 ok\n");
}
#endif
udelay(150);
if (co_clock_type) {
/*step0,clk buf ctrl */
WMT_PLAT_INFO_FUNC("co clock type(%d),turn on clk buf\n", co_clock_type);
#if CONSYS_CLOCK_BUF_CTRL
clk_buf_ctrl(CLK_BUF_CONN, 1);
#endif
/*if co-clock mode: */
/*2.set VCN28 to SW control mode (with PMIC_WRAP API) */
/*turn on VCN28 LDO only when FMSYS is activated" */
pmic_set_register_value(PMIC_RG_VCN28_ON_CTRL, 0);
} else {
/*if NOT co-clock: */
/*2.1.switch VCN28 to HW control mode (with PMIC_WRAP API) */
pmic_set_register_value(PMIC_RG_VCN28_ON_CTRL, 1);
/*2.2.turn on VCN28 LDO (with PMIC_WRAP API)" */
/*fix vcn28 not balance warning */
#if defined(CONFIG_MTK_PMIC_LEGACY)
hwPowerOn(MT6328_POWER_LDO_VCN28, VOL_2800, "wcn_drv");
#else
if (reg_VCN28) {
regulator_set_voltage(reg_VCN28, VOL_2800, VOL_2800);
if (regulator_enable(reg_VCN28))
WMT_PLAT_ERR_FUNC("enable VCN_2V8 fail!\n");
else
WMT_PLAT_DBG_FUNC("enable VCN_2V8 ok\n");
}
#endif
}
#endif
/*step2.MTCMOS ctrl*/
#ifdef CONFIG_OF /*use DT */
/*3.assert CONNSYS CPU SW reset 0x10007018 "[12]=1'b1 [31:24]=8'h88 (key)" */
CONSYS_REG_WRITE((conn_reg.ap_rgu_base + CONSYS_CPU_SW_RST_OFFSET),
CONSYS_REG_READ(conn_reg.ap_rgu_base + CONSYS_CPU_SW_RST_OFFSET) |
CONSYS_CPU_SW_RST_BIT | CONSYS_CPU_SW_RST_CTRL_KEY);
/*turn on SPM clock gating enable PWRON_CONFG_EN 0x10006000 32'h0b160001 */
CONSYS_REG_WRITE((conn_reg.spm_base + CONSYS_PWRON_CONFG_EN_OFFSET), CONSYS_PWRON_CONFG_EN_VALUE);
#if CONSYS_PWR_ON_OFF_API_AVAILABLE
#if defined(CONFIG_MTK_CLKMGR)
iRet = conn_power_on(); /* consult clkmgr owner. */
if (iRet)
WMT_PLAT_ERR_FUNC("conn_power_on fail(%d)\n", iRet);
WMT_PLAT_DBG_FUNC("conn_power_on ok\n");
#else
iRet = clk_prepare_enable(clk_scp_conn_main);
if (iRet)
WMT_PLAT_ERR_FUNC("clk_prepare_enable(clk_scp_conn_main) fail(%d)\n", iRet);
WMT_PLAT_DBG_FUNC("clk_prepare_enable(clk_scp_conn_main) ok\n");
#endif /* defined(CONFIG_MTK_CLKMGR) */
#else
/*2.write conn_top1_pwr_on=1, power on conn_top1 0x10006280 [2] 1'b1 */
CONSYS_REG_WRITE(conn_reg.spm_base + CONSYS_TOP1_PWR_CTRL_OFFSET,
CONSYS_REG_READ(conn_reg.spm_base + CONSYS_TOP1_PWR_CTRL_OFFSET) |
CONSYS_SPM_PWR_ON_BIT);
/*3.read conn_top1_pwr_on_ack =1, power on ack ready 0x1000660C [1] */
while (0 == (CONSYS_PWR_ON_ACK_BIT & CONSYS_REG_READ(conn_reg.spm_base + CONSYS_PWR_CONN_ACK_OFFSET)))
NULL;
/*5.write conn_top1_pwr_on_s=1, power on conn_top1 0x10006280 [3] 1'b1 */
CONSYS_REG_WRITE(conn_reg.spm_base + CONSYS_TOP1_PWR_CTRL_OFFSET,
CONSYS_REG_READ(conn_reg.spm_base + CONSYS_TOP1_PWR_CTRL_OFFSET) |
CONSYS_SPM_PWR_ON_S_BIT);
/*6.write conn_clk_dis=0, enable connsys clock 0x10006280 [4] 1'b0 */
CONSYS_REG_WRITE(conn_reg.spm_base + CONSYS_TOP1_PWR_CTRL_OFFSET,
CONSYS_REG_READ(conn_reg.spm_base + CONSYS_TOP1_PWR_CTRL_OFFSET) &
~CONSYS_CLK_CTRL_BIT);
/*7.wait 1us */
udelay(1);
/*8.read conn_top1_pwr_on_ack_s =1, power on ack ready 0x10006610 [1] */
while (0 == (CONSYS_PWR_CONN_ACK_S_BIT &
CONSYS_REG_READ(conn_reg.spm_base + CONSYS_PWR_CONN_ACK_S_OFFSET)))
NULL;
/*9.release connsys ISO, conn_top1_iso_en=0 0x10006280 [1] 1'b0 */
CONSYS_REG_WRITE(conn_reg.spm_base + CONSYS_TOP1_PWR_CTRL_OFFSET,
CONSYS_REG_READ(conn_reg.spm_base + CONSYS_TOP1_PWR_CTRL_OFFSET) &
~CONSYS_SPM_PWR_ISO_S_BIT);
/*10.release SW reset of connsys, conn_ap_sw_rst_b=1 0x10006280[0] 1'b1 */
CONSYS_REG_WRITE(conn_reg.spm_base + CONSYS_TOP1_PWR_CTRL_OFFSET,
CONSYS_REG_READ(conn_reg.spm_base + CONSYS_TOP1_PWR_CTRL_OFFSET) |
CONSYS_SPM_PWR_RST_BIT);
/*disable AXI BUS protect */
CONSYS_REG_WRITE(conn_reg.topckgen_base + CONSYS_TOPAXI_PROT_EN_OFFSET,
CONSYS_REG_READ(conn_reg.topckgen_base + CONSYS_TOPAXI_PROT_EN_OFFSET) &
~CONSYS_PROT_MASK);
while (CONSYS_REG_READ(conn_reg.topckgen_base + CONSYS_TOPAXI_PROT_STA1_OFFSET) & CONSYS_PROT_MASK)
NULL;
#endif
/*11.26M is ready now, delay 10us for mem_pd de-assert */
udelay(10);
/*enable AP bus clock : connmcu_bus_pd API: enable_clock() ++?? */
#if CONSYS_AHB_CLK_MAGEMENT
#if defined(CONFIG_MTK_CLKMGR)
enable_clock(MT_CG_INFRA_CONNMCU_BUS, "WCN_MOD");
WMT_PLAT_DBG_FUNC("enable MT_CG_INFRA_CONNMCU_BUS CLK\n");
#else
iRet = clk_prepare_enable(clk_infra_conn_main);
if (iRet)
WMT_PLAT_ERR_FUNC("clk_prepare_enable(clk_infra_conn_main) fail(%d)\n", iRet);
WMT_PLAT_DBG_FUNC("[CCF]enable clk_infra_conn_main\n");
#endif /* defined(CONFIG_MTK_CLKMGR) */
#endif
/*12.poll CONNSYS CHIP ID until chipid is returned 0x18070008 */
while (retry-- > 0) {
consysHwChipId = CONSYS_REG_READ(conn_reg.mcu_base + CONSYS_CHIP_ID_OFFSET);
if ((consysHwChipId == 0x0321) || (consysHwChipId == 0x0335) || (consysHwChipId == 0x0337)) {
WMT_PLAT_INFO_FUNC("retry(%d)consys chipId(0x%08x)\n", retry, consysHwChipId);
break;
}
WMT_PLAT_ERR_FUNC("Read CONSYS chipId(0x%08x)", consysHwChipId);
msleep(20);
}
if ((0 == retry) || (0 == consysHwChipId)) {
WMT_PLAT_ERR_FUNC("Maybe has a consys power on issue,(0x%08x)\n", consysHwChipId);
WMT_PLAT_ERR_FUNC("reg dump:CONSYS_CPU_SW_RST_REG(0x%x)\n",
CONSYS_REG_READ(conn_reg.ap_rgu_base + CONSYS_CPU_SW_RST_OFFSET));
WMT_PLAT_ERR_FUNC("reg dump:CONSYS_PWR_CONN_ACK_REG(0x%x)\n",
CONSYS_REG_READ(conn_reg.spm_base + CONSYS_PWR_CONN_ACK_OFFSET));
WMT_PLAT_ERR_FUNC("reg dump:CONSYS_PWR_CONN_ACK_S_REG(0x%x)\n",
CONSYS_REG_READ(conn_reg.spm_base + CONSYS_PWR_CONN_ACK_S_OFFSET));
WMT_PLAT_ERR_FUNC("reg dump:CONSYS_TOP1_PWR_CTRL_REG(0x%x)\n",
CONSYS_REG_READ(conn_reg.spm_base + CONSYS_TOP1_PWR_CTRL_OFFSET));
}
/*13.{default no need}update ROMDEL/PATCH RAM DELSEL if needed 0x18070114 */
/*
*14.write 1 to conn_mcu_confg ACR[1] if real speed MBIST
*(default write "1") ACR 0x18070110[18] 1'b1
*if this bit is 0, HW will do memory auto test under low CPU frequence (26M Hz)
*if this bit is 0, HW will do memory auto test under high CPU frequence(138M Hz)
*inclulding low CPU frequence
*/
CONSYS_REG_WRITE(conn_reg.mcu_base + CONSYS_MCU_CFG_ACR_OFFSET,
CONSYS_REG_READ(conn_reg.mcu_base + CONSYS_MCU_CFG_ACR_OFFSET) |
CONSYS_MCU_CFG_ACR_MBIST_BIT);
#if 0
/*15.default no need,update ANA_WBG(AFE) CR if needed, CONSYS_AFE_REG */
CONSYS_REG_WRITE(CONSYS_AFE_REG_DIG_RCK_01, CONSYS_AFE_REG_DIG_RCK_01_VALUE);
CONSYS_REG_WRITE(CONSYS_AFE_REG_WBG_PLL_02, CONSYS_AFE_REG_WBG_PLL_02_VALUE);
CONSYS_REG_WRITE(CONSYS_AFE_REG_WBG_WB_TX_01, CONSYS_AFE_REG_WBG_WB_TX_01_VALUE);
#endif
/*16.deassert CONNSYS CPU SW reset 0x10007018 "[12]=1'b0 [31:24] =8'h88 (key)" */
CONSYS_REG_WRITE(conn_reg.ap_rgu_base + CONSYS_CPU_SW_RST_OFFSET,
(CONSYS_REG_READ(conn_reg.ap_rgu_base + CONSYS_CPU_SW_RST_OFFSET) &
~CONSYS_CPU_SW_RST_BIT) | CONSYS_CPU_SW_RST_CTRL_KEY);
#else /*use HADRCODE, maybe no use.. */
/*3.assert CONNSYS CPU SW reset 0x10007018 "[12]=1'b1 [31:24]=8'h88 (key)" */
CONSYS_REG_WRITE(CONSYS_CPU_SW_RST_REG,
(CONSYS_REG_READ(CONSYS_CPU_SW_RST_REG) | CONSYS_CPU_SW_RST_BIT |
CONSYS_CPU_SW_RST_CTRL_KEY));
/*turn on SPM clock gating enable PWRON_CONFG_EN 0x10006000 32'h0b160001 */
CONSYS_REG_WRITE(CONSYS_PWRON_CONFG_EN_REG, CONSYS_PWRON_CONFG_EN_VALUE);
#if CONSYS_PWR_ON_OFF_API_AVAILABLE
#if defined(CONFIG_MTK_CLKMGR)
iRet = conn_power_on(); /* consult clkmgr owner */
if (iRet)
WMT_PLAT_ERR_FUNC("conn_power_on fail(%d)\n", iRet);
WMT_PLAT_DBG_FUNC("conn_power_on ok\n");
#else
iRet = clk_prepare_enable(clk_scp_conn_main);
if (iRet)
WMT_PLAT_ERR_FUNC("clk_prepare_enable(clk_scp_conn_main) fail(%d)\n", iRet);
WMT_PLAT_DBG_FUNC("clk_prepare_enable(clk_scp_conn_main) ok\n");
#endif /* defined(CONFIG_MTK_CLKMGR) */
#else
/*2.write conn_top1_pwr_on=1, power on conn_top1 0x10006280 [2] 1'b1 */
CONSYS_REG_WRITE(CONSYS_TOP1_PWR_CTRL_REG,
CONSYS_REG_READ(CONSYS_TOP1_PWR_CTRL_REG) | CONSYS_SPM_PWR_ON_BIT);
/*3.read conn_top1_pwr_on_ack =1, power on ack ready 0x1000660C [1] */
while (0 == (CONSYS_PWR_ON_ACK_BIT & CONSYS_REG_READ(CONSYS_PWR_CONN_ACK_REG)))
NULL;
/*5.write conn_top1_pwr_on_s=1, power on conn_top1 0x10006280 [3] 1'b1 */
CONSYS_REG_WRITE(CONSYS_TOP1_PWR_CTRL_REG,
CONSYS_REG_READ(CONSYS_TOP1_PWR_CTRL_REG) | CONSYS_SPM_PWR_ON_S_BIT);
/*6.write conn_clk_dis=0, enable connsys clock 0x10006280 [4] 1'b0 */
CONSYS_REG_WRITE(CONSYS_TOP1_PWR_CTRL_REG,
CONSYS_REG_READ(CONSYS_TOP1_PWR_CTRL_REG) & ~CONSYS_CLK_CTRL_BIT);
/*7.wait 1us */
udelay(1);
/*8.read conn_top1_pwr_on_ack_s =1, power on ack ready 0x10006610 [1] */
while (0 == (CONSYS_PWR_CONN_ACK_S_BIT & CONSYS_REG_READ(CONSYS_PWR_CONN_ACK_S_REG)))
NULL;
/*9.release connsys ISO, conn_top1_iso_en=0 0x10006280 [1] 1'b0 */
CONSYS_REG_WRITE(CONSYS_TOP1_PWR_CTRL_REG,
CONSYS_REG_READ(CONSYS_TOP1_PWR_CTRL_REG) & ~CONSYS_SPM_PWR_ISO_S_BIT);
/*10.release SW reset of connsys, conn_ap_sw_rst_b=1 0x10006280[0] 1'b1 */
CONSYS_REG_WRITE(CONSYS_TOP1_PWR_CTRL_REG,
CONSYS_REG_READ(CONSYS_TOP1_PWR_CTRL_REG) | CONSYS_SPM_PWR_RST_BIT);
/*disable AXI BUS protect */
CONSYS_REG_WRITE(CONSYS_TOPAXI_PROT_EN, CONSYS_REG_READ(CONSYS_TOPAXI_PROT_EN) & ~CONSYS_PROT_MASK);
while (CONSYS_REG_READ(CONSYS_TOPAXI_PROT_STA1) & CONSYS_PROT_MASK)
NULL;
#endif
/*11.26M is ready now, delay 10us for mem_pd de-assert */
udelay(10);
/*enable AP bus clock : connmcu_bus_pd API: enable_clock() ++?? */
#if CONSYS_AHB_CLK_MAGEMENT
#if defined(CONFIG_MTK_CLKMGR)
enable_clock(MT_CG_INFRA_CONNMCU_BUS, "WCN_MOD");
WMT_PLAT_DBG_FUNC("enable MT_CG_INFRA_CONNMCU_BUS CLK\n");
#else
iRet = clk_prepare_enable(clk_infra_conn_main);
if (iRet)
WMT_PLAT_ERR_FUNC("clk_prepare_enable(clk_infra_conn_main) fail(%d)\n", iRet);
WMT_PLAT_DBG_FUNC("[CCF]enable clk_infra_conn_main\n");
#endif /* defined(CONFIG_MTK_CLKMGR) */
#endif
/*12.poll CONNSYS CHIP ID until 6752 is returned 0x18070008 32'h6752 */
while (retry-- > 0) {
WMT_PLAT_DBG_FUNC("CONSYS_CHIP_ID_REG(0x%08x)", CONSYS_REG_READ(CONSYS_CHIP_ID_REG));
consysHwChipId = CONSYS_REG_READ(CONSYS_CHIP_ID_REG);
if ((consysHwChipId == 0x0321) || (consysHwChipId == 0x0335) || (consysHwChipId == 0x0337)) {
WMT_PLAT_INFO_FUNC("retry(%d)consys chipId(0x%08x)\n", retry, consysHwChipId);
break;
}
msleep(20);
}
if ((0 == retry) || (0 == consysHwChipId)) {
WMT_PLAT_ERR_FUNC("Maybe has a consys power on issue,(0x%08x)\n", consysHwChipId);
WMT_PLAT_INFO_FUNC("reg dump:CONSYS_CPU_SW_RST_REG(0x%x)\n",
CONSYS_REG_READ(CONSYS_CPU_SW_RST_REG));
WMT_PLAT_INFO_FUNC("reg dump:CONSYS_PWR_CONN_ACK_REG(0x%x)\n",
CONSYS_REG_READ(CONSYS_PWR_CONN_ACK_REG));
WMT_PLAT_INFO_FUNC("reg dump:CONSYS_PWR_CONN_ACK_S_REG(0x%x)\n",
CONSYS_REG_READ(CONSYS_PWR_CONN_ACK_S_REG));
WMT_PLAT_INFO_FUNC("reg dump:CONSYS_TOP1_PWR_CTRL_REG(0x%x)\n",
CONSYS_REG_READ(CONSYS_TOP1_PWR_CTRL_REG));
}
/*13.{default no need}update ROMDEL/PATCH RAM DELSEL if needed 0x18070114 */
/*
*14.write 1 to conn_mcu_confg ACR[1] if real speed MBIST
*(default write "1") ACR 0x18070110[18] 1'b1
*if this bit is 0, HW will do memory auto test under low CPU frequence (26M Hz)
*if this bit is 0, HW will do memory auto test under high CPU frequence(138M Hz)
*inclulding low CPU frequence
*/
CONSYS_REG_WRITE(CONSYS_MCU_CFG_ACR_REG,
CONSYS_REG_READ(CONSYS_MCU_CFG_ACR_REG) | CONSYS_MCU_CFG_ACR_MBIST_BIT);
/*update ANA_WBG(AFE) CR. AFE setting file: AP Offset = 0x180B2000 */
#if 0
/*15.default no need,update ANA_WBG(AFE) CR if needed, CONSYS_AFE_REG */
CONSYS_REG_WRITE(CONSYS_AFE_REG_DIG_RCK_01, CONSYS_AFE_REG_DIG_RCK_01_VALUE);
CONSYS_REG_WRITE(CONSYS_AFE_REG_WBG_PLL_02, CONSYS_AFE_REG_WBG_PLL_02_VALUE);
CONSYS_REG_WRITE(CONSYS_AFE_REG_WBG_WB_TX_01, CONSYS_AFE_REG_WBG_WB_TX_01_VALUE);
#endif
/*16.deassert CONNSYS CPU SW reset 0x10007018 "[12]=1'b0 [31:24] =8'h88(key)" */
CONSYS_REG_WRITE(CONSYS_CPU_SW_RST_REG,
(CONSYS_REG_READ(CONSYS_CPU_SW_RST_REG) & ~CONSYS_CPU_SW_RST_BIT) |
CONSYS_CPU_SW_RST_CTRL_KEY);
#endif
msleep(20); /* msleep < 20ms can sleep for up to 20ms */
} else {
#ifdef CONFIG_OF
#if CONSYS_AHB_CLK_MAGEMENT
#if defined(CONFIG_MTK_CLKMGR)
disable_clock(MT_CG_INFRA_CONNMCU_BUS, "WMT_MOD");
#else
clk_disable_unprepare(clk_infra_conn_main);
WMT_PLAT_DBG_FUNC("[CCF] clk_disable_unprepare(clk_infra_conn_main) calling\n");
#endif /* defined(CONFIG_MTK_CLKMGR) */
#endif
#if CONSYS_PWR_ON_OFF_API_AVAILABLE
#if defined(CONFIG_MTK_CLKMGR)
/*power off connsys by API (MT6582, MT6572 are different) API: conn_power_off() */
iRet = conn_power_off(); /* consult clkmgr owner */
if (iRet)
WMT_PLAT_ERR_FUNC("conn_power_off fail(%d)\n", iRet);
WMT_PLAT_DBG_FUNC("conn_power_off ok\n");
#else
clk_disable_unprepare(clk_scp_conn_main);
WMT_PLAT_DBG_FUNC("clk_disable_unprepare(clk_scp_conn_main) calling\n");
#endif /* defined(CONFIG_MTK_CLKMGR) */
#else
{
INT32 count = 0;
CONSYS_REG_WRITE(conn_reg.topckgen_base + CONSYS_TOPAXI_PROT_EN_OFFSET,
CONSYS_REG_READ(conn_reg.topckgen_base + CONSYS_TOPAXI_PROT_EN_OFFSET) |
CONSYS_PROT_MASK);
while ((CONSYS_REG_READ(conn_reg.topckgen_base + CONSYS_TOPAXI_PROT_STA1_OFFSET) &
CONSYS_PROT_MASK) != CONSYS_PROT_MASK) {
count++;
if (count > 1000)
break;
}
}
/*release connsys ISO, conn_top1_iso_en=1 0x10006280 [1] 1'b1 */
CONSYS_REG_WRITE(conn_reg.spm_base + CONSYS_TOP1_PWR_CTRL_OFFSET,
CONSYS_REG_READ(conn_reg.spm_base + CONSYS_TOP1_PWR_CTRL_OFFSET) |
CONSYS_SPM_PWR_ISO_S_BIT);
/*assert SW reset of connsys, conn_ap_sw_rst_b=0 0x10006280[0] 1'b0 */
CONSYS_REG_WRITE(conn_reg.spm_base + CONSYS_TOP1_PWR_CTRL_OFFSET,
CONSYS_REG_READ(conn_reg.spm_base + CONSYS_TOP1_PWR_CTRL_OFFSET) &
~CONSYS_SPM_PWR_RST_BIT);
/*write conn_clk_dis=1, disable connsys clock 0x10006280 [4] 1'b1 */
CONSYS_REG_WRITE(conn_reg.spm_base + CONSYS_TOP1_PWR_CTRL_OFFSET,
CONSYS_REG_READ(conn_reg.spm_base + CONSYS_TOP1_PWR_CTRL_OFFSET) |
CONSYS_CLK_CTRL_BIT);
/*wait 1us */
udelay(1);
/*write conn_top1_pwr_on=0, power off conn_top1 0x10006280 [3:2] 2'b00 */
CONSYS_REG_WRITE(conn_reg.spm_base + CONSYS_TOP1_PWR_CTRL_OFFSET,
CONSYS_REG_READ(conn_reg.spm_base + CONSYS_TOP1_PWR_CTRL_OFFSET) &
~(CONSYS_SPM_PWR_ON_BIT | CONSYS_SPM_PWR_ON_S_BIT));
#endif
#else
#if CONSYS_PWR_ON_OFF_API_AVAILABLE
#if CONSYS_AHB_CLK_MAGEMENT
#if defined(CONFIG_MTK_CLKMGR)
disable_clock(MT_CG_INFRA_CONNMCU_BUS, "WMT_MOD");
#else
clk_disable_unprepare(clk_infra_conn_main);
#endif /* defined(CONFIG_MTK_CLKMGR) */
#endif
#if defined(CONFIG_MTK_CLKMGR)
/*power off connsys by API: conn_power_off() */
iRet = conn_power_off(); /* consult clkmgr owner */
if (iRet)
WMT_PLAT_ERR_FUNC("conn_power_off fail(%d)\n", iRet);
WMT_PLAT_DBG_FUNC("conn_power_off ok\n");
#else
clk_disable_unprepare(clk_scp_conn_main);
WMT_PLAT_DBG_FUNC("clk_disable_unprepare(clk_scp_conn_main) calling\n");
#endif /* defined(CONFIG_MTK_CLKMGR) */
#else
{
INT32 count = 0;
CONSYS_REG_WRITE(CONSYS_TOPAXI_PROT_EN,
CONSYS_REG_READ(CONSYS_TOPAXI_PROT_EN) | CONSYS_PROT_MASK);
while ((CONSYS_REG_READ(CONSYS_TOPAXI_PROT_STA1) & CONSYS_PROT_MASK) != CONSYS_PROT_MASK) {
count++;
if (count > 1000)
break;
}
}
/*release connsys ISO, conn_top1_iso_en=1 0x10006280 [1] 1'b1 */
CONSYS_REG_WRITE(CONSYS_TOP1_PWR_CTRL_REG,
CONSYS_REG_READ(CONSYS_TOP1_PWR_CTRL_REG) | CONSYS_SPM_PWR_ISO_S_BIT);
/*assert SW reset of connsys, conn_ap_sw_rst_b=0 0x10006280[0] 1'b0 */
CONSYS_REG_WRITE(CONSYS_TOP1_PWR_CTRL_REG,
CONSYS_REG_READ(CONSYS_TOP1_PWR_CTRL_REG) & ~CONSYS_SPM_PWR_RST_BIT);
/*write conn_clk_dis=1, disable connsys clock 0x10006280 [4] 1'b1 */
CONSYS_REG_WRITE(CONSYS_TOP1_PWR_CTRL_REG,
CONSYS_REG_READ(CONSYS_TOP1_PWR_CTRL_REG) | CONSYS_CLK_CTRL_BIT);
/*wait 1us */
udelay(1);
/*write conn_top1_pwr_on=0, power off conn_top1 0x10006280 [3:2] 2'b00 */
CONSYS_REG_WRITE(CONSYS_TOP1_PWR_CTRL_REG, CONSYS_REG_READ(CONSYS_TOP1_PWR_CTRL_REG) &
~(CONSYS_SPM_PWR_ON_BIT | CONSYS_SPM_PWR_ON_S_BIT));
#endif
#endif
#if CONSYS_PMIC_CTRL_ENABLE
if (co_clock_type) {
/*VCN28 has been turned off by GPS OR FM */
#if CONSYS_CLOCK_BUF_CTRL
clk_buf_ctrl(CLK_BUF_CONN, 0);
#endif
} else {
pmic_set_register_value(PMIC_RG_VCN28_ON_CTRL, 0);
/*turn off VCN28 LDO (with PMIC_WRAP API)" */
#if defined(CONFIG_MTK_PMIC_LEGACY)
hwPowerDown(MT6328_POWER_LDO_VCN28, "wcn_drv");
#else
if (reg_VCN28) {
if (regulator_disable(reg_VCN28))
WMT_PLAT_ERR_FUNC("disable VCN_2V8 fail!\n");
else
WMT_PLAT_DBG_FUNC("disable VCN_2V8 ok\n");
}
#endif
}
/*AP power off MT6625L VCN_1V8 LDO */
pmic_set_register_value(PMIC_RG_VCN18_ON_CTRL, 0);
#if defined(CONFIG_MTK_PMIC_LEGACY)
hwPowerDown(MT6328_POWER_LDO_VCN18, "wcn_drv");
#else
if (reg_VCN18) {
if (regulator_disable(reg_VCN18))
WMT_PLAT_ERR_FUNC("disable VCN_1V8 fail!\n");
else
WMT_PLAT_DBG_FUNC("disable VCN_1V8 ok\n");
}
#endif
#endif
}
WMT_PLAT_WARN_FUNC("CONSYS-HW-REG-CTRL(0x%08x),finish\n", on);
return 0;
}
INT32 mtk_wcn_consys_hw_reg_ctrl(UINT32 on,UINT32 co_clock_en)
{
INT32 iRet = -1;
UINT32 retry = 10;
UINT32 consysHwChipId = 0;
WMT_PLAT_INFO_FUNC("CONSYS-HW-REG-CTRL(0x%08x),start\n",on);
if(on)
{
#if CONSYS_PMIC_CTRL_ENABLE
/*need PMIC driver provide new API protocol before 1/18/2013*/
/*1.Power on MT6323 VCN_1V8 LDO<--<VCN_1V8>-->write 0 to 0x512[1], write 1 to 0x512[14]*/
upmu_set_vcn_1v8_lp_mode_set(0);
//upmu_set_rg_vcn_1v8_en(1);
/*will be replaced by hwpoweron just as below*/
hwPowerOn(MT6323_POWER_LDO_VCN_1V8,VOL_DEFAULT,"MOD_WMT");
if(co_clock_en)
{
/*2.set VCN_28 to SW control mode<--<VCN28_ON_CTRL>-->write 0 to 0x41C[14]*/
upmu_set_vcn28_on_ctrl(0);
}
else
{
/*2.1.switch VCN28 to HW control mode<--<VCN28_ON_CTRL>-->write 1 to 0x41C[14]*/
upmu_set_vcn28_on_ctrl(1);
/*2.2.turn on VCN28LDO<--<RG_VCN28_EN>-->write 1 to 0x41C[12]*/
//upmu_set_rg_vcn28_en(1);
/*will be replaced by hwpoweron just as below*/
hwPowerOn(MT6323_POWER_LDO_VCN28,VOL_DEFAULT,"MOD_WMT");
}
#endif
/*mask this action and put it into FW patch for resolve ALPS00544691*/
#if 0
/*1.assert CONSYS CPU SW reset, <CONSYS_CPU_SW_RST_REG>, [12] = 1'b1, [31:24]=8'h88(key)--> CONSYS_CPU_SW_RST_BIT | CONSYS_CPU_SW_RST_CTRL_KEY*/
CONSYS_SET_BIT(CONSYS_CPU_SW_RST_REG, CONSYS_CPU_SW_RST_BIT | CONSYS_CPU_SW_RST_CTRL_KEY);
WMT_PLAT_DBG_FUNC("reg uump:CONSYS_CPU_SW_RST_REG(0x%x)\n",CONSYS_REG_READ(CONSYS_CPU_SW_RST_REG));
#endif
#if 0
/*turn on top clock gating enable*/
CONSYS_REG_WRITE(CONSYS_TOP_CLKCG_CLR_REG,CONSYS_REG_READ(CONSYS_TOP_CLKCG_CLR_REG) | CONSYS_TOP_CLKCG_BIT);
WMT_PLAT_DBG_FUNC("reg dump:CONSYS_TOP_CLKCG_CLR_REG(0x%x)\n",CONSYS_REG_READ(CONSYS_TOP_CLKCG_CLR_REG));
/*turn on SPM clock gating enable*/
CONSYS_REG_WRITE(CONSYS_PWRON_CONFG_EN_REG, CONSYS_PWRON_CONFG_EN_VALUE);
WMT_PLAT_DBG_FUNC("reg dump:CONSYS_PWRON_CONFG_EN_REG(0x%x)\n",CONSYS_REG_READ(CONSYS_PWRON_CONFG_EN_REG));
#endif
/*use colck manger API to control MTCMOS*/
conn_power_on();
WMT_PLAT_INFO_FUNC("reg dump:CONSYS_PWR_CONN_ACK_REG(0x%x)\n",CONSYS_REG_READ(CONSYS_PWR_CONN_ACK_REG));
WMT_PLAT_INFO_FUNC("reg dump:CONSYS_PWR_CONN_ACK_S_REG(0x%x)\n",CONSYS_REG_READ(CONSYS_PWR_CONN_ACK_S_REG));
WMT_PLAT_INFO_FUNC("reg dump:CONSYS_TOP1_PWR_CTRL_REG(0x%x)\n",CONSYS_REG_READ(CONSYS_TOP1_PWR_CTRL_REG));
/*11.delay 10us, 26M is ready*/
udelay(10);
enable_clock(MT_CG_INFRA_CONNMCU, "WMT_MOD");
/*12.poll CONSYS CHIP until MT6582/MT6572 is returned, <CONSYS_CHIP_ID_REG>, 32'h6582/32'h6572 */
/*what does HW do, why we need to polling this register?*/
while (retry-- > 0)
{
WMT_PLAT_DBG_FUNC("CONSYS_CHIP_ID_REG(0x%08x)",CONSYS_REG_READ(CONSYS_CHIP_ID_REG));
consysHwChipId = CONSYS_REG_READ(CONSYS_CHIP_ID_REG);
if((consysHwChipId == 0x6582) || (consysHwChipId == 0x6572))
{
WMT_PLAT_INFO_FUNC("retry(%d)consys chipId(0x%08x)\n", retry,consysHwChipId);
break;
}
msleep(20);
}
/*mask this action and put it into FW patch for resolve ALPS00544691*/
#if 0
/*13.{default no need}update ROMDEL/PATCH RAM DELSEL if needed, <CONSYS_ROM_RAM_DELSEL_REG>*/
/*14.write 1 to conn_mcu_config ACR[1] if real speed MBIST (default write "1"), <CONSYS_MCU_CFG_ACR_REG>,[18]1'b1-->CONSYS_MCU_CFG_ACR_MBIST_BIT*/
/*if this bit is 0, HW will do memory auto test under low CPU frequence (26M Hz)*/
/*if this bit is 0, HW will do memory auto test under high CPU frequence(138M Hz) inclulding low CPU frequence*/
CONSYS_SET_BIT(CONSYS_MCU_CFG_ACR_REG, CONSYS_MCU_CFG_ACR_MBIST_BIT);
/*15.{default no need, Analog HW will inform if this need to be update or not 1 week after IC sample back}
update ANA_WBG(AFE) CR if needed, CONSYS_AFE_REG */
CONSYS_REG_WRITE(CONSYS_AFE_REG_DIG_RCK_01,CONSYS_AFE_REG_DIG_RCK_01_VALUE);
CONSYS_REG_WRITE(CONSYS_AFE_REG_WBG_PLL_02,CONSYS_AFE_REG_WBG_PLL_02_VALUE);
CONSYS_REG_WRITE(CONSYS_AFE_REG_WBG_WB_TX_01,CONSYS_AFE_REG_WBG_WB_TX_01_VALUE);
/*16.deassert CONSYS CPU SW reset, <CONSYS_CPU_SW_RST_REG>, [12] = 1'b0, [31:24]=8'h88(key)*/
CONSYS_CLR_BIT_WITH_KEY(CONSYS_CPU_SW_RST_REG, CONSYS_CPU_SW_RST_BIT , CONSYS_CPU_SW_RST_CTRL_KEY);
#endif
msleep(5);
iRet = 0;
}else{
disable_clock(MT_CG_INFRA_CONNMCU, "WMT_MOD");
/*New: use colck manger API to control MTCMOS*/
conn_power_off();
#if CONSYS_PMIC_CTRL_ENABLE
/*set VCN_28 to SW control mode*/
upmu_set_vcn28_on_ctrl(0);
/*turn off VCN28 LDO*/
//upmu_set_rg_vcn28_en(0);
/*will be replaced by hwPowerOff*/
hwPowerDown(MT6323_POWER_LDO_VCN28,"MOD_WMT");
/*power off MT6627 VWCN_1V8 LDO*/
upmu_set_vcn_1v8_lp_mode_set(0);
//upmu_set_rg_vcn_1v8_en(0);
/*will be replaced by hwPowerOff*/
hwPowerDown(MT6323_POWER_LDO_VCN_1V8,"MOD_WMT");
#endif
iRet = 0;
}
WMT_PLAT_INFO_FUNC("CONSYS-HW-REG-CTRL(0x%08x),finish\n",on);
return iRet;
}
