/* MT6306 GPIO7 is GPIO_GPS_LNA_EN, for K2 common phone pin modification */
static INT32 wmt_plat_gps_lna_ctrl(ENUM_PIN_STATE state)
{
#ifdef GPIO_GPS_LNA_PIN
switch (state) {
case PIN_STA_INIT:
case PIN_STA_DEINIT:
WMT_PLAT_ERR_FUNC("Gps LNA pin ctrl %d!\n", state);
mt6306_set_gpio_dir(GPIO_GPS_LNA_PIN, GPIO_DIR_OUT);
mt6306_set_gpio_out(GPIO_GPS_LNA_PIN, GPIO_OUT_ZERO);
break;
case PIN_STA_OUT_H:
WMT_PLAT_ERR_FUNC("Gps LNA pin output high!\n");
mt6306_set_gpio_out(GPIO_GPS_LNA_PIN, GPIO_OUT_ONE);
break;
case PIN_STA_OUT_L:
WMT_PLAT_ERR_FUNC("Gps LNA pin output low!\n");
mt6306_set_gpio_out(GPIO_GPS_LNA_PIN, GPIO_OUT_ZERO);
break;
default:
WMT_PLAT_WARN_FUNC("%d mode not defined for gps lna pin !!!\n", state);
break;
}
return 0;
#else
WMT_PLAT_WARN_FUNC("host gps lna pin not defined!!!\n");
return 0;
#endif
}
static INT32
wmt_plat_gps_lna_ctrl (
ENUM_PIN_STATE state
)
{
#ifdef GPIO_GPS_LNA_PIN
switch (state) {
case PIN_STA_INIT:
case PIN_STA_DEINIT:
mt_set_gpio_pull_enable(GPIO_GPS_LNA_PIN, GPIO_PULL_DISABLE);
mt_set_gpio_dir(GPIO_GPS_LNA_PIN, GPIO_DIR_OUT);
mt_set_gpio_mode(GPIO_GPS_LNA_PIN, GPIO_GPS_LNA_PIN_M_GPIO);
mt_set_gpio_out(GPIO_GPS_LNA_PIN, GPIO_OUT_ZERO);
break;
case PIN_STA_OUT_H:
mt_set_gpio_out(GPIO_GPS_LNA_PIN, GPIO_OUT_ONE);
break;
case PIN_STA_OUT_L:
mt_set_gpio_out(GPIO_GPS_LNA_PIN, GPIO_OUT_ZERO);
break;
default:
WMT_PLAT_WARN_FUNC("%d mode not defined for gps lna pin !!!\n", state);
break;
}
return 0;
#else
WMT_PLAT_WARN_FUNC("host gps lna pin not defined!!!\n");
return 0;
#endif
}
INT32 mtk_wcn_consys_hw_restore(struct device *device)
{
UINT32 addrPhy = 0;
if (gConEmiPhyBase) {
#if CONSYS_EMI_MPU_SETTING
/*set MPU for EMI share Memory */
WMT_PLAT_INFO_FUNC("setting MPU for EMI share memory\n");
#if defined(CONFIG_ARCH_MT6735)
emi_mpu_set_region_protection(gConEmiPhyBase + SZ_1M / 2,
gConEmiPhyBase + SZ_1M - 1,
13,
SET_ACCESS_PERMISSON(FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
FORBIDDEN, NO_PROTECTION, FORBIDDEN, NO_PROTECTION));
#elif defined(CONFIG_ARCH_MT6735M)
emi_mpu_set_region_protection(gConEmiPhyBase,
gConEmiPhyBase + SZ_1M - 1,
6,
SET_ACCESS_PERMISSON(FORBIDDEN, NO_PROTECTION, FORBIDDEN,
NO_PROTECTION));
#elif defined(CONFIG_ARCH_MT6753)
emi_mpu_set_region_protection(gConEmiPhyBase + SZ_1M / 2,
gConEmiPhyBase + SZ_1M - 1,
13,
SET_ACCESS_PERMISSON(FORBIDDEN, FORBIDDEN, FORBIDDEN,
FORBIDDEN, FORBIDDEN, NO_PROTECTION, FORBIDDEN, NO_PROTECTION));
#else
WMT_PLAT_WARN_FUNC("not define platform config\n");
#endif
#endif
/*consys to ap emi remapping register:10000320, cal remapping address */
addrPhy = (gConEmiPhyBase & 0xFFF00000) >> 20;
/*enable consys to ap emi remapping bit12 */
addrPhy = addrPhy | 0x1000;
CONSYS_REG_WRITE(conn_reg.topckgen_base + CONSYS_EMI_MAPPING_OFFSET,
CONSYS_REG_READ(conn_reg.topckgen_base + CONSYS_EMI_MAPPING_OFFSET) | addrPhy);
WMT_PLAT_INFO_FUNC("CONSYS_EMI_MAPPING dump in restore cb(0x%08x)\n",
CONSYS_REG_READ(conn_reg.topckgen_base + CONSYS_EMI_MAPPING_OFFSET));
#if 1
pEmibaseaddr = ioremap_nocache(gConEmiPhyBase + SZ_1M / 2, CONSYS_EMI_MEM_SIZE);
#else
pEmibaseaddr = ioremap_nocache(CONSYS_EMI_AP_PHY_BASE, CONSYS_EMI_MEM_SIZE);
#endif
if (pEmibaseaddr) {
WMT_PLAT_WARN_FUNC("EMI mapping OK(0x%p)\n", pEmibaseaddr);
memset_io(pEmibaseaddr, 0, CONSYS_EMI_MEM_SIZE);
} else {
WMT_PLAT_ERR_FUNC("EMI mapping fail\n");
}
} else {
INT32 wmt_plat_wake_lock_ctrl(ENUM_WL_OP opId)
{
#ifdef CFG_WMT_WAKELOCK_SUPPORT
static INT32 counter;
INT32 status;
INT32 ret = 0;
ret = mutex_lock_killable(&gOsSLock);
if (ret) {
WMT_PLAT_ERR_FUNC("--->lock gOsSLock failed, ret=%d\n", ret);
return ret;
}
if (WL_OP_GET == opId)
++counter;
else if (WL_OP_PUT == opId)
--counter;
mutex_unlock(&gOsSLock);
if (WL_OP_GET == opId && counter == 1) {
#ifdef CONFIG_PM_WAKELOCKS
__pm_stay_awake(&wmtWakeLock);
status = wmtWakeLock.active;
#else
wake_lock(&wmtWakeLock);
status = wake_lock_active(&wmtWakeLock);
#endif
WMT_PLAT_DBG_FUNC("WMT-PLAT: after wake_lock(%d), counter(%d)\n", status, counter);
} else if (WL_OP_PUT == opId && counter == 0) {
#ifdef CONFIG_PM_WAKELOCKS
__pm_relax(&wmtWakeLock);
status = wmtWakeLock.active;
#else
wake_unlock(&wmtWakeLock);
status = wake_lock_active(&wmtWakeLock);
#endif
WMT_PLAT_DBG_FUNC("WMT-PLAT: after wake_unlock(%d), counter(%d)\n", status, counter);
} else {
#ifdef CONFIG_PM_WAKELOCKS
status = wmtWakeLock.active;
#else
status = wake_lock_active(&wmtWakeLock);
#endif
WMT_PLAT_WARN_FUNC("WMT-PLAT: wakelock status(%d), counter(%d)\n", status, counter);
}
return 0;
#else
WMT_PLAT_WARN_FUNC("WMT-PLAT: host awake function is not supported.\n");
return 0;
#endif
}
INT32 wmt_plat_get_tdm_antsel_index(VOID)
{
INT32 ret = -1;
#ifdef GPIO_TDM_REQ
UINT32 i;
UINT32 tbl_num = sizeof(mtk_wcn_tdm_req_info_tbls) / sizeof(mtk_wcn_tdm_req_info_tbls[0]);
UINT32 gpio_num = GPIO_TDM_REQ & 0x7fffffff;
for(i = 0; i < tbl_num; i++)
{
if(gpio_num == mtk_wcn_tdm_req_info_tbls[i].gpio_number)
break;
}
if(i == tbl_num)
{
WMT_PLAT_WARN_FUNC("can not get antsel index of GPIO_TDM_REQ(GPIO%d)\n",
gpio_num);
ret = -2;
}else
{
ret = mtk_wcn_tdm_req_info_tbls[i].ant_sel_index;
WMT_PLAT_INFO_FUNC("current GPIO_TDM_REQ(GPIO%d) antsel index is %d\n",
gpio_num,ret);
}
#else
WMT_PLAT_INFO_FUNC("GPIO_TDM_REQ is not defined\n");
#endif
return ret;
}
INT32 wmt_plat_pwr_ctrl (
ENUM_FUNC_STATE state
)
{
INT32 ret = -1;
switch (state) {
case FUNC_ON:
// TODO:[ChangeFeature][George] always output this or by request throuth /proc or sysfs?
wmt_plat_dump_pin_conf();
ret = mtk_wcn_consys_hw_pwr_on(gCoClockFlag);
break;
case FUNC_OFF:
ret = mtk_wcn_consys_hw_pwr_off();
break;
case FUNC_RST:
ret = mtk_wcn_consys_hw_rst(gCoClockFlag);
break;
case FUNC_STAT:
ret = mtk_wcn_consys_hw_state_show();
break;
default:
WMT_PLAT_WARN_FUNC("WMT-PLAT:Warnning, invalid state(%d) in pwr_ctrl\n", state);
break;
}
return ret;
}
INT32 wmt_plat_wake_lock_ctrl(ENUM_WL_OP opId)
{
#ifdef CFG_WMT_WAKELOCK_SUPPORT
static INT32 counter = 0;
INT32 ret = 0;
ret = mutex_lock_killable( &gOsSLock);
if (ret) {
WMT_PLAT_ERR_FUNC("--->lock gOsSLock failed, ret=%d\n", ret);
return ret;
}
if (WL_OP_GET == opId)
{
++counter;
}else if (WL_OP_PUT == opId)
{
--counter;
}
mutex_unlock( &gOsSLock);
if (WL_OP_GET == opId && counter == 1)
{
wake_lock(&wmtWakeLock);
WMT_PLAT_DBG_FUNC("WMT-PLAT: after wake_lock(%d), counter(%d)\n", wake_lock_active(&wmtWakeLock), counter);
}
else if (WL_OP_PUT == opId && counter == 0)
{
wake_unlock(&wmtWakeLock);
WMT_PLAT_DBG_FUNC("WMT-PLAT: after wake_unlock(%d), counter(%d)\n", wake_lock_active(&wmtWakeLock), counter);
}
else
{
WMT_PLAT_WARN_FUNC("WMT-PLAT: wakelock status(%d), counter(%d)\n", wake_lock_active(&wmtWakeLock), counter);
}
return 0;
#else
WMT_PLAT_WARN_FUNC("WMT-PLAT: host awake function is not supported.");
return 0;
#endif
}
/*!
* \brief audio control callback function for CMB_STUB on ALPS
*
* A platform function required for dynamic binding with CMB_STUB on ALPS.
*
* \param state desired audio interface state to use
* \param flag audio interface control options
*
* \retval 0 operation success
* \retval -1 invalid parameters
* \retval < 0 error for operation fail
*/
INT32 wmt_plat_audio_ctrl(CMB_STUB_AIF_X state, CMB_STUB_AIF_CTRL ctrl)
{
INT32 iRet = 0;
/* input sanity check */
if ((CMB_STUB_AIF_MAX <= state)
|| (CMB_STUB_AIF_CTRL_MAX <= ctrl)) {
return -1;
}
iRet = 0;
/* set host side first */
switch (state) {
case CMB_STUB_AIF_0:
/* BT_PCM_OFF & FM line in/out */
iRet += wmt_plat_gpio_ctrl(PIN_I2S_GRP, PIN_STA_DEINIT);
break;
case CMB_STUB_AIF_1:
iRet += wmt_plat_gpio_ctrl(PIN_I2S_GRP, PIN_STA_DEINIT);
break;
case CMB_STUB_AIF_2:
iRet += wmt_plat_gpio_ctrl(PIN_I2S_GRP, PIN_STA_INIT);
break;
case CMB_STUB_AIF_3:
iRet += wmt_plat_gpio_ctrl(PIN_I2S_GRP, PIN_STA_INIT);
break;
default:
/* FIXME: move to cust folder? */
WMT_PLAT_ERR_FUNC("invalid state [%d]\n", state);
iRet = -1;
break;
}
if (CMB_STUB_AIF_CTRL_EN == ctrl) {
WMT_PLAT_INFO_FUNC("call chip aif setting\n");
/* need to control chip side GPIO */
if (NULL != wmt_plat_audio_if_cb) {
iRet += (*wmt_plat_audio_if_cb) (state, MTK_WCN_BOOL_FALSE);
} else {
WMT_PLAT_WARN_FUNC("wmt_plat_audio_if_cb is not registered\n");
iRet -= 1;
}
} else {
WMT_PLAT_INFO_FUNC("skip chip aif setting\n");
}
return iRet;
}
INT32 wmt_plat_get_dump_info(UINT32 offset)
{
PUINT8 p_virtual_addr = NULL;
p_virtual_addr = wmt_plat_get_emi_virt_add(offset);
if (!p_virtual_addr) {
WMT_PLAT_ERR_FUNC("get virtual address fail\n");
return -1;
}
WMT_PLAT_WARN_FUNC("connsys_reg_read (0x%x), (0x%p), (0x%x)\n", CONSYS_REG_READ(p_virtual_addr), p_virtual_addr,
offset);
return CONSYS_REG_READ(p_virtual_addr);
}
static VOID wmt_plat_bgf_eirq_cb(VOID)
{
#if CFG_WMT_PS_SUPPORT
/* #error "need to disable EINT here" */
/* wmt_lib_ps_irq_cb(); */
if (NULL != wmt_plat_bgf_irq_cb)
(*(wmt_plat_bgf_irq_cb)) ();
else
WMT_PLAT_WARN_FUNC("WMT-PLAT: wmt_plat_bgf_irq_cb not registered\n");
#else
return;
#endif
}
INT32 wmt_plat_gpio_ctrl(ENUM_PIN_ID id, ENUM_PIN_STATE state)
{
if ((PIN_ID_MAX > id)
&& (PIN_STA_MAX > state)) {
/* TODO: [FixMe][GeorgeKuo] do sanity check to const function table when init and skip checking here */
if (gfp_set_pin_table[id])
return (*(gfp_set_pin_table[id])) (state); /* .handler */
WMT_PLAT_WARN_FUNC("WMT-PLAT: null fp for gpio_ctrl(%d)\n", id);
return -2;
}
return -1;
}
INT32 wmt_plat_i2s_ctrl(ENUM_PIN_STATE state)
{
/* TODO: [NewFeature][GeorgeKuo]: GPIO_I2Sx is changed according to different project. */
/* TODO: provide a translation table in board_custom.h for different ALPS project customization. */
#if defined(CONFIG_MTK_GPIO_LEGACY)
#if defined(FM_DIGITAL_INPUT) || defined(FM_DIGITAL_OUTPUT)
#if defined(GPIO_COMBO_I2S_CK_PIN)
switch (state) {
case PIN_STA_INIT:
case PIN_STA_MUX:
mt_set_gpio_mode(GPIO_COMBO_I2S_CK_PIN, GPIO_COMBO_I2S_CK_PIN_M_I2S0_CK);
mt_set_gpio_mode(GPIO_COMBO_I2S_WS_PIN, GPIO_COMBO_I2S_WS_PIN_M_I2S0_WS);
mt_set_gpio_mode(GPIO_COMBO_I2S_DAT_PIN, GPIO_COMBO_I2S_DAT_PIN_M_I2S0_DAT);
WMT_PLAT_DBG_FUNC("WMT-PLAT:I2S init (I2S0 system)\n");
break;
case PIN_STA_IN_L:
case PIN_STA_DEINIT:
mt_set_gpio_mode(GPIO_COMBO_I2S_CK_PIN, GPIO_COMBO_I2S_CK_PIN_M_GPIO);
mt_set_gpio_dir(GPIO_COMBO_I2S_CK_PIN, GPIO_DIR_OUT);
mt_set_gpio_out(GPIO_COMBO_I2S_CK_PIN, GPIO_OUT_ZERO);
mt_set_gpio_mode(GPIO_COMBO_I2S_WS_PIN, GPIO_COMBO_I2S_WS_PIN_M_GPIO);
mt_set_gpio_dir(GPIO_COMBO_I2S_WS_PIN, GPIO_DIR_OUT);
mt_set_gpio_out(GPIO_COMBO_I2S_WS_PIN, GPIO_OUT_ZERO);
mt_set_gpio_mode(GPIO_COMBO_I2S_DAT_PIN, GPIO_COMBO_I2S_DAT_PIN_M_GPIO);
mt_set_gpio_dir(GPIO_COMBO_I2S_DAT_PIN, GPIO_DIR_OUT);
mt_set_gpio_out(GPIO_COMBO_I2S_DAT_PIN, GPIO_OUT_ZERO);
WMT_PLAT_DBG_FUNC("WMT-PLAT:I2S deinit (out 0)\n");
break;
default:
WMT_PLAT_WARN_FUNC("WMT-PLAT:Warnning, invalid state(%d) on I2S Group\n", state);
break;
}
#else
WMT_PLAT_ERR_FUNC("[MT6620]Error:FM digital mode set, but no I2S GPIOs defined\n");
#endif
#else
WMT_PLAT_INFO_FUNC
("[MT6620]warnning:FM digital mode is not set, no I2S GPIO settings should be modified by combo driver\n");
#endif
#else /* #if defined(CONFIG_MTK_GPIO_LEGACY) */
#endif
return 0;
}
INT32
wmt_plat_bgf_eint_ctrl (
ENUM_PIN_STATE state
)
{
#ifdef GPIO_COMBO_BGF_EINT_PIN
switch(state)
{
case PIN_STA_INIT:
/*set to gpio input low, pull down enable*/
mt_set_gpio_mode(GPIO_COMBO_BGF_EINT_PIN, GPIO_COMBO_BGF_EINT_PIN_M_GPIO);
mt_set_gpio_dir(GPIO_COMBO_BGF_EINT_PIN, GPIO_DIR_IN);
mt_set_gpio_pull_select(GPIO_COMBO_BGF_EINT_PIN, GPIO_PULL_DOWN);
mt_set_gpio_pull_enable(GPIO_COMBO_BGF_EINT_PIN, GPIO_PULL_ENABLE);
WMT_PLAT_DBG_FUNC("WMT-PLAT:BGFInt init(in pd) \n");
break;
case PIN_STA_MUX:
mt_set_gpio_mode(GPIO_COMBO_BGF_EINT_PIN, GPIO_COMBO_BGF_EINT_PIN_M_GPIO);
mt_set_gpio_pull_enable(GPIO_COMBO_BGF_EINT_PIN, GPIO_PULL_ENABLE);
mt_set_gpio_pull_select(GPIO_COMBO_BGF_EINT_PIN, GPIO_PULL_UP);
mt_set_gpio_mode(GPIO_COMBO_BGF_EINT_PIN, GPIO_COMBO_BGF_EINT_PIN_M_EINT);
WMT_PLAT_DBG_FUNC("WMT-PLAT:BGFInt mux (eint) \n");
break;
case PIN_STA_IN_L:
case PIN_STA_DEINIT:
/*set to gpio input low, pull down enable*/
mt_set_gpio_mode(GPIO_COMBO_BGF_EINT_PIN, GPIO_COMBO_BGF_EINT_PIN_M_GPIO);
mt_set_gpio_dir(GPIO_COMBO_BGF_EINT_PIN, GPIO_DIR_IN);
mt_set_gpio_pull_select(GPIO_COMBO_BGF_EINT_PIN, GPIO_PULL_DOWN);
mt_set_gpio_pull_enable(GPIO_COMBO_BGF_EINT_PIN, GPIO_PULL_ENABLE);
WMT_PLAT_DBG_FUNC("WMT-PLAT:BGFInt deinit(in pd) \n");
break;
default:
WMT_PLAT_WARN_FUNC("WMT-PLAT:Warnning, invalid state(%d) on BGF EINT\n", state);
break;
}
#else
WMT_PLAT_INFO_FUNC("WMT-PLAT:BGF EINT not defined\n");
#endif
return 0;
}
INT32 wmt_plat_soc_paldo_ctrl(ENUM_PALDO_TYPE ePt,ENUM_PALDO_OP ePo)
{
INT32 iRet = 0;
switch(ePt){
case BT_PALDO:
iRet = mtk_wcn_consys_hw_bt_paldo_ctrl(ePo);
break;
case WIFI_PALDO:
iRet = mtk_wcn_consys_hw_wifi_paldo_ctrl(ePo);
break;
case FM_PALDO:
case GPS_PALDO:
iRet = mtk_wcn_consys_hw_vcn28_ctrl(ePo);
break;
default:
WMT_PLAT_WARN_FUNC("WMT-PLAT:Warnning, invalid type(%d) in palod_ctrl\n", ePt);
break;
}
return iRet;
}
INT32
wmt_plat_eirq_ctrl (
ENUM_PIN_ID id,
ENUM_PIN_STATE state
)
{
INT32 iret;
// TODO: [ChangeFeature][GeorgeKuo]: use another function to handle this, as done in gpio_ctrls
if ( (PIN_STA_INIT != state )
&& (PIN_STA_DEINIT != state )
&& (PIN_STA_EINT_EN != state )
&& (PIN_STA_EINT_DIS != state ) ) {
WMT_PLAT_WARN_FUNC("WMT-PLAT:invalid PIN_STATE(%d) in eirq_ctrl for PIN(%d)\n", state, id);
return -1;
}
iret = -2;
switch (id) {
case PIN_BGF_EINT:
#if 1
if (PIN_STA_INIT == state) {
iret = request_irq(MT_CONN2AP_BTIF_WAKEUP_IRQ_ID,
(irq_handler_t)wmt_plat_bgf_irq_isr,
IRQF_TRIGGER_LOW,
"BTIF_WAKEUP_IRQ",
NULL);
if(iret)
{
WMT_PLAT_ERR_FUNC("request_irq fail,irq_no(%d),iret(%d)\n",MT_CONN2AP_BTIF_WAKEUP_IRQ_ID,iret);
return iret;
}
gbgfIrqBle.counter = 1;
}
else if (PIN_STA_EINT_EN == state) {
spin_lock_irqsave(&gbgfIrqBle.lock,gbgfIrqBle.flags);
if(gbgfIrqBle.counter)
{
WMT_PLAT_DBG_FUNC("BGF INT has been enabled,counter(%d)\n",gbgfIrqBle.counter);;
}
else
{
enable_irq(MT_CONN2AP_BTIF_WAKEUP_IRQ_ID);
gbgfIrqBle.counter++;
}
WMT_PLAT_DBG_FUNC("WMT-PLAT:BGFInt (en) \n");
spin_unlock_irqrestore(&gbgfIrqBle.lock,gbgfIrqBle.flags);
}
else if (PIN_STA_EINT_DIS == state) {
spin_lock_irqsave(&gbgfIrqBle.lock,gbgfIrqBle.flags);
if(!gbgfIrqBle.counter)
{
WMT_PLAT_INFO_FUNC("BGF INT has been disabled,counter(%d)\n",gbgfIrqBle.counter);;
}
else
{
disable_irq_nosync(MT_CONN2AP_BTIF_WAKEUP_IRQ_ID);
gbgfIrqBle.counter--;
}
WMT_PLAT_DBG_FUNC("WMT-PLAT:BGFInt (dis) \n");
spin_unlock_irqrestore(&gbgfIrqBle.lock,gbgfIrqBle.flags);
}
else {
free_irq(MT_CONN2AP_BTIF_WAKEUP_IRQ_ID,NULL);
/* de-init: nothing to do in ALPS, such as un-registration... */
}
#else
WMT_PLAT_INFO_FUNC("WMT-PLAT:BGF EINT not defined\n", state);
#endif
iret = 0;
break;
default:
WMT_PLAT_WARN_FUNC("WMT-PLAT:unsupported EIRQ(PIN_ID:%d) in eirq_ctrl\n", id);
iret = -1;
break;
}
return iret;
}
INT32 mtk_wcn_consys_hw_reg_ctrl(UINT32 on, UINT32 co_clock_type)
{
INT32 iRet = -1;
UINT32 retry = 10;
UINT32 consysHwChipId = 0;
WMT_PLAT_WARN_FUNC("CONSYS-HW-REG-CTRL(0x%08x),start\n", on);
if (on) {
WMT_PLAT_DBG_FUNC("++\n");
/*step1.PMIC ctrl*/
#if CONSYS_PMIC_CTRL_ENABLE
/*need PMIC driver provide new API protocol */
/*1.AP power on VCN_1V8 LDO (with PMIC_WRAP API) VCN_1V8 */
pmic_set_register_value(PMIC_RG_VCN18_ON_CTRL, 0);
/* VOL_DEFAULT, VOL_1200, VOL_1300, VOL_1500, VOL_1800... */
#if defined(CONFIG_MTK_PMIC_LEGACY)
hwPowerOn(MT6328_POWER_LDO_VCN18, VOL_1800, "wcn_drv");
#else
if (reg_VCN18) {
regulator_set_voltage(reg_VCN18, VOL_1800, VOL_1800);
if (regulator_enable(reg_VCN18))
WMT_PLAT_ERR_FUNC("enable VCN18 fail\n");
else
WMT_PLAT_DBG_FUNC("enable VCN18 ok\n");
}
#endif
udelay(150);
if (co_clock_type) {
/*step0,clk buf ctrl */
WMT_PLAT_INFO_FUNC("co clock type(%d),turn on clk buf\n", co_clock_type);
#if CONSYS_CLOCK_BUF_CTRL
clk_buf_ctrl(CLK_BUF_CONN, 1);
#endif
/*if co-clock mode: */
/*2.set VCN28 to SW control mode (with PMIC_WRAP API) */
/*turn on VCN28 LDO only when FMSYS is activated" */
pmic_set_register_value(PMIC_RG_VCN28_ON_CTRL, 0);
} else {
/*if NOT co-clock: */
/*2.1.switch VCN28 to HW control mode (with PMIC_WRAP API) */
pmic_set_register_value(PMIC_RG_VCN28_ON_CTRL, 1);
/*2.2.turn on VCN28 LDO (with PMIC_WRAP API)" */
/*fix vcn28 not balance warning */
#if defined(CONFIG_MTK_PMIC_LEGACY)
hwPowerOn(MT6328_POWER_LDO_VCN28, VOL_2800, "wcn_drv");
#else
if (reg_VCN28) {
regulator_set_voltage(reg_VCN28, VOL_2800, VOL_2800);
if (regulator_enable(reg_VCN28))
WMT_PLAT_ERR_FUNC("enable VCN_2V8 fail!\n");
else
WMT_PLAT_DBG_FUNC("enable VCN_2V8 ok\n");
}
#endif
}
#endif
/*step2.MTCMOS ctrl*/
#ifdef CONFIG_OF /*use DT */
/*3.assert CONNSYS CPU SW reset 0x10007018 "[12]=1'b1 [31:24]=8'h88 (key)" */
CONSYS_REG_WRITE((conn_reg.ap_rgu_base + CONSYS_CPU_SW_RST_OFFSET),
CONSYS_REG_READ(conn_reg.ap_rgu_base + CONSYS_CPU_SW_RST_OFFSET) |
CONSYS_CPU_SW_RST_BIT | CONSYS_CPU_SW_RST_CTRL_KEY);
/*turn on SPM clock gating enable PWRON_CONFG_EN 0x10006000 32'h0b160001 */
CONSYS_REG_WRITE((conn_reg.spm_base + CONSYS_PWRON_CONFG_EN_OFFSET), CONSYS_PWRON_CONFG_EN_VALUE);
#if CONSYS_PWR_ON_OFF_API_AVAILABLE
#if defined(CONFIG_MTK_CLKMGR)
iRet = conn_power_on(); /* consult clkmgr owner. */
if (iRet)
WMT_PLAT_ERR_FUNC("conn_power_on fail(%d)\n", iRet);
WMT_PLAT_DBG_FUNC("conn_power_on ok\n");
#else
iRet = clk_prepare_enable(clk_scp_conn_main);
if (iRet)
WMT_PLAT_ERR_FUNC("clk_prepare_enable(clk_scp_conn_main) fail(%d)\n", iRet);
WMT_PLAT_DBG_FUNC("clk_prepare_enable(clk_scp_conn_main) ok\n");
#endif /* defined(CONFIG_MTK_CLKMGR) */
#else
/*2.write conn_top1_pwr_on=1, power on conn_top1 0x10006280 [2] 1'b1 */
CONSYS_REG_WRITE(conn_reg.spm_base + CONSYS_TOP1_PWR_CTRL_OFFSET,
CONSYS_REG_READ(conn_reg.spm_base + CONSYS_TOP1_PWR_CTRL_OFFSET) |
CONSYS_SPM_PWR_ON_BIT);
/*3.read conn_top1_pwr_on_ack =1, power on ack ready 0x1000660C [1] */
while (0 == (CONSYS_PWR_ON_ACK_BIT & CONSYS_REG_READ(conn_reg.spm_base + CONSYS_PWR_CONN_ACK_OFFSET)))
NULL;
/*5.write conn_top1_pwr_on_s=1, power on conn_top1 0x10006280 [3] 1'b1 */
CONSYS_REG_WRITE(conn_reg.spm_base + CONSYS_TOP1_PWR_CTRL_OFFSET,
CONSYS_REG_READ(conn_reg.spm_base + CONSYS_TOP1_PWR_CTRL_OFFSET) |
CONSYS_SPM_PWR_ON_S_BIT);
/*6.write conn_clk_dis=0, enable connsys clock 0x10006280 [4] 1'b0 */
CONSYS_REG_WRITE(conn_reg.spm_base + CONSYS_TOP1_PWR_CTRL_OFFSET,
CONSYS_REG_READ(conn_reg.spm_base + CONSYS_TOP1_PWR_CTRL_OFFSET) &
~CONSYS_CLK_CTRL_BIT);
/*7.wait 1us */
udelay(1);
/*8.read conn_top1_pwr_on_ack_s =1, power on ack ready 0x10006610 [1] */
while (0 == (CONSYS_PWR_CONN_ACK_S_BIT &
CONSYS_REG_READ(conn_reg.spm_base + CONSYS_PWR_CONN_ACK_S_OFFSET)))
NULL;
/*9.release connsys ISO, conn_top1_iso_en=0 0x10006280 [1] 1'b0 */
CONSYS_REG_WRITE(conn_reg.spm_base + CONSYS_TOP1_PWR_CTRL_OFFSET,
CONSYS_REG_READ(conn_reg.spm_base + CONSYS_TOP1_PWR_CTRL_OFFSET) &
~CONSYS_SPM_PWR_ISO_S_BIT);
/*10.release SW reset of connsys, conn_ap_sw_rst_b=1 0x10006280[0] 1'b1 */
CONSYS_REG_WRITE(conn_reg.spm_base + CONSYS_TOP1_PWR_CTRL_OFFSET,
CONSYS_REG_READ(conn_reg.spm_base + CONSYS_TOP1_PWR_CTRL_OFFSET) |
CONSYS_SPM_PWR_RST_BIT);
/*disable AXI BUS protect */
CONSYS_REG_WRITE(conn_reg.topckgen_base + CONSYS_TOPAXI_PROT_EN_OFFSET,
CONSYS_REG_READ(conn_reg.topckgen_base + CONSYS_TOPAXI_PROT_EN_OFFSET) &
~CONSYS_PROT_MASK);
while (CONSYS_REG_READ(conn_reg.topckgen_base + CONSYS_TOPAXI_PROT_STA1_OFFSET) & CONSYS_PROT_MASK)
NULL;
#endif
/*11.26M is ready now, delay 10us for mem_pd de-assert */
udelay(10);
/*enable AP bus clock : connmcu_bus_pd API: enable_clock() ++?? */
#if CONSYS_AHB_CLK_MAGEMENT
#if defined(CONFIG_MTK_CLKMGR)
enable_clock(MT_CG_INFRA_CONNMCU_BUS, "WCN_MOD");
WMT_PLAT_DBG_FUNC("enable MT_CG_INFRA_CONNMCU_BUS CLK\n");
#else
iRet = clk_prepare_enable(clk_infra_conn_main);
if (iRet)
WMT_PLAT_ERR_FUNC("clk_prepare_enable(clk_infra_conn_main) fail(%d)\n", iRet);
WMT_PLAT_DBG_FUNC("[CCF]enable clk_infra_conn_main\n");
#endif /* defined(CONFIG_MTK_CLKMGR) */
#endif
/*12.poll CONNSYS CHIP ID until chipid is returned 0x18070008 */
while (retry-- > 0) {
consysHwChipId = CONSYS_REG_READ(conn_reg.mcu_base + CONSYS_CHIP_ID_OFFSET);
if ((consysHwChipId == 0x0321) || (consysHwChipId == 0x0335) || (consysHwChipId == 0x0337)) {
WMT_PLAT_INFO_FUNC("retry(%d)consys chipId(0x%08x)\n", retry, consysHwChipId);
break;
}
WMT_PLAT_ERR_FUNC("Read CONSYS chipId(0x%08x)", consysHwChipId);
msleep(20);
}
if ((0 == retry) || (0 == consysHwChipId)) {
WMT_PLAT_ERR_FUNC("Maybe has a consys power on issue,(0x%08x)\n", consysHwChipId);
WMT_PLAT_ERR_FUNC("reg dump:CONSYS_CPU_SW_RST_REG(0x%x)\n",
CONSYS_REG_READ(conn_reg.ap_rgu_base + CONSYS_CPU_SW_RST_OFFSET));
WMT_PLAT_ERR_FUNC("reg dump:CONSYS_PWR_CONN_ACK_REG(0x%x)\n",
CONSYS_REG_READ(conn_reg.spm_base + CONSYS_PWR_CONN_ACK_OFFSET));
WMT_PLAT_ERR_FUNC("reg dump:CONSYS_PWR_CONN_ACK_S_REG(0x%x)\n",
CONSYS_REG_READ(conn_reg.spm_base + CONSYS_PWR_CONN_ACK_S_OFFSET));
WMT_PLAT_ERR_FUNC("reg dump:CONSYS_TOP1_PWR_CTRL_REG(0x%x)\n",
CONSYS_REG_READ(conn_reg.spm_base + CONSYS_TOP1_PWR_CTRL_OFFSET));
}
/*13.{default no need}update ROMDEL/PATCH RAM DELSEL if needed 0x18070114 */
/*
*14.write 1 to conn_mcu_confg ACR[1] if real speed MBIST
*(default write "1") ACR 0x18070110[18] 1'b1
*if this bit is 0, HW will do memory auto test under low CPU frequence (26M Hz)
*if this bit is 0, HW will do memory auto test under high CPU frequence(138M Hz)
*inclulding low CPU frequence
*/
CONSYS_REG_WRITE(conn_reg.mcu_base + CONSYS_MCU_CFG_ACR_OFFSET,
CONSYS_REG_READ(conn_reg.mcu_base + CONSYS_MCU_CFG_ACR_OFFSET) |
CONSYS_MCU_CFG_ACR_MBIST_BIT);
#if 0
/*15.default no need,update ANA_WBG(AFE) CR if needed, CONSYS_AFE_REG */
CONSYS_REG_WRITE(CONSYS_AFE_REG_DIG_RCK_01, CONSYS_AFE_REG_DIG_RCK_01_VALUE);
CONSYS_REG_WRITE(CONSYS_AFE_REG_WBG_PLL_02, CONSYS_AFE_REG_WBG_PLL_02_VALUE);
CONSYS_REG_WRITE(CONSYS_AFE_REG_WBG_WB_TX_01, CONSYS_AFE_REG_WBG_WB_TX_01_VALUE);
#endif
/*16.deassert CONNSYS CPU SW reset 0x10007018 "[12]=1'b0 [31:24] =8'h88 (key)" */
CONSYS_REG_WRITE(conn_reg.ap_rgu_base + CONSYS_CPU_SW_RST_OFFSET,
(CONSYS_REG_READ(conn_reg.ap_rgu_base + CONSYS_CPU_SW_RST_OFFSET) &
~CONSYS_CPU_SW_RST_BIT) | CONSYS_CPU_SW_RST_CTRL_KEY);
#else /*use HADRCODE, maybe no use.. */
/*3.assert CONNSYS CPU SW reset 0x10007018 "[12]=1'b1 [31:24]=8'h88 (key)" */
CONSYS_REG_WRITE(CONSYS_CPU_SW_RST_REG,
(CONSYS_REG_READ(CONSYS_CPU_SW_RST_REG) | CONSYS_CPU_SW_RST_BIT |
CONSYS_CPU_SW_RST_CTRL_KEY));
/*turn on SPM clock gating enable PWRON_CONFG_EN 0x10006000 32'h0b160001 */
CONSYS_REG_WRITE(CONSYS_PWRON_CONFG_EN_REG, CONSYS_PWRON_CONFG_EN_VALUE);
#if CONSYS_PWR_ON_OFF_API_AVAILABLE
#if defined(CONFIG_MTK_CLKMGR)
iRet = conn_power_on(); /* consult clkmgr owner */
if (iRet)
WMT_PLAT_ERR_FUNC("conn_power_on fail(%d)\n", iRet);
WMT_PLAT_DBG_FUNC("conn_power_on ok\n");
#else
iRet = clk_prepare_enable(clk_scp_conn_main);
if (iRet)
WMT_PLAT_ERR_FUNC("clk_prepare_enable(clk_scp_conn_main) fail(%d)\n", iRet);
WMT_PLAT_DBG_FUNC("clk_prepare_enable(clk_scp_conn_main) ok\n");
#endif /* defined(CONFIG_MTK_CLKMGR) */
#else
/*2.write conn_top1_pwr_on=1, power on conn_top1 0x10006280 [2] 1'b1 */
CONSYS_REG_WRITE(CONSYS_TOP1_PWR_CTRL_REG,
CONSYS_REG_READ(CONSYS_TOP1_PWR_CTRL_REG) | CONSYS_SPM_PWR_ON_BIT);
/*3.read conn_top1_pwr_on_ack =1, power on ack ready 0x1000660C [1] */
while (0 == (CONSYS_PWR_ON_ACK_BIT & CONSYS_REG_READ(CONSYS_PWR_CONN_ACK_REG)))
NULL;
/*5.write conn_top1_pwr_on_s=1, power on conn_top1 0x10006280 [3] 1'b1 */
CONSYS_REG_WRITE(CONSYS_TOP1_PWR_CTRL_REG,
CONSYS_REG_READ(CONSYS_TOP1_PWR_CTRL_REG) | CONSYS_SPM_PWR_ON_S_BIT);
/*6.write conn_clk_dis=0, enable connsys clock 0x10006280 [4] 1'b0 */
CONSYS_REG_WRITE(CONSYS_TOP1_PWR_CTRL_REG,
CONSYS_REG_READ(CONSYS_TOP1_PWR_CTRL_REG) & ~CONSYS_CLK_CTRL_BIT);
/*7.wait 1us */
udelay(1);
/*8.read conn_top1_pwr_on_ack_s =1, power on ack ready 0x10006610 [1] */
while (0 == (CONSYS_PWR_CONN_ACK_S_BIT & CONSYS_REG_READ(CONSYS_PWR_CONN_ACK_S_REG)))
NULL;
/*9.release connsys ISO, conn_top1_iso_en=0 0x10006280 [1] 1'b0 */
CONSYS_REG_WRITE(CONSYS_TOP1_PWR_CTRL_REG,
CONSYS_REG_READ(CONSYS_TOP1_PWR_CTRL_REG) & ~CONSYS_SPM_PWR_ISO_S_BIT);
/*10.release SW reset of connsys, conn_ap_sw_rst_b=1 0x10006280[0] 1'b1 */
CONSYS_REG_WRITE(CONSYS_TOP1_PWR_CTRL_REG,
CONSYS_REG_READ(CONSYS_TOP1_PWR_CTRL_REG) | CONSYS_SPM_PWR_RST_BIT);
/*disable AXI BUS protect */
CONSYS_REG_WRITE(CONSYS_TOPAXI_PROT_EN, CONSYS_REG_READ(CONSYS_TOPAXI_PROT_EN) & ~CONSYS_PROT_MASK);
while (CONSYS_REG_READ(CONSYS_TOPAXI_PROT_STA1) & CONSYS_PROT_MASK)
NULL;
#endif
/*11.26M is ready now, delay 10us for mem_pd de-assert */
udelay(10);
/*enable AP bus clock : connmcu_bus_pd API: enable_clock() ++?? */
#if CONSYS_AHB_CLK_MAGEMENT
#if defined(CONFIG_MTK_CLKMGR)
enable_clock(MT_CG_INFRA_CONNMCU_BUS, "WCN_MOD");
WMT_PLAT_DBG_FUNC("enable MT_CG_INFRA_CONNMCU_BUS CLK\n");
#else
iRet = clk_prepare_enable(clk_infra_conn_main);
if (iRet)
WMT_PLAT_ERR_FUNC("clk_prepare_enable(clk_infra_conn_main) fail(%d)\n", iRet);
WMT_PLAT_DBG_FUNC("[CCF]enable clk_infra_conn_main\n");
#endif /* defined(CONFIG_MTK_CLKMGR) */
#endif
/*12.poll CONNSYS CHIP ID until 6752 is returned 0x18070008 32'h6752 */
while (retry-- > 0) {
WMT_PLAT_DBG_FUNC("CONSYS_CHIP_ID_REG(0x%08x)", CONSYS_REG_READ(CONSYS_CHIP_ID_REG));
consysHwChipId = CONSYS_REG_READ(CONSYS_CHIP_ID_REG);
if ((consysHwChipId == 0x0321) || (consysHwChipId == 0x0335) || (consysHwChipId == 0x0337)) {
WMT_PLAT_INFO_FUNC("retry(%d)consys chipId(0x%08x)\n", retry, consysHwChipId);
break;
}
msleep(20);
}
if ((0 == retry) || (0 == consysHwChipId)) {
WMT_PLAT_ERR_FUNC("Maybe has a consys power on issue,(0x%08x)\n", consysHwChipId);
WMT_PLAT_INFO_FUNC("reg dump:CONSYS_CPU_SW_RST_REG(0x%x)\n",
CONSYS_REG_READ(CONSYS_CPU_SW_RST_REG));
WMT_PLAT_INFO_FUNC("reg dump:CONSYS_PWR_CONN_ACK_REG(0x%x)\n",
CONSYS_REG_READ(CONSYS_PWR_CONN_ACK_REG));
WMT_PLAT_INFO_FUNC("reg dump:CONSYS_PWR_CONN_ACK_S_REG(0x%x)\n",
CONSYS_REG_READ(CONSYS_PWR_CONN_ACK_S_REG));
WMT_PLAT_INFO_FUNC("reg dump:CONSYS_TOP1_PWR_CTRL_REG(0x%x)\n",
CONSYS_REG_READ(CONSYS_TOP1_PWR_CTRL_REG));
}
/*13.{default no need}update ROMDEL/PATCH RAM DELSEL if needed 0x18070114 */
/*
*14.write 1 to conn_mcu_confg ACR[1] if real speed MBIST
*(default write "1") ACR 0x18070110[18] 1'b1
*if this bit is 0, HW will do memory auto test under low CPU frequence (26M Hz)
*if this bit is 0, HW will do memory auto test under high CPU frequence(138M Hz)
*inclulding low CPU frequence
*/
CONSYS_REG_WRITE(CONSYS_MCU_CFG_ACR_REG,
CONSYS_REG_READ(CONSYS_MCU_CFG_ACR_REG) | CONSYS_MCU_CFG_ACR_MBIST_BIT);
/*update ANA_WBG(AFE) CR. AFE setting file: AP Offset = 0x180B2000 */
#if 0
/*15.default no need,update ANA_WBG(AFE) CR if needed, CONSYS_AFE_REG */
CONSYS_REG_WRITE(CONSYS_AFE_REG_DIG_RCK_01, CONSYS_AFE_REG_DIG_RCK_01_VALUE);
CONSYS_REG_WRITE(CONSYS_AFE_REG_WBG_PLL_02, CONSYS_AFE_REG_WBG_PLL_02_VALUE);
CONSYS_REG_WRITE(CONSYS_AFE_REG_WBG_WB_TX_01, CONSYS_AFE_REG_WBG_WB_TX_01_VALUE);
#endif
/*16.deassert CONNSYS CPU SW reset 0x10007018 "[12]=1'b0 [31:24] =8'h88(key)" */
CONSYS_REG_WRITE(CONSYS_CPU_SW_RST_REG,
(CONSYS_REG_READ(CONSYS_CPU_SW_RST_REG) & ~CONSYS_CPU_SW_RST_BIT) |
CONSYS_CPU_SW_RST_CTRL_KEY);
#endif
msleep(20); /* msleep < 20ms can sleep for up to 20ms */
} else {
#ifdef CONFIG_OF
#if CONSYS_AHB_CLK_MAGEMENT
#if defined(CONFIG_MTK_CLKMGR)
disable_clock(MT_CG_INFRA_CONNMCU_BUS, "WMT_MOD");
#else
clk_disable_unprepare(clk_infra_conn_main);
WMT_PLAT_DBG_FUNC("[CCF] clk_disable_unprepare(clk_infra_conn_main) calling\n");
#endif /* defined(CONFIG_MTK_CLKMGR) */
#endif
#if CONSYS_PWR_ON_OFF_API_AVAILABLE
#if defined(CONFIG_MTK_CLKMGR)
/*power off connsys by API (MT6582, MT6572 are different) API: conn_power_off() */
iRet = conn_power_off(); /* consult clkmgr owner */
if (iRet)
WMT_PLAT_ERR_FUNC("conn_power_off fail(%d)\n", iRet);
WMT_PLAT_DBG_FUNC("conn_power_off ok\n");
#else
clk_disable_unprepare(clk_scp_conn_main);
WMT_PLAT_DBG_FUNC("clk_disable_unprepare(clk_scp_conn_main) calling\n");
#endif /* defined(CONFIG_MTK_CLKMGR) */
#else
{
INT32 count = 0;
CONSYS_REG_WRITE(conn_reg.topckgen_base + CONSYS_TOPAXI_PROT_EN_OFFSET,
CONSYS_REG_READ(conn_reg.topckgen_base + CONSYS_TOPAXI_PROT_EN_OFFSET) |
CONSYS_PROT_MASK);
while ((CONSYS_REG_READ(conn_reg.topckgen_base + CONSYS_TOPAXI_PROT_STA1_OFFSET) &
CONSYS_PROT_MASK) != CONSYS_PROT_MASK) {
count++;
if (count > 1000)
break;
}
}
/*release connsys ISO, conn_top1_iso_en=1 0x10006280 [1] 1'b1 */
CONSYS_REG_WRITE(conn_reg.spm_base + CONSYS_TOP1_PWR_CTRL_OFFSET,
CONSYS_REG_READ(conn_reg.spm_base + CONSYS_TOP1_PWR_CTRL_OFFSET) |
CONSYS_SPM_PWR_ISO_S_BIT);
/*assert SW reset of connsys, conn_ap_sw_rst_b=0 0x10006280[0] 1'b0 */
CONSYS_REG_WRITE(conn_reg.spm_base + CONSYS_TOP1_PWR_CTRL_OFFSET,
CONSYS_REG_READ(conn_reg.spm_base + CONSYS_TOP1_PWR_CTRL_OFFSET) &
~CONSYS_SPM_PWR_RST_BIT);
/*write conn_clk_dis=1, disable connsys clock 0x10006280 [4] 1'b1 */
CONSYS_REG_WRITE(conn_reg.spm_base + CONSYS_TOP1_PWR_CTRL_OFFSET,
CONSYS_REG_READ(conn_reg.spm_base + CONSYS_TOP1_PWR_CTRL_OFFSET) |
CONSYS_CLK_CTRL_BIT);
/*wait 1us */
udelay(1);
/*write conn_top1_pwr_on=0, power off conn_top1 0x10006280 [3:2] 2'b00 */
CONSYS_REG_WRITE(conn_reg.spm_base + CONSYS_TOP1_PWR_CTRL_OFFSET,
CONSYS_REG_READ(conn_reg.spm_base + CONSYS_TOP1_PWR_CTRL_OFFSET) &
~(CONSYS_SPM_PWR_ON_BIT | CONSYS_SPM_PWR_ON_S_BIT));
#endif
#else
#if CONSYS_PWR_ON_OFF_API_AVAILABLE
#if CONSYS_AHB_CLK_MAGEMENT
#if defined(CONFIG_MTK_CLKMGR)
disable_clock(MT_CG_INFRA_CONNMCU_BUS, "WMT_MOD");
#else
clk_disable_unprepare(clk_infra_conn_main);
#endif /* defined(CONFIG_MTK_CLKMGR) */
#endif
#if defined(CONFIG_MTK_CLKMGR)
/*power off connsys by API: conn_power_off() */
iRet = conn_power_off(); /* consult clkmgr owner */
if (iRet)
WMT_PLAT_ERR_FUNC("conn_power_off fail(%d)\n", iRet);
WMT_PLAT_DBG_FUNC("conn_power_off ok\n");
#else
clk_disable_unprepare(clk_scp_conn_main);
WMT_PLAT_DBG_FUNC("clk_disable_unprepare(clk_scp_conn_main) calling\n");
#endif /* defined(CONFIG_MTK_CLKMGR) */
#else
{
INT32 count = 0;
CONSYS_REG_WRITE(CONSYS_TOPAXI_PROT_EN,
CONSYS_REG_READ(CONSYS_TOPAXI_PROT_EN) | CONSYS_PROT_MASK);
while ((CONSYS_REG_READ(CONSYS_TOPAXI_PROT_STA1) & CONSYS_PROT_MASK) != CONSYS_PROT_MASK) {
count++;
if (count > 1000)
break;
}
}
/*release connsys ISO, conn_top1_iso_en=1 0x10006280 [1] 1'b1 */
CONSYS_REG_WRITE(CONSYS_TOP1_PWR_CTRL_REG,
CONSYS_REG_READ(CONSYS_TOP1_PWR_CTRL_REG) | CONSYS_SPM_PWR_ISO_S_BIT);
/*assert SW reset of connsys, conn_ap_sw_rst_b=0 0x10006280[0] 1'b0 */
CONSYS_REG_WRITE(CONSYS_TOP1_PWR_CTRL_REG,
CONSYS_REG_READ(CONSYS_TOP1_PWR_CTRL_REG) & ~CONSYS_SPM_PWR_RST_BIT);
/*write conn_clk_dis=1, disable connsys clock 0x10006280 [4] 1'b1 */
CONSYS_REG_WRITE(CONSYS_TOP1_PWR_CTRL_REG,
CONSYS_REG_READ(CONSYS_TOP1_PWR_CTRL_REG) | CONSYS_CLK_CTRL_BIT);
/*wait 1us */
udelay(1);
/*write conn_top1_pwr_on=0, power off conn_top1 0x10006280 [3:2] 2'b00 */
CONSYS_REG_WRITE(CONSYS_TOP1_PWR_CTRL_REG, CONSYS_REG_READ(CONSYS_TOP1_PWR_CTRL_REG) &
~(CONSYS_SPM_PWR_ON_BIT | CONSYS_SPM_PWR_ON_S_BIT));
#endif
#endif
#if CONSYS_PMIC_CTRL_ENABLE
if (co_clock_type) {
/*VCN28 has been turned off by GPS OR FM */
#if CONSYS_CLOCK_BUF_CTRL
clk_buf_ctrl(CLK_BUF_CONN, 0);
#endif
} else {
pmic_set_register_value(PMIC_RG_VCN28_ON_CTRL, 0);
/*turn off VCN28 LDO (with PMIC_WRAP API)" */
#if defined(CONFIG_MTK_PMIC_LEGACY)
hwPowerDown(MT6328_POWER_LDO_VCN28, "wcn_drv");
#else
if (reg_VCN28) {
if (regulator_disable(reg_VCN28))
WMT_PLAT_ERR_FUNC("disable VCN_2V8 fail!\n");
else
WMT_PLAT_DBG_FUNC("disable VCN_2V8 ok\n");
}
#endif
}
/*AP power off MT6625L VCN_1V8 LDO */
pmic_set_register_value(PMIC_RG_VCN18_ON_CTRL, 0);
#if defined(CONFIG_MTK_PMIC_LEGACY)
hwPowerDown(MT6328_POWER_LDO_VCN18, "wcn_drv");
#else
if (reg_VCN18) {
if (regulator_disable(reg_VCN18))
WMT_PLAT_ERR_FUNC("disable VCN_1V8 fail!\n");
else
WMT_PLAT_DBG_FUNC("disable VCN_1V8 ok\n");
}
#endif
#endif
}
WMT_PLAT_WARN_FUNC("CONSYS-HW-REG-CTRL(0x%08x),finish\n", on);
return 0;
}
INT32 wmt_plat_eirq_ctrl(ENUM_PIN_ID id, ENUM_PIN_STATE state)
{
#ifdef CONFIG_OF
struct device_node *node;
unsigned int irq_info[3] = { 0, 0, 0 };
#endif
INT32 iret = -EINVAL;
static INT32 bgf_irq_num = -1;
static UINT32 bgf_irq_flag;
/* TODO: [ChangeFeature][GeorgeKuo]: use another function to handle this, as done in gpio_ctrls */
if ((PIN_STA_INIT != state)
&& (PIN_STA_DEINIT != state)
&& (PIN_STA_EINT_EN != state)
&& (PIN_STA_EINT_DIS != state)) {
WMT_PLAT_WARN_FUNC("WMT-PLAT:invalid PIN_STATE(%d) in eirq_ctrl for PIN(%d)\n", state, id);
return -1;
}
switch (id) {
case PIN_BGF_EINT:
if (PIN_STA_INIT == state) {
#ifdef CONFIG_OF
node = of_find_compatible_node(NULL, NULL, "mediatek,mt6735-consys");
if (node) {
bgf_irq_num = irq_of_parse_and_map(node, 0);
/* get the interrupt line behaviour */
if (of_property_read_u32_array(node, "interrupts", irq_info, ARRAY_SIZE(irq_info))) {
WMT_PLAT_ERR_FUNC("get irq flags from DTS fail!!\n");
return iret;
}
bgf_irq_flag = irq_info[2];
WMT_PLAT_INFO_FUNC("get irq id(%d) and irq trigger flag(%d) from DT\n", bgf_irq_num,
bgf_irq_flag);
} else {
WMT_PLAT_ERR_FUNC("[%s] can't find CONSYS compatible node\n", __func__);
return iret;
}
#else
bgf_irq_num = MT_CONN2AP_BTIF_WAKEUP_IRQ_ID;
bgf_irq_flag = IRQF_TRIGGER_LOW;
#endif
iret = request_irq(bgf_irq_num, wmt_plat_bgf_irq_isr, bgf_irq_flag, "BTIF_WAKEUP_IRQ", NULL);
if (iret) {
WMT_PLAT_ERR_FUNC("request_irq fail,irq_no(%d),iret(%d)\n", bgf_irq_num, iret);
return iret;
}
gbgfIrqBle.counter = 1;
} else if (PIN_STA_EINT_EN == state) {
spin_lock_irqsave(&gbgfIrqBle.lock, gbgfIrqBle.flags);
if (gbgfIrqBle.counter) {
WMT_PLAT_DBG_FUNC("BGF INT has been enabled,counter(%d)\n", gbgfIrqBle.counter);
} else {
enable_irq(bgf_irq_num);
gbgfIrqBle.counter++;
}
WMT_PLAT_DBG_FUNC("WMT-PLAT:BGFInt (en)\n");
spin_unlock_irqrestore(&gbgfIrqBle.lock, gbgfIrqBle.flags);
} else if (PIN_STA_EINT_DIS == state) {
spin_lock_irqsave(&gbgfIrqBle.lock, gbgfIrqBle.flags);
if (!gbgfIrqBle.counter) {
WMT_PLAT_INFO_FUNC("BGF INT has been disabled,counter(%d)\n", gbgfIrqBle.counter);
} else {
disable_irq_nosync(bgf_irq_num);
gbgfIrqBle.counter--;
}
WMT_PLAT_DBG_FUNC("WMT-PLAT:BGFInt (dis)\n");
spin_unlock_irqrestore(&gbgfIrqBle.lock, gbgfIrqBle.flags);
} else {
free_irq(bgf_irq_num, NULL);
/* de-init: nothing to do in ALPS, such as un-registration... */
}
iret = 0;
break;
default:
WMT_PLAT_WARN_FUNC("WMT-PLAT:unsupported EIRQ(PIN_ID:%d) in eirq_ctrl\n", id);
iret = -1;
break;
}
return iret;
}
static INT32 wmt_plat_gps_lna_ctrl(ENUM_PIN_STATE state)
{
#if !defined(CONFIG_MTK_GPIO_LEGACY)
static struct pinctrl_state *gps_lna_init;
static struct pinctrl_state *gps_lna_oh;
static struct pinctrl_state *gps_lna_ol;
static struct pinctrl *consys_pinctrl;
WMT_PLAT_DBG_FUNC("ENTER++\n");
consys_pinctrl = mtk_wcn_consys_get_pinctrl();
if (NULL == consys_pinctrl) {
WMT_PLAT_ERR_FUNC("get consys pinctrl fail\n");
return -1;
}
gps_lna_init = pinctrl_lookup_state(consys_pinctrl, "gps_lna_state_init");
if (NULL == gps_lna_init) {
WMT_PLAT_ERR_FUNC("Cannot find gps lna pin init state!\n");
return -2;
}
gps_lna_oh = pinctrl_lookup_state(consys_pinctrl, "gps_lna_state_oh");
if (NULL == gps_lna_oh) {
WMT_PLAT_ERR_FUNC("Cannot find gps lna pin oh state!\n");
return -3;
}
gps_lna_ol = pinctrl_lookup_state(consys_pinctrl, "gps_lna_state_ol");
if (NULL == gps_lna_ol) {
WMT_PLAT_ERR_FUNC("Cannot find gps lna pin ol state!\n");
return -4;
}
switch (state) {
case PIN_STA_INIT:
case PIN_STA_DEINIT:
pinctrl_select_state(consys_pinctrl, gps_lna_init);
WMT_PLAT_INFO_FUNC("set gps lna to init\n");
break;
case PIN_STA_OUT_H:
pinctrl_select_state(consys_pinctrl, gps_lna_oh);
WMT_PLAT_INFO_FUNC("set gps lna to oh\n");
break;
case PIN_STA_OUT_L:
pinctrl_select_state(consys_pinctrl, gps_lna_ol);
WMT_PLAT_INFO_FUNC("set gps lna to ol\n");
break;
default:
WMT_PLAT_WARN_FUNC("%d mode not defined for gps lna pin !!!\n", state);
break;
}
return 0;
#else
#ifdef GPIO_GPS_LNA_PIN
switch (state) {
case PIN_STA_INIT:
case PIN_STA_DEINIT:
mt_set_gpio_pull_enable(GPIO_GPS_LNA_PIN, GPIO_PULL_DISABLE);
mt_set_gpio_dir(GPIO_GPS_LNA_PIN, GPIO_DIR_OUT);
mt_set_gpio_mode(GPIO_GPS_LNA_PIN, GPIO_GPS_LNA_PIN_M_GPIO);
mt_set_gpio_out(GPIO_GPS_LNA_PIN, GPIO_OUT_ZERO);
break;
case PIN_STA_OUT_H:
mt_set_gpio_out(GPIO_GPS_LNA_PIN, GPIO_OUT_ONE);
break;
case PIN_STA_OUT_L:
mt_set_gpio_out(GPIO_GPS_LNA_PIN, GPIO_OUT_ZERO);
break;
default:
WMT_PLAT_WARN_FUNC("%d mode not defined for gps lna pin !!!\n", state);
break;
}
return 0;
#else
WMT_PLAT_WARN_FUNC("host gps lna pin not defined!!!\n");
return 0;
#endif
#endif /* !defined(CONFIG_MTK_GPIO_LEGACY) */
}