int spi_transfer(unsigned char * send_buffer, unsigned char * receive_buffer, unsigned int size)
{
int ret ;
struct spi_ioc_transfer tr = {
.tx_buf = (unsigned long)send_buffer,
.rx_buf = (unsigned long)receive_buffer,
.len = size,
.delay_usecs = delay,
.speed_hz = speed,
.bits_per_word = bits,
};
ret = ioctl(fd, SPI_IOC_MESSAGE(1), &tr);
if (ret < 1){
printf("can't send spi message \n");
return -1 ;
}
return 0;
}
int mark1_write(unsigned int add, unsigned char * data, unsigned int size, unsigned char inc){
com_buffer[0] = WR0(add, inc) ;
com_buffer[1] = WR1(add, inc) ;
memcpy(&com_buffer[2], data, size);
return spi_transfer(com_buffer, com_buffer , (size + 2));
}
static void
sdhci_reset(struct sdhci_slot *slot, uint8_t mask)
{
int timeout;
uint8_t res;
if (slot->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) {
if (!(RD4(slot, SDHCI_PRESENT_STATE) &
SDHCI_CARD_PRESENT))
return;
}
/* Some controllers need this kick or reset won't work. */
if ((mask & SDHCI_RESET_ALL) == 0 &&
(slot->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET)) {
uint32_t clock;
/* This is to force an update */
clock = slot->clock;
slot->clock = 0;
sdhci_set_clock(slot, clock);
}
WR1(slot, SDHCI_SOFTWARE_RESET, mask);
if (mask & SDHCI_RESET_ALL) {
slot->clock = 0;
slot->power = 0;
}
/* Wait max 100 ms */
timeout = 100;
/* Controller clears the bits when it's done */
while ((res = RD1(slot, SDHCI_SOFTWARE_RESET)) & mask) {
if (timeout == 0) {
slot_printf(slot,
"Reset 0x%x never completed - 0x%x.\n",
(int)mask, (int)res);
sdhci_dumpregs(slot);
return;
}
timeout--;
DELAY(1000);
}
}
static void
sdhci_reset(struct sdhci_slot *slot, uint8_t mask)
{
int timeout;
if (slot->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) {
if (!(RD4(slot, SDHCI_PRESENT_STATE) &
SDHCI_CARD_PRESENT))
return;
}
/* Some controllers need this kick or reset won't work. */
if ((mask & SDHCI_RESET_ALL) == 0 &&
(slot->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET)) {
uint32_t clock;
/* This is to force an update */
clock = slot->clock;
slot->clock = 0;
sdhci_set_clock(slot, clock);
}
if (mask & SDHCI_RESET_ALL) {
slot->clock = 0;
slot->power = 0;
}
WR1(slot, SDHCI_SOFTWARE_RESET, mask);
if (slot->quirks & SDHCI_QUIRK_WAITFOR_RESET_ASSERTED) {
/*
* Resets on TI OMAPs and AM335x are incompatible with SDHCI
* specification. The reset bit has internal propagation delay,
* so a fast read after write returns 0 even if reset process is
* in progress. The workaround is to poll for 1 before polling
* for 0. In the worst case, if we miss seeing it asserted the
* time we spent waiting is enough to ensure the reset finishes.
*/
timeout = 10000;
while ((RD1(slot, SDHCI_SOFTWARE_RESET) & mask) != mask) {
if (timeout <= 0)
break;
timeout--;
DELAY(1);
}
}
/* Wait max 100 ms */
timeout = 10000;
/* Controller clears the bits when it's done */
while (RD1(slot, SDHCI_SOFTWARE_RESET) & mask) {
if (timeout <= 0) {
slot_printf(slot, "Reset 0x%x never completed.\n",
mask);
sdhci_dumpregs(slot);
return;
}
timeout--;
DELAY(10);
}
}
