u8 DRXD_InitSC[] = {
WR16(SC_COMM_EXEC__A, 0),
WR16(SC_COMM_STATE__A, 0),
#ifdef COMPILE_FOR_QT
WR16(SC_RA_RAM_BE_OPT_DELAY__A, 0x100),
#endif
/* SC is not started, this is done in SetChannels() */
END_OF_TABLE
};
u8 DRXD_InitDiversityEnd[] = {
/* End demod *********** combining RF in and diversity in, MPEG TS out **** */
/* disable near/far; switch on timing slave mode */
WR16(B_SC_RA_RAM_CONFIG__A, B_SC_RA_RAM_CONFIG_FR_ENABLE__M |
B_SC_RA_RAM_CONFIG_FREQSCAN__M |
B_SC_RA_RAM_CONFIG_DIV_ECHO_ENABLE__M |
B_SC_RA_RAM_CONFIG_SLAVE__M |
B_SC_RA_RAM_CONFIG_DIV_BLANK_ENABLE__M
/* MV from CtrlDiversity */
),
#ifdef DRXDDIV_SRMM_SLAVING
WR16(SC_RA_RAM_LC_ABS_2K__A, 0x3c7),
WR16(SC_RA_RAM_LC_ABS_8K__A, 0x3c7),
#else
WR16(SC_RA_RAM_LC_ABS_2K__A, 0x7),
WR16(SC_RA_RAM_LC_ABS_8K__A, 0x7),
#endif
WR16(B_SC_RA_RAM_IR_COARSE_8K_LENGTH__A, IRLEN_COARSE_8K),
WR16(B_SC_RA_RAM_IR_COARSE_8K_FREQINC__A, 1 << (11 - IRLEN_COARSE_8K)),
WR16(B_SC_RA_RAM_IR_COARSE_8K_KAISINC__A, 1 << (17 - IRLEN_COARSE_8K)),
WR16(B_SC_RA_RAM_IR_FINE_8K_LENGTH__A, IRLEN_FINE_8K),
WR16(B_SC_RA_RAM_IR_FINE_8K_FREQINC__A, 1 << (11 - IRLEN_FINE_8K)),
WR16(B_SC_RA_RAM_IR_FINE_8K_KAISINC__A, 1 << (17 - IRLEN_FINE_8K)),
WR16(B_SC_RA_RAM_IR_COARSE_2K_LENGTH__A, IRLEN_COARSE_2K),
WR16(B_SC_RA_RAM_IR_COARSE_2K_FREQINC__A, 1 << (11 - IRLEN_COARSE_2K)),
WR16(B_SC_RA_RAM_IR_COARSE_2K_KAISINC__A, 1 << (17 - IRLEN_COARSE_2K)),
WR16(B_SC_RA_RAM_IR_FINE_2K_LENGTH__A, IRLEN_FINE_2K),
WR16(B_SC_RA_RAM_IR_FINE_2K_FREQINC__A, 1 << (11 - IRLEN_FINE_2K)),
WR16(B_SC_RA_RAM_IR_FINE_2K_KAISINC__A, 1 << (17 - IRLEN_FINE_2K)),
0x01, 0x00, /* */
0x01, 0x06, /* */
0xC2, 0x07, 0x20, 0x00, /* */
0x01, 0x00, /* */
0x01, 0x06, /* */
0xC2, 0x07, 0x30, 0x00, /* */
0x01, 0x00, /* */
0x01, 0x00, /* */
0x01, 0x00, /* */
0x68, 0x00, /* */
0x29, 0x00, /* */
0x28, 0x00, /* */
0x29, 0x00, /* */
0xF8, 0x07, 0x2F, 0x00, /* */
WR16((B_HI_IF_RAM_TRP_BPT0__AX + ((2 * 0) + 1)),
(u16) (HI_RST_FUNC_ADDR & 0x3FF)),
WR16((B_HI_IF_RAM_TRP_BPT0__AX + ((2 * 1) + 1)),
(u16) (HI_RST_FUNC_ADDR & 0x3FF)),
WR16((B_HI_IF_RAM_TRP_BPT0__AX + ((2 * 2) + 1)),
(u16) (HI_RST_FUNC_ADDR & 0x3FF)),
WR16((B_HI_IF_RAM_TRP_BPT0__AX + ((2 * 3) + 1)),
(u16) (HI_RST_FUNC_ADDR & 0x3FF)),
/* */
WR16(B_HI_CT_REG_COMM_STATE__A, 0),
END_OF_TABLE
};
/* */
u8 DRXD_HiI2cPatch_3[] = {
WRBLOCK(HI_RST_FUNC_ADDR, HI_RST_FUNC_SIZE),
