irom static void setclear_perireg(uint32_t reg, uint32_t clear, uint32_t set)
{
uint32_t tmp;
tmp = READ_PERI_REG(reg);
tmp &= (uint32_t)~clear;
tmp |= set;
WRITE_PERI_REG(reg, tmp);
}
/******************************************************************************
* FunctionName : uart1_tx_one_char
* Description : Internal used function
* Use uart1 interface to transfer one char
* Parameters : uint8 TxChar - character to tx
* Returns : OK
*******************************************************************************/
STATUS
uart_tx_one_char(uint8 uart, uint8 c)
{
//Wait until there is room in the FIFO
while (((READ_PERI_REG(UART_STATUS(uart))>>UART_TXFIFO_CNT_S)&UART_TXFIFO_CNT)>=100) ;
//Send the character
WRITE_PERI_REG(UART_FIFO(uart), c);
return OK;
}
static void uart_tx_char(unsigned uartno, char ch) {
while (1) {
uint32 fifo_cnt =
(READ_PERI_REG(UART_DATA_STATUS(uartno)) & 0x00FF0000) >> 16;
if (fifo_cnt < 126) {
break;
}
}
WRITE_PERI_REG(UART_BUF(uartno), ch);
}
static void tx_buff_write_done(void)
{
union sdio_slave_status sdio_sta;
/////modify sdio status reg
sdio_sta.word_value=READ_PERI_REG(SLC_HOST_CONF_W2);
sdio_sta.elm_value.comm_cnt++;
sdio_sta.elm_value.wr_busy=1;
sdio_sta.elm_value.intr_no &= (~TX_AVAILIBLE);
WRITE_PERI_REG(SLC_HOST_CONF_W2, sdio_sta.word_value); //update sdio status register
}
void UARTInit() {
//Enable TxD pin
PIN_PULLUP_DIS(PERIPHS_IO_MUX_U0TXD_U);
PIN_FUNC_SELECT(PERIPHS_IO_MUX_U0TXD_U, FUNC_U0TXD);
//Set baud rate and other serial parameters to 115200,n,8,1
uart_div_modify(0, UART_CLK_FREQ/BIT_RATE_115200);
WRITE_PERI_REG(UART_CONF0(0), (STICK_PARITY_DIS)|(ONE_STOP_BIT << UART_STOP_BIT_NUM_S)| \
(EIGHT_BITS << UART_BIT_NUM_S));
//Reset tx & rx fifo
SET_PERI_REG_MASK(UART_CONF0(0), UART_RXFIFO_RST|UART_TXFIFO_RST);
CLEAR_PERI_REG_MASK(UART_CONF0(0), UART_RXFIFO_RST|UART_TXFIFO_RST);
//Clear pending interrupts
WRITE_PERI_REG(UART_INT_CLR(0), 0xffff);
//Install our own putchar handler
os_install_putc1((void *)UARTPutChar);
}
void esp_uart_deinit(struct esp_uart_state *us) {
WRITE_PERI_REG(UART_INT_ENA(us->cfg->uart_no), 0);
os_timer_disarm(&us->status_timer);
cs_rbuf_deinit(&us->rx_buf);
cs_rbuf_deinit(&us->tx_buf);
memset(us->cfg, 0, sizeof(*us->cfg));
free(us->cfg);
memset(us, 0, sizeof(*us));
free(us);
}
/* @defgroup SPI hardware implementation
* @brief begin()
*
* Initializes the SPI bus using the default SPISettings
*
*/
void SPIClass::begin() {
WRITE_PERI_REG(PERIPHS_IO_MUX, 0x105); //clear bit9
PIN_FUNC_SELECT(PERIPHS_IO_MUX_MTDI_U, 2); // HSPIQ MISO == GPIO12
PIN_FUNC_SELECT(PERIPHS_IO_MUX_MTCK_U, 2); // HSPID MOSI == GPIO13
PIN_FUNC_SELECT(PERIPHS_IO_MUX_MTMS_U, 2); // CLK == GPIO14
prepare(this->SPIDefaultSettings);
}
IRAM NOINSTR static void rx_isr(void *param) {
/* TODO(alashkin): add errors checking */
unsigned int peri_reg = READ_PERI_REG(UART_INTR_STATUS(UART_MAIN));
static volatile int tail = 0;
(void) param;
if ((peri_reg & UART_RXBUF_FULL) != 0 || (peri_reg & UART_RX_NEW) != 0) {
int char_count, i;
CLEAR_PERI_REG_MASK(UART_CTRL_INTR(UART_MAIN),
UART_RXBUF_FULL | UART_RX_NEW);
WRITE_PERI_REG(UART_CLEAR_INTR(UART_MAIN), UART_RXBUF_FULL | UART_RX_NEW);
char_count = READ_PERI_REG(UART_DATA_STATUS(UART_MAIN)) & 0x000000FF;
/* TODO(mkm): handle overrun */
for (i = 0; i < char_count; i++) {
char ch = READ_PERI_REG(UART_BUF(UART_MAIN)) & 0xFF;
if (s_custom_callback != NULL) {
s_custom_callback(ch);
} else {
rx_buf[tail] = ch;
if (rx_buf[tail] == UART_SIGINT_CHAR && uart_interrupt_cb) {
/* swallow the intr byte */
tail = (tail - 1) % RX_BUFFER_SIZE;
uart_interrupt_cb(UART_SIGINT_CHAR);
}
tail = (tail + 1) % RX_BUFFER_SIZE;
}
}
WRITE_PERI_REG(UART_CLEAR_INTR(UART_MAIN), UART_RXBUF_FULL | UART_RX_NEW);
SET_PERI_REG_MASK(UART_CTRL_INTR(UART_MAIN), UART_RXBUF_FULL | UART_RX_NEW);
if (s_custom_callback == NULL) {
#ifndef RTOS_SDK
system_os_post(TASK_PRIORITY, 0, tail);
#else
rtos_dispatch_char_handler(tail);
#endif
}
}
}
void pin_set(uint pin, int value) {
if (pin == 16) {
int out_en = (pin_mode[pin] == GPIO_MODE_OUTPUT);
WRITE_PERI_REG(PAD_XPD_DCDC_CONF, (READ_PERI_REG(PAD_XPD_DCDC_CONF) & 0xffffffbc) | 1);
WRITE_PERI_REG(RTC_GPIO_CONF, READ_PERI_REG(RTC_GPIO_CONF) & ~1);
WRITE_PERI_REG(RTC_GPIO_ENABLE, (READ_PERI_REG(RTC_GPIO_ENABLE) & ~1) | out_en);
WRITE_PERI_REG(RTC_GPIO_OUT, (READ_PERI_REG(RTC_GPIO_OUT) & ~1) | value);
return;
}
uint32_t enable = 0;
uint32_t disable = 0;
switch (pin_mode[pin]) {
case GPIO_MODE_INPUT:
value = -1;
disable = 1;
break;
case GPIO_MODE_OUTPUT:
enable = 1;
break;
case GPIO_MODE_OPEN_DRAIN:
if (value == -1) {
return;
} else if (value == 0) {
enable = 1;
} else {
value = -1;
disable = 1;
}
break;
}
enable <<= pin;
disable <<= pin;
if (value == -1) {
gpio_output_set(0, 0, enable, disable);
} else {
gpio_output_set(value << pin, (1 - value) << pin, enable, disable);
}
}
IRAM void esp_uart_dispatch_bottom(int uart_no) {
struct esp_uart_state *us = s_us[uart_no];
if (us == NULL) return;
cs_rbuf_t *rxb = &us->rx_buf;
cs_rbuf_t *txb = &us->tx_buf;
uint32_t int_ena = UART_INFO_INTS;
/* Determine which interrupts we want. */
if (us->rx_enabled && rxb->avail > 0) int_ena |= UART_RX_INTS;
if (txb->used > 0) int_ena |= UART_TX_INTS;
WRITE_PERI_REG(UART_INT_ENA(uart_no), int_ena);
}
static void hard_i2c_stop(void)
{
int count_ = 1000;
WRITE_PERI_REG(PREG_I2C_MS_TOKEN_LIST_REG0, ((I2C_END << 28) |
(I2C_END << 24) |
(I2C_END << 20) |
(I2C_END << 16) |
(I2C_END << 12) |
(I2C_END << 8) |
(I2C_END << 4) |
(I2C_STOP << 0) ));
// Toggle start low then high
WRITE_PERI_REG(PREG_I2C_MS_CTRL, ((READ_PERI_REG(PREG_I2C_MS_CTRL)) & 0xfffffffe ));
WRITE_PERI_REG(PREG_I2C_MS_CTRL, ((READ_PERI_REG(PREG_I2C_MS_CTRL)) | 0x1 ));
while( ((READ_PERI_REG(PREG_I2C_MS_CTRL)) & (1 << I2C_M_STATUS)) && (count_ -- )); // Wait for the transfer to complete
}
void HardwareSerial::uart0_rx_intr_handler(void *para)
{
/* uart0 and uart1 intr combine togther, when interrupt occur, see reg 0x3ff20020, bit2, bit0 represents
* uart1 and uart0 respectively
*/
RcvMsgBuff *pRxBuff = (RcvMsgBuff *)para;
uint8 RcvChar;
if (UART_RXFIFO_FULL_INT_ST != (READ_PERI_REG(UART_INT_ST(UART_ID_0)) & UART_RXFIFO_FULL_INT_ST))
return;
WRITE_PERI_REG(UART_INT_CLR(UART_ID_0), UART_RXFIFO_FULL_INT_CLR);
while (READ_PERI_REG(UART_STATUS(UART_ID_0)) & (UART_RXFIFO_CNT << UART_RXFIFO_CNT_S))
{
RcvChar = READ_PERI_REG(UART_FIFO(UART_ID_0)) & 0xFF;
/* you can add your handle code below.*/
if (memberData[UART_ID_0].useRxBuff)
{
*(pRxBuff->pWritePos) = RcvChar;
// insert here for get one command line from uart
if (RcvChar == '\n' )
pRxBuff->BuffState = WRITE_OVER;
pRxBuff->pWritePos++;
if (pRxBuff->pWritePos == (pRxBuff->pRcvMsgBuff + RX_BUFF_SIZE))
{
// overflow ...we may need more error handle here.
pRxBuff->pWritePos = pRxBuff->pRcvMsgBuff;
}
if (pRxBuff->pWritePos == pRxBuff->pReadPos)
{ // Prevent readbuffer overflow
if (pRxBuff->pReadPos == (pRxBuff->pRcvMsgBuff + RX_BUFF_SIZE))
{
pRxBuff->pReadPos = pRxBuff->pRcvMsgBuff ;
} else {
pRxBuff->pReadPos++;
}
}
}
if (memberData[UART_ID_0].HWSDelegate)
{
unsigned short cc;
cc = (pRxBuff->pWritePos < pRxBuff->pReadPos) ? ((pRxBuff->pWritePos + RX_BUFF_SIZE) - pRxBuff->pReadPos)
: (pRxBuff->pWritePos - pRxBuff->pReadPos);
memberData[UART_ID_0].HWSDelegate(Serial, RcvChar, cc);
}
}
}
// Init UART1 to be able to stream WS2812 data
// We use GPIO2 as output pin
static void ws2812_init() {
// Configure UART1
// Set baudrate of UART1 to 3200000
WRITE_PERI_REG(UART_CLKDIV(1), UART_CLK_FREQ / 3200000);
// Set UART Configuration No parity / 6 DataBits / 1 StopBits / Invert TX
WRITE_PERI_REG(UART_CONF0(1), UART_TXD_INV | (1 << UART_STOP_BIT_NUM_S) | (1 << UART_BIT_NUM_S));
// Pull GPIO2 down
platform_gpio_mode(4, PLATFORM_GPIO_OUTPUT, PLATFORM_GPIO_FLOAT);
platform_gpio_write(4, 0);
// Waits 10us to simulate a reset
os_delay_us(10);
// Redirect UART1 to GPIO2
// Disable GPIO2
GPIO_REG_WRITE(GPIO_ENABLE_W1TC_ADDRESS, BIT2);
// Enable Function 2 for GPIO2 (U1TXD)
PIN_FUNC_SELECT(PERIPHS_IO_MUX_GPIO2_U, FUNC_U1TXD_BK);
}
IRAM NOINSTR static void esp_handle_uart_int(struct esp_uart_state *us) {
const int uart_no = us->cfg->uart_no;
/* Since both UARTs use the same int, we need to apply the mask manually. */
const unsigned int int_st = READ_PERI_REG(UART_INT_ST(uart_no)) &
READ_PERI_REG(UART_INT_ENA(uart_no));
if (int_st == 0) return;
us->stats.ints++;
if (int_st & UART_RXFIFO_OVF_INT_ST) us->stats.rx_overflows++;
if (int_st & UART_CTS_CHG_INT_ST) {
if (cts(uart_no) != 0 && tx_fifo_len(uart_no) > 0) us->stats.tx_throttles++;
}
if (int_st & (UART_RX_INTS | UART_TX_INTS)) {
if (int_st & UART_RX_INTS) us->stats.rx_ints++;
if (int_st & UART_TX_INTS) us->stats.tx_ints++;
/* Wake up the processor and disable TX and RX ints until it runs. */
WRITE_PERI_REG(UART_INT_ENA(uart_no), UART_INFO_INTS);
us->cfg->dispatch_cb(uart_no);
}
WRITE_PERI_REG(UART_INT_CLR(uart_no), int_st);
}
static uint32 get_gpio16()
{
// set output level to 1
WRITE_PERI_REG(RTC_GPIO_OUT, (READ_PERI_REG(RTC_GPIO_OUT) & (uint32)0xfffffffe) | (uint32)(1));
// read level
WRITE_PERI_REG(PAD_XPD_DCDC_CONF,
(READ_PERI_REG(PAD_XPD_DCDC_CONF) & 0xffffffbc)
| (uint32)0x1); // mux configuration for XPD_DCDC and
// rtc_gpio0 connection
WRITE_PERI_REG(RTC_GPIO_CONF,
(READ_PERI_REG(RTC_GPIO_CONF) & (uint32)0xfffffffe)
| (uint32)0x0); // mux configuration for out enable
WRITE_PERI_REG(
RTC_GPIO_ENABLE, READ_PERI_REG(RTC_GPIO_ENABLE) & (uint32)0xfffffffe); // out disable
uint32 x = (READ_PERI_REG(RTC_GPIO_IN_DATA) & 1);
return x;
}
/// @brief HSPI Initiaization - with automatic chip select
/// Pins:
/// MISO GPIO12
/// MOSI GPIO13
/// CLK GPIO14
/// CS GPIO15 - optional
/// DC GPIO2
/// @param[in] prescale: prescale from CPU clock 0 .. 0x1fff
/// @param[in] hwcs: enable GPIO15 hardware chip select
/// @return void
void hspi_init(uint16_t prescale, int hwcs)
{
// We only make changes if the speed changes
if(prescale == hspi_clock)
return;
hspi_clock = prescale;
PIN_FUNC_SELECT(PERIPHS_IO_MUX_MTDI_U, 2); // HSPIQ MISO GPIO12
PIN_FUNC_SELECT(PERIPHS_IO_MUX_MTCK_U, 2); // HSPID MOSI GPIO13
PIN_FUNC_SELECT(PERIPHS_IO_MUX_MTMS_U, 2); // CLK GPIO14
// HARDWARE SPI CS
if(hwcs)
PIN_FUNC_SELECT(PERIPHS_IO_MUX_MTDO_U, 2); // CS AUTOMATIC ONLY ON GPIO15
if(prescale == 0)
{
WRITE_PERI_REG(PERIPHS_IO_MUX, 0x305); //set bit9
WRITE_PERI_REG(SPI_FLASH_CLOCK(HSPI), SPI_CLK_EQU_SYSCLK);
}
else
{
// prescale >= 1
WRITE_PERI_REG(PERIPHS_IO_MUX, 0x105); //clear bit9
WRITE_PERI_REG(SPI_FLASH_CLOCK(HSPI),
(((prescale - 1) & SPI_CLKDIV_PRE) << SPI_CLKDIV_PRE_S) |
((1 & SPI_CLKCNT_N) << SPI_CLKCNT_N_S) |
((0 & SPI_CLKCNT_H) << SPI_CLKCNT_H_S) |
((1 & SPI_CLKCNT_L) << SPI_CLKCNT_L_S));
/*
WRITE_PERI_REG(SPI_FLASH_CLOCK(HSPI),
(((prescale - 1) & SPI_CLKDIV_PRE) << SPI_CLKDIV_PRE_S) |
((1 & SPI_CLKCNT_N) << SPI_CLKCNT_N_S) |
((0 & SPI_CLKCNT_H) << SPI_CLKCNT_H_S) |
((1 & SPI_CLKCNT_L) << SPI_CLKCNT_L_S));
*/
}
WRITE_PERI_REG(SPI_FLASH_CTRL1(HSPI), 0);
}
static void rx_buff_read_done(void)
{
union sdio_slave_status sdio_sta;
/////modify sdio status reg
sdio_sta.word_value=READ_PERI_REG(SLC_HOST_CONF_W2);
sdio_sta.elm_value.comm_cnt++;
sdio_sta.elm_value.rd_empty=1;
sdio_sta.elm_value.rx_length=0;
sdio_sta.elm_value.intr_no &= (~RX_AVAILIBLE);
WRITE_PERI_REG(SLC_HOST_CONF_W2, sdio_sta.word_value); //update sdio status register
//os_printf("rx_buff_read_done\r\n");
}
bool mgos_uart_hal_init(struct mgos_uart_state *us) {
/* Start with ints disabled. */
WRITE_PERI_REG(UART_INT_ENA(us->uart_no), 0);
#ifdef RTOS_SDK
_xt_isr_mask(1 << ETS_UART_INUM);
_xt_isr_attach(ETS_UART_INUM, (void *) esp_uart_isr, NULL);
#else
ETS_INTR_DISABLE(ETS_UART_INUM);
ETS_UART_INTR_ATTACH(esp_uart_isr, NULL);
#endif
return true;
}
int gdb_read_uart_buf(char *buf) {
unsigned int peri_reg = READ_PERI_REG(UART_INTR_STATUS(UART_MAIN));
if ((peri_reg & UART_RXBUF_FULL) != 0 || (peri_reg & UART_RX_NEW) != 0) {
int char_count, i;
CLEAR_PERI_REG_MASK(UART_CTRL_INTR(UART_MAIN),
UART_RXBUF_FULL | UART_RX_NEW);
WRITE_PERI_REG(UART_CLEAR_INTR(UART_MAIN), UART_RXBUF_FULL | UART_RX_NEW);
char_count = READ_PERI_REG(UART_DATA_STATUS(UART_MAIN)) & 0x000000FF;
for (i = 0; i < char_count; i++) {
buf[i] = READ_PERI_REG(UART_BUF(UART_MAIN)) & 0xFF;
}
WRITE_PERI_REG(UART_CLEAR_INTR(UART_MAIN), UART_RXBUF_FULL | UART_RX_NEW);
SET_PERI_REG_MASK(UART_CTRL_INTR(UART_MAIN), UART_RXBUF_FULL | UART_RX_NEW);
return char_count;
}
return 0;
}
void mp_hal_pin_config_od(mp_hal_pin_obj_t pin_id) {
const pyb_pin_obj_t *pin = &pyb_pin_obj[pin_id];
if (pin->phys_port == 16) {
// configure GPIO16 as input with output register holding 0
WRITE_PERI_REG(PAD_XPD_DCDC_CONF, (READ_PERI_REG(PAD_XPD_DCDC_CONF) & 0xffffffbc) | 1);
WRITE_PERI_REG(RTC_GPIO_CONF, READ_PERI_REG(RTC_GPIO_CONF) & ~1);
WRITE_PERI_REG(RTC_GPIO_ENABLE, (READ_PERI_REG(RTC_GPIO_ENABLE) & ~1)); // input
WRITE_PERI_REG(RTC_GPIO_OUT, (READ_PERI_REG(RTC_GPIO_OUT) & ~1)); // out=0
return;
}
ETS_GPIO_INTR_DISABLE();
PIN_FUNC_SELECT(pin->periph, pin->func);
GPIO_REG_WRITE(GPIO_PIN_ADDR(GPIO_ID_PIN(pin->phys_port)),
GPIO_REG_READ(GPIO_PIN_ADDR(GPIO_ID_PIN(pin->phys_port)))
| GPIO_PIN_PAD_DRIVER_SET(GPIO_PAD_DRIVER_ENABLE)); // open drain
GPIO_REG_WRITE(GPIO_ENABLE_ADDRESS,
GPIO_REG_READ(GPIO_ENABLE_ADDRESS) | (1 << pin->phys_port));
ETS_GPIO_INTR_ENABLE();
}
uint32_t platform_s_flash_read( void *to, uint32_t fromaddr, uint32_t size )
{
fromaddr -= INTERNAL_FLASH_START_ADDRESS;
SpiFlashOpResult r;
WRITE_PERI_REG(0x60000914, 0x73);
r = flash_read(fromaddr, (uint32 *)to, size);
if(SPI_FLASH_RESULT_OK == r)
return size;
else{
NODE_ERR( "ERROR in flash_read: r=%d at %08X\n", ( int )r, ( unsigned )fromaddr+INTERNAL_FLASH_START_ADDRESS );
return 0;
}
}
void spi_reinit(spi_config *config)
{
current_spi_port = config->spi_port;
spi_fifo = (uint32_t*)SPI_FLASH_C0(current_spi_port);
uint32_t regvalue = SPI_FLASH_DOUT;
WRITE_PERI_REG(SPI_FLASH_CLOCK(current_spi_port), config->clock_reg_val);
WRITE_PERI_REG(SPI_FLASH_CTRL1(current_spi_port), 0);
switch(config->mode)
{
case spi_mode_tx:
regvalue &= ~(BIT2 | SPI_FLASH_USR_ADDR | SPI_FLASH_USR_DUMMY | SPI_FLASH_USR_DIN | SPI_USR_COMMAND | SPI_DOUTDIN);
break;
case spi_mode_txrx:
regvalue |= SPI_DOUTDIN | SPI_CK_I_EDGE;
regvalue &= ~(BIT2 | SPI_FLASH_USR_ADDR | SPI_FLASH_USR_DUMMY | SPI_FLASH_USR_DIN | SPI_USR_COMMAND);
break;
}
WRITE_PERI_REG(SPI_FLASH_USER(current_spi_port), regvalue);
}
/**
* @brief Load data to send buffer by slave mode.
*
*/
int ICACHE_FLASH_ATTR SPISlaveSendData(SpiNum spiNum, uint32_t *pInData, uint8_t inLen)
{
if (NULL == pInData) {
return -1;
}
char i;
for (i = 0; i < inLen; ++i) {
WRITE_PERI_REG((SPI_W8(spiNum) + (i << 2)), *pInData++);
}
// Enable slave transmission liston
SET_PERI_REG_MASK(SPI_CMD(spiNum), SPI_USR);
return 0;
}
void mgos_uart_hal_dispatch_bottom(struct mgos_uart_state *us) {
uint32_t int_ena = UART_INFO_INTS;
/* Determine which interrupts we want. */
if (us->rx_enabled) {
if (mgos_uart_rxb_free(us) > 0) {
int_ena |= UART_RX_INTS;
}
if (adj_rx_fifo_full_thresh(us)) {
int_ena |= UART_RXFIFO_FULL_INT_ENA;
}
}
if (us->tx_buf.len > 0) int_ena |= UART_TX_INTS;
WRITE_PERI_REG(UART_INT_ENA(us->uart_no), int_ena);
}
IRAM bool adj_rx_fifo_full_thresh(struct mgos_uart_state *us) {
int uart_no = us->uart_no;
uint8_t thresh = us->cfg.dev.rx_fifo_full_thresh;
uint8_t rx_fifo_len = esp_uart_rx_fifo_len(uart_no);
if (rx_fifo_len >= thresh && us->cfg.rx_fc_type == MGOS_UART_FC_SW) {
thresh = us->cfg.dev.rx_fifo_fc_thresh;
}
if (get_rx_fifo_full_thresh(uart_no) != thresh) {
uint32_t conf1 = READ_PERI_REG(UART_CONF1(uart_no));
conf1 = (conf1 & ~0x7f) | thresh;
WRITE_PERI_REG(UART_CONF1(uart_no), conf1);
}
return (rx_fifo_len < thresh);
}
/**
* @brief Send data to slave(ESP8266 register of RD_STATUS or WR_STATUS).
*
*/
void ICACHE_FLASH_ATTR SPIMasterSendStatus(SpiNum spiNum, uint8_t data)
{
if (spiNum > SpiNum_HSPI) {
return;
}
while (READ_PERI_REG(SPI_CMD(spiNum))&SPI_USR);
// Enable MOSI
SET_PERI_REG_MASK(SPI_USER(spiNum), SPI_USR_MOSI);
CLEAR_PERI_REG_MASK(SPI_USER(spiNum), SPI_USR_MISO | SPI_USR_DUMMY | SPI_USR_ADDR);
// 8bits cmd, 0x04 is eps8266 slave write cmd value
WRITE_PERI_REG(SPI_USER2(spiNum),
((7 & SPI_USR_COMMAND_BITLEN) << SPI_USR_COMMAND_BITLEN_S)
| MASTER_WRITE_STATUS_TO_SLAVE_CMD);
// Set data send buffer length.
SET_PERI_REG_BITS(SPI_USER1(spiNum), SPI_USR_MOSI_BITLEN,
((sizeof(data) << 3) - 1), SPI_USR_MOSI_BITLEN_S);
WRITE_PERI_REG(SPI_W0(spiNum), (uint32)(data));
// Start SPI
SET_PERI_REG_MASK(SPI_CMD(spiNum), SPI_USR);
}
// Lua: delay( us )
static int tmr_delay( lua_State* L )
{
s32 us;
us = luaL_checkinteger( L, 1 );
if ( us <= 0 )
return luaL_error( L, "wrong arg range" );
if(us<1000000)
{
os_delay_us( us );
WRITE_PERI_REG(0x60000914, 0x73);
return 0;
}
unsigned sec = (unsigned)us / 1000000;
unsigned remain = (unsigned)us % 1000000;
int i = 0;
for(i=0;i<sec;i++){
os_delay_us( 1000000 );
WRITE_PERI_REG(0x60000914, 0x73);
}
if(remain>0)
os_delay_us( remain );
return 0;
}
void uart_isr(void *arg) {
uint32_t int_st = READ_PERI_REG(UART_INT_ST(0));
while (1) {
uint32_t fifo_len = READ_PERI_REG(UART_STATUS(0)) & 0xff;
if (fifo_len == 0) {
break;
}
while (fifo_len-- > 0) {
uint8_t byte = READ_PERI_REG(UART_FIFO(0)) & 0xff;
uart_isr_receive(byte);
}
}
WRITE_PERI_REG(UART_INT_CLR(0), int_st);
}
void HardwareSerial::begin(const uint32_t baud/* = 9600*/)
{
//TODO: Move to params!
UartDev.baut_rate = (UartBautRate)baud;
UartDev.parity = NONE_BITS;
UartDev.exist_parity = STICK_PARITY_DIS;
UartDev.stop_bits = ONE_STOP_BIT;
UartDev.data_bits = EIGHT_BITS;
ETS_UART_INTR_ATTACH((void*)uart0_rx_intr_handler, &(UartDev.rcv_buff));
PIN_PULLUP_DIS(PERIPHS_IO_MUX_U0TXD_U);
PIN_FUNC_SELECT(PERIPHS_IO_MUX_U0TXD_U, FUNC_U0TXD);
uart_div_modify(uart, UART_CLK_FREQ / (UartDev.baut_rate));
WRITE_PERI_REG(UART_CONF0(uart), UartDev.exist_parity
| UartDev.parity
| (UartDev.stop_bits << UART_STOP_BIT_NUM_S)
| (UartDev.data_bits << UART_BIT_NUM_S));
//clear rx and tx fifo,not ready
SET_PERI_REG_MASK(UART_CONF0(uart), UART_RXFIFO_RST | UART_TXFIFO_RST);
CLEAR_PERI_REG_MASK(UART_CONF0(uart), UART_RXFIFO_RST | UART_TXFIFO_RST);
//set rx fifo trigger
WRITE_PERI_REG(UART_CONF1(uart), (UartDev.rcv_buff.TrigLvl & UART_RXFIFO_FULL_THRHD) << UART_RXFIFO_FULL_THRHD_S);
//clear all interrupt
WRITE_PERI_REG(UART_INT_CLR(uart), 0xffff);
//enable rx_interrupt
SET_PERI_REG_MASK(UART_INT_ENA(uart), UART_RXFIFO_FULL_INT_ENA);
ETS_UART_INTR_ENABLE();
delay(10);
Serial.println("\r\n"); // after SPAM :)
}
static void ICACHE_FLASH_ATTR recvTask(os_event_t *events)
{
uint8_t i;
while (READ_PERI_REG(UART_STATUS(UART0)) & (UART_RXFIFO_CNT << UART_RXFIFO_CNT_S))
{
WRITE_PERI_REG(0X60000914, 0x73); //WTD
uint16 length = 0;
while ((READ_PERI_REG(UART_STATUS(UART0)) & (UART_RXFIFO_CNT << UART_RXFIFO_CNT_S)) && (length<MAX_UARTBUFFER))
uartbuffer[length++] = READ_PERI_REG(UART_FIFO(UART0)) & 0xFF;
for (i = 0; i < MAX_CONN; ++i)
if (connData[i].conn)
espbuffsent(&connData[i], uartbuffer, length);
}
if(UART_RXFIFO_FULL_INT_ST == (READ_PERI_REG(UART_INT_ST(UART0)) & UART_RXFIFO_FULL_INT_ST))
{
WRITE_PERI_REG(UART_INT_CLR(UART0), UART_RXFIFO_FULL_INT_CLR);
}
else if(UART_RXFIFO_TOUT_INT_ST == (READ_PERI_REG(UART_INT_ST(UART0)) & UART_RXFIFO_TOUT_INT_ST))
{
WRITE_PERI_REG(UART_INT_CLR(UART0), UART_RXFIFO_TOUT_INT_CLR);
}
ETS_UART_INTR_ENABLE();
}
