VOID
HalpResetP9100(
VOID
)
/*++
Routine Description:
This routine initializes the VGA part of an Orchid P9000VLB or Diamond Viper card
Arguments:
None.
Return Value:
None.
--*/
{
LONG IcdVal;
int i;
//
// First, reprogram register broken by the p9100 driver
//
switch (HalpMainBoard) {
case M8036:
WRITE_REGISTER_UCHAR (0xbfcc0000, 0x00); // RM200
break;
case M8042 :
WRITE_REGISTER_UCHAR (0xbc010000, 0xff); // RM400 MT
break;
case M8032 :
WRITE_REGISTER_UCHAR (0xbc0c0000, 0xff); // RM400 T
break;
}
//
// unlock and disable the P9000 on the board
//
WRITE_REGISTER_UCHAR (VGA_SEQ_IDX, 0x11);
WRITE_REGISTER_UCHAR (VGA_SEQ_DATA,0x00); // unlock extended SEQ reg
WRITE_REGISTER_UCHAR (VGA_SEQ_DATA,0x00);
WRITE_REGISTER_UCHAR (VGA_SEQ_DATA,0x00);
WRITE_REGISTER_UCHAR (VGA_SEQ_IDX, 0x12); // select extended reg 0x12
if (HalpVideoBoard == P9000_ORCHID) {
WRITE_REGISTER_UCHAR (VGA_SEQ_DATA, 0x08);
} else {
WRITE_REGISTER_UCHAR (VGA_SEQ_DATA, 0x88);
}
//
// init the clock generator, we use use the 80x50 Text mode
// so we need a 25.175Mhz clock
//
// if(( IcdVal = ICD2061CalcClockgen(25175)) == -1){
// DebugPrint(("HAL: Error calculating ICD Value for 25.175Mhz\n"));
// }
// byte = READ_REGISTER_UCHAR((PUCHAR) VGA_MISC_WRITE);
IcdVal = 0x7170a0;ICD2061LoadClockgen((PUCHAR) VGA_MISC_WRITE , IcdVal, 2);
IcdVal = 0x01a8bc;ICD2061LoadClockgen((PUCHAR) VGA_MISC_WRITE , IcdVal, 2);
IcdVal = 0x2560ac;ICD2061LoadClockgen((PUCHAR) VGA_MISC_WRITE , IcdVal, 2);
IcdVal = 0x4560ac;ICD2061LoadClockgen((PUCHAR) VGA_MISC_WRITE , IcdVal, 2);
// WRITE_REGISTER_UCHAR((PUCHAR) VGA_MISC_WRITE,byte);
WRITE_REGISTER_UCHAR(VGA_MISC_WRITE, 0x67) ; // 28.322 Mhz - crt ad = 3dx
//
// if this is the first initialisation i.e. Systemboot,
// the firmware has initialized the VGA part properly
//
if (HalpFirstBoot) return;
WRITE_REGISTER_UCHAR( P9100_CFG_IDX, P9100_CONFIG_REG); // enable VGA
WRITE_REGISTER_UCHAR( P9100_CFG_DATA, 0x02);
WRITE_REGISTER_UCHAR( P9100_CFG_IDX, P9100_COMMAND_REG); // enable I/O space - ctl VGA palette snoop
WRITE_REGISTER_UCHAR( P9100_CFG_DATA, 0x83);
WRITE_REGISTER_UCHAR( P9100_CFG_IDX, P9100_MEM_BASE_ADDR_REG); // why not...
WRITE_REGISTER_UCHAR( P9100_CFG_DATA, 0x00);
// init ramdac (bug workaround + other unknown things...)
WRITE_REGISTER_UCHAR( P9100_CFG_IDX, P9100_CONFIG_REG); // enable VGA
WRITE_REGISTER_UCHAR( P9100_CFG_DATA, 0x00);
WRITE_REGISTER_ULONG( P9100_RAMDAC_HIGH_ADDR, 0x00000000);
WRITE_REGISTER_ULONG( P9100_RAMDAC_LOW_ADDR, 0x90909090);
WRITE_REGISTER_ULONG( P9100_RAMDAC_CTRL, 0x01010101);
WRITE_REGISTER_ULONG( P9100_RAMDAC_DATA, 0x03030303);
WRITE_REGISTER_ULONG( P9100_RAMDAC_HIGH_ADDR, 0x00000000);
WRITE_REGISTER_ULONG( P9100_RAMDAC_LOW_ADDR, 0x70707070);
WRITE_REGISTER_ULONG( P9100_RAMDAC_CTRL, 0x01010101);
WRITE_REGISTER_ULONG( P9100_RAMDAC_DATA, 0x40404040);
WRITE_REGISTER_ULONG( P9100_RAMDAC_HIGH_ADDR, 0x00000000);
WRITE_REGISTER_ULONG( P9100_RAMDAC_LOW_ADDR, 0x0a0a0a0a);
WRITE_REGISTER_ULONG( P9100_RAMDAC_CTRL, 0x02020202);
WRITE_REGISTER_ULONG( P9100_RAMDAC_DATA, 0x40404040);
WRITE_REGISTER_ULONG( P9100_RAMDAC_HIGH_ADDR, 0x00000000);
WRITE_REGISTER_ULONG( P9100_RAMDAC_LOW_ADDR, 0x71717171);
WRITE_REGISTER_ULONG( P9100_RAMDAC_CTRL, 0x01010101);
WRITE_REGISTER_ULONG( P9100_RAMDAC_DATA, 0x40404040);
WRITE_REGISTER_ULONG( P9100_RAMDAC_HIGH_ADDR, 0x00000000);
WRITE_REGISTER_ULONG( P9100_RAMDAC_LOW_ADDR, 0x71717171);
WRITE_REGISTER_ULONG( P9100_RAMDAC_CTRL, 0x01010101);
WRITE_REGISTER_ULONG( P9100_RAMDAC_DATA, 0x00000000);
WRITE_REGISTER_ULONG( P9100_RAMDAC_HIGH_ADDR, 0x00000000);
WRITE_REGISTER_ULONG( P9100_RAMDAC_LOW_ADDR, 0x02020202);
WRITE_REGISTER_ULONG( P9100_RAMDAC_CTRL, 0x01010101);
for(i=2;i <= 0x72; ++i) {
WRITE_REGISTER_ULONG( P9100_RAMDAC_DATA, 0x00000000);
}
WRITE_REGISTER_ULONG( P9100_RAMDAC_HIGH_ADDR, 0x00000000);
WRITE_REGISTER_ULONG( P9100_RAMDAC_CTRL, 0x00000000);
WRITE_REGISTER_ULONG( P9100_RAMDAC_LOW_ADDR, 0x02020202);
WRITE_REGISTER_ULONG( P9100_RAMDAC_DATA, 0x01010101);
WRITE_REGISTER_ULONG( P9100_RAMDAC_LOW_ADDR, 0x0a0a0a0a);
WRITE_REGISTER_ULONG( P9100_RAMDAC_DATA, 0x03030303);
WRITE_REGISTER_ULONG( P9100_RAMDAC_LOW_ADDR, 0x14141414);
WRITE_REGISTER_ULONG( P9100_RAMDAC_DATA, 0x0e0e0e0e);
WRITE_REGISTER_ULONG( P9100_RAMDAC_LOW_ADDR, 0x20202020);
WRITE_REGISTER_ULONG( P9100_RAMDAC_DATA, 0x24242424);
WRITE_REGISTER_ULONG( P9100_RAMDAC_LOW_ADDR, 0x21212121);
WRITE_REGISTER_ULONG( P9100_RAMDAC_DATA, 0x30303030);
WRITE_REGISTER_UCHAR( P9100_CFG_IDX, P9100_CONFIG_REG); // enable VGA
WRITE_REGISTER_UCHAR( P9100_CFG_DATA, 0x02);
WRITE_REGISTER_UCHAR(VGA_MISC_WRITE, 0x67) ; // 28.322 Mhz - crt ad = 3dx
}
BOOLEAN
HalMakeBeep(
IN ULONG Frequency
)
/*++
Routine Description:
This function sets the frequency of the speaker, causing it to sound a
tone. The tone will sound until the speaker is explicitly turned off,
so the driver is responsible for controlling the duration of the tone.
Arguments:
Frequency - Supplies the frequency of the desired tone. A frequency of
0 means the speaker should be shut off.
Return Value:
TRUE - Operation was successful (frequency within range or zero).
FALSE - Operation was unsuccessful (frequency was out of range).
Current tone (if any) is unchanged.
--*/
{
KIRQL OldIrql;
NMI_STATUS NmiStatus;
PEISA_CONTROL controlBase = HalpEisaControlBase;
TIMER_CONTROL timerControl;
ULONG newCount;
BOOLEAN Result;
if ( HalpPmpRevision >= 3 ) {
//
// For PMP V3, we are NOT using speaker timer in ESC for speaker tone.
// Need to add code to generate via sound card.
//
Result = TRUE;
return Result;
}
//
// Raise IRQL to dispatch level and acquire the beep spin lock.
//
KeAcquireSpinLock(&HalpBeepLock, &OldIrql);
//
// Stop the speaker.
//
*((PUCHAR)&NmiStatus) = READ_REGISTER_UCHAR(&controlBase->NmiStatus);
NmiStatus.SpeakerGate = 0;
NmiStatus.SpeakerData = 0;
WRITE_REGISTER_UCHAR(&controlBase->NmiStatus, *((PUCHAR)&NmiStatus));
//
// If the specified frequency is zero, then the speaker is to be stopped.
//
if (Frequency == 0) {
Result = TRUE;
} else {
//
// If the new count has a magnitude less than 65,536 (0x10000), then
// set the speaker time to the correct mode. Otherwise, return a value
// of FALSE sinc ethe frequency is out of range.
//
newCount = TIMER_CLOCK_IN / Frequency;
if (newCount >= 0x10000) {
Result = FALSE;
} else {
//
// Set the speaker timer to the correct mode.
//
timerControl.BcdMode = 0;
timerControl.Mode = TM_SQUARE_WAVE;
timerControl.SelectByte = SB_LSB_THEN_MSB;
timerControl.SelectCounter = SELECT_COUNTER_2;
WRITE_REGISTER_UCHAR(&controlBase->CommandMode1, *((PUCHAR) &timerControl));
//
// Set the speaker timer to the correct mode.
//
WRITE_REGISTER_UCHAR(&controlBase->SpeakerTone, (UCHAR)(newCount & 0xff));
WRITE_REGISTER_UCHAR(&controlBase->SpeakerTone, (UCHAR)(newCount >> 8));
//
// Start the speaker.
//
NmiStatus.SpeakerGate = 1;
NmiStatus.SpeakerData = 1;
WRITE_REGISTER_UCHAR(&controlBase->NmiStatus, *((PUCHAR) &NmiStatus));
Result = TRUE;
}
}
//
// Release the beep spin lock and lower IRQL to its previous value.
//
KeReleaseSpinLock(&HalpBeepLock, OldIrql);
return Result;
}
VOID
HalpVGASetup(
VOID
)
/*++
Routine Description:
This routine initializes a VGA based Graphic card
Arguments:
None.
Return Value:
None.
--*/
{
UCHAR byte;
switch (HalpVideoBoard){
case S3_GENERIC_VLB:
case CIRRUS_GENERIC_VLB:
case VGA_GENERIC_VLB:
case P9100_WEITEK:
//
// N.B.
// on an SNI desktop model the VL I/O space is transparent, so
// acces in the normal Backplane area results in correct values
// the minitower instead, does not decode all VL signals correct,
// so ther is an EXTRA I/O space for accessing VL I/O (0x1exxxxxx)
// this is handled in the definition of VESA_IO in SNIdef.h
//
HalpVGAControlBase = (HalpIsRM200) ? (PVOID)HalpEisaControlBase : (PVOID)VESA_IO;
VideoBuffer = ( PUSHORT)( VESA_BUS + 0xb8000);
FontBuffer = ( PUCHAR )( VESA_BUS + 0xa0000);
break;
case CIRRUS_ONBOARD:
HalpVGAControlBase = (PVOID)HalpOnboardControlBase;
VideoBuffer = ( PUSHORT)( RM200_ONBOARD_MEMORY + 0xb8000);
FontBuffer = ( PUCHAR )( RM200_ONBOARD_MEMORY + 0xa0000);
break;
case S3_GENERIC:
case CIRRUS_GENERIC:
case VGA_GENERIC:
default:
HalpVGAControlBase = (PVOID)HalpEisaControlBase;
VideoBuffer = ( PUSHORT)( EISA_MEMORY_BASE + 0xb8000);
FontBuffer = ( PUCHAR )( EISA_MEMORY_BASE + 0xa0000);
break;
}
//
// if "only" VGA is detected look for an S3 or cirrus chip (VGA ON ATBUS)
// if the firmware detects an S3 chip, look if this is an 805i (interleave)
//
if ((HalpVideoChip == VGA) || (HalpVideoChip == S3)){
WRITE_REGISTER_USHORT(VGA_SEQ_IDX, 0x1206); // look for Cirrus chips
byte = READ_REGISTER_UCHAR(VGA_SEQ_DATA); // read it back
if (byte != 0x12) { // no cirrus
WRITE_REGISTER_USHORT(VGA_CRT_IDX, 0x4838); // unlock the S3 regs
WRITE_REGISTER_USHORT(VGA_CRT_IDX, 0xa539); // Unlock the SC regs
WRITE_REGISTER_UCHAR(VGA_CRT_IDX, 0x30); // look for s3 chip id
byte = READ_REGISTER_UCHAR(VGA_CRT_DATA) ; // look only for major id
switch (byte & 0xf0){
case 0xa0: // 801/805 chipset
if (byte == 0xa8) { // the new 805i (interleave)
// DebugPrint(("HAL: Found the new 805i Chip resetting to 805 mode\n"));
WRITE_REGISTER_USHORT(VGA_CRT_IDX, 0x0053);
WRITE_REGISTER_USHORT(VGA_CRT_IDX, 0x0067);
}
case 0x80:
case 0x90:
// DebugPrint(("HAL: Found S3 Chip set - Chip id 0x%x\n",byte));
HalpVideoChip = S3;
WRITE_REGISTER_USHORT(VGA_CRT_IDX, 0x0038); // lock s3 regs
WRITE_REGISTER_USHORT(VGA_CRT_IDX, 0x0039); // lock more s3 regs
break;
default: DebugPrint(("HAL: This seems to be no S3 Chip\n"));
}
} else { // this may be an cirrus
WRITE_REGISTER_UCHAR(VGA_CRT_IDX, 0x27); // cirrus id reg
byte = READ_REGISTER_UCHAR(VGA_CRT_DATA);
if ((byte & 0xe0) == 0x80) { // look for 100xxxxx
// DebugPrint(("HAL: Found Cirrus Chip set - Chip id 0x%x\n",byte));
HalpVideoChip = CIRRUS;
WRITE_REGISTER_USHORT(VGA_SEQ_IDX, 0x0006); // lock Cirrus extensions
}
}
}
switch (HalpVideoChip) {
case VGA_P9000:
HalpResetP9000();
//
// we have programmed the clock into register 0 of the ICD2061, so
// select it via the VGA_MISC register
//
// WRITE_REGISTER_UCHAR(VGA_MISC_WRITE, 0xa3);
break;
case S3: HalpResetS3Chip();
break;
case CIRRUS: HalpResetCirrusChip();
break;
case VGA_P9100:
HalpResetP9100();
break;
default: ;
}
HalpInitializeVGADisplay(TEXT_80x50);
//
// Initialize the current display column, row, and ownership values.
//
HalpColumn = 0;
HalpRow = 0;
HalpDisplayOwnedByHal = TRUE;
return;
}
VOID
HalpInitializeVGADisplay(
TEXT_MODE TextMode
)
{
static UCHAR _80x50_crt_regs [MAX_CRT] = { // 80x50 text mode
0x5f, 0x4f, 0x50, 0x82, 0x55, // cr0 - cr4
0x81, 0xBF, 0x1f, 0x0, 0x47, // cr9 - 7 lines per char
0x20, 0x00, 0x00, 0x00, 0x00, // cra - cursor off
0x00, 0x9c, 0x8e, 0x8f, 0x28,
0x1f, 0x96, 0xb9, 0xa3, 0xff
};
static UCHAR _132x50_crt_regs [MAX_CRT] = { // 132x50 text mode
0xa0, 0x83, 0x84, 0x83, 0x8a, // cr0 - cr4
0x9e, 0xBF, 0x1f, 0x0, 0x47, // cr9 - 7 lines per char
0x20, 0x00, 0x00, 0x00, 0x00,
0x00, 0x9c, 0x85, 0x8f, 0x42,
0x1f, 0x95, 0xa5, 0xa3, 0xff
};
static UCHAR default_graph_regs[GRAPH_MAX] =
{
0x00, 0x00, 0x00, 0x00, 0x00,
0x10, 0x0e, 0x00, 0xff
};
static UCHAR default_pal_regs[MAX_PALETTE] = {
0x00, 0x01, 0x02, 0x03, 0x04,
0x05, 0x14, 0x7, 0x38, 0x39,
0x3A, 0x3B, 0x3C, 0x3d, 0x3e,
0x3f, 0x08, 0x00, 0x0f, 0x00,
0x00
};
int i;
UCHAR byte;
// reset ATC FlipFlop
byte = READ_REGISTER_UCHAR(VGA_ATC_FF);
WRITE_REGISTER_UCHAR(VGA_ATC_DATA, 0); // Disable palette
// stop the sequencer
WRITE_REGISTER_USHORT(VGA_SEQ_IDX, 0x0100);
if (TextMode == TEXT_132x50) {
// external clock (40MHz)
WRITE_REGISTER_UCHAR(VGA_MISC_WRITE, 0xAF);
} else {
// COLOR registers , enable RAM, 25 MHz (???) 400 Lines,
if (HalpVideoChip == VGA_P9100) {
WRITE_REGISTER_UCHAR(VGA_MISC_WRITE, 0x67) ; // 28.322 Mhz
} else {
WRITE_REGISTER_UCHAR(VGA_MISC_WRITE, 0x63) ; // 25,175 MHz (don't use with P9100).
}
}
// Select the timing sequencer values
// 8 dot/char
WRITE_REGISTER_USHORT(VGA_SEQ_IDX, 0x0101);
WRITE_REGISTER_USHORT(VGA_SEQ_IDX, 0x0302);
WRITE_REGISTER_USHORT(VGA_SEQ_IDX, 0x0003);
WRITE_REGISTER_USHORT(VGA_SEQ_IDX, 0x0204);
// start the sequencer
WRITE_REGISTER_USHORT(VGA_SEQ_IDX, 0x0300);
// Unprotect CRT regs and program them
WRITE_REGISTER_USHORT(VGA_CRT_IDX , 0x0011);
for(i=0; i<MAX_CRT; i++) {
WRITE_REGISTER_UCHAR(VGA_CRT_IDX, i);
if (TextMode == TEXT_132x50){
WRITE_REGISTER_UCHAR(VGA_CRT_DATA, _132x50_crt_regs[i]);
} else {
WRITE_REGISTER_UCHAR(VGA_CRT_DATA, _80x50_crt_regs[i]);
}
}
DownLoadVGAFont();
HalpDisplayWidth = (TextMode == TEXT_132x50) ? 132 : 80;
HalpDisplayText = 50;
HalpClearVGADisplay();
i = READ_REGISTER_UCHAR(VGA_ATC_FF); // Reset attr FF
if (!HalpFirstBoot) {
//
// if this is not the First Boot
// i.e. an Bugcheck; we have to setup
// the Attribute and colors of the VGA PART
//
for(i=0; i<GRAPH_MAX; i++) {
WRITE_REGISTER_UCHAR(VGA_GRAPH_IDX , i);
WRITE_REGISTER_UCHAR(VGA_GRAPH_DATA, default_graph_regs[i]);
}
for(i=0; i<MAX_PALETTE; i++) { // PALETTE (ATC)
WRITE_REGISTER_UCHAR(VGA_ATC_IDX , i);
WRITE_REGISTER_UCHAR(VGA_ATC_DATA, default_pal_regs[i]);
}
}
WRITE_REGISTER_UCHAR(VGA_DAC_MASK , 0xff);
//
// set the 16 base colors for text mode in the DAC
//
WRITE_REGISTER_UCHAR(VGA_DAC_WRITE_INDEX, 0x00);
for(i=0; i<48; i++) {
WRITE_REGISTER_UCHAR(VGA_DAC_DATA, base_colors[i]);
}
WRITE_REGISTER_UCHAR(VGA_ATC_IDX, 0x20);
WRITE_REGISTER_UCHAR(VGA_SEQ_IDX, 0x01); // Screen on
byte = READ_REGISTER_UCHAR(VGA_SEQ_DATA);
WRITE_REGISTER_UCHAR(VGA_SEQ_DATA, (byte & 0xdf)); // in the sequencer
}
VOID
HalpResetP9000(
VOID
)
/*++
Routine Description:
This routine initializes the VGA part of an Orchid P9000VLB or Diamond Viper card
Arguments:
None.
Return Value:
None.
--*/
{
LONG IcdVal;
//
// unlock and disable the P9000 on the board
//
WRITE_REGISTER_UCHAR (VGA_SEQ_IDX, 0x11);
WRITE_REGISTER_UCHAR (VGA_SEQ_DATA,0x00); // unlock extended SEQ reg
WRITE_REGISTER_UCHAR (VGA_SEQ_DATA,0x00);
WRITE_REGISTER_UCHAR (VGA_SEQ_DATA,0x00);
WRITE_REGISTER_UCHAR (VGA_SEQ_IDX, 0x12); // select extended reg 0x12
if (HalpVideoBoard == P9000_ORCHID) {
WRITE_REGISTER_UCHAR (VGA_SEQ_DATA, 0x08);
} else {
WRITE_REGISTER_UCHAR (VGA_SEQ_DATA, 0x88);
}
//
// init the clock generator, we use use the 80x50 Text mode
// so we need a 25.175Mhz clock
//
if(( IcdVal = ICD2061CalcClockgen(25175)) == -1){
DebugPrint(("HAL: Error calculating ICD Value for 25.175Mhz\n"));
}
ICD2061LoadClockgen((PUCHAR) VGA_MISC_WRITE , IcdVal, 2);
//
// if this is the first initialisation i.e. Systemboot,
// the firmware has initialized the VGA part properly
//
if (HalpFirstBoot) return;
//
// reset the RamDac (Bt485) to VGA mode, no clock doubler
//
WRITE_REGISTER_UCHAR( Bt485_CR0, 0xa0); // 6 bit operations, no sync on colors
WRITE_REGISTER_UCHAR( Bt485_CR1, 0x00); //
// WRITE_REGISTER_UCHAR( Bt485_CR1, 0x40); //
WRITE_REGISTER_UCHAR( Bt485_CR2, 0x00); // select VGA port
// enable CR3 via CR0
WRITE_REGISTER_UCHAR( Bt485_ADDR, 0x01);
WRITE_REGISTER_UCHAR( Bt485_CR3, 0x00); // disable clock multiplier
WRITE_REGISTER_UCHAR( Bt485_MASK, 0xff);
}
VOID
HalpResetS3Chip(
VOID
)
/*+++
This function resets/loads default values to the S3 Chip
extended registers
this code is borrowed/derived from the s3 miniport driver
---*/
{
UCHAR byte;
WRITE_REGISTER_USHORT(VGA_CRT_IDX, 0x4838); // unlock the S3 regs
WRITE_REGISTER_USHORT(VGA_CRT_IDX, 0xa539); // Unlock the SC regs
WRITE_REGISTER_UCHAR(VGA_SEQ_IDX, 0x01); // Screen off
byte = READ_REGISTER_UCHAR(VGA_SEQ_DATA);
WRITE_REGISTER_UCHAR(VGA_SEQ_DATA, (byte | 0x20)); // stop the sequencer
WRITE_REGISTER_USHORT(VGA_CRT_IDX, 0x0140); // Enable the enhanced 8514 registers
WRITE_REGISTER_USHORT(S3_ADVFUNC_CNTL, 0x02); // reset to normal VGA operation
WRITE_REGISTER_USHORT(VGA_CRT_IDX, 0x0032); // Backward Compat 3
WRITE_REGISTER_USHORT(VGA_CRT_IDX, 0x0035); // CRTC Lock
WRITE_REGISTER_UCHAR(VGA_SEQ_IDX, 0x00); // async reset
WRITE_REGISTER_UCHAR(VGA_SEQ_DATA, 0x01); //
WRITE_REGISTER_UCHAR(VGA_FEAT_CNTRL, 0x00); // normal sync
WRITE_REGISTER_UCHAR(VGA_MISC_READ, 0x00); //
WRITE_REGISTER_USHORT(VGA_CRT_IDX, 0x8531);
WRITE_REGISTER_USHORT(VGA_CRT_IDX, 0x2033); // Backward Compat 2
WRITE_REGISTER_USHORT(VGA_CRT_IDX, 0x0034); // Backward Compat 3
WRITE_REGISTER_USHORT(VGA_CRT_IDX, 0x853a); // S3 Misc 1
WRITE_REGISTER_USHORT(VGA_CRT_IDX, 0x5a3b); // Data Transfer Exec Pos
WRITE_REGISTER_USHORT(VGA_CRT_IDX, 0x103c); // Interlace Retrace start
WRITE_REGISTER_UCHAR(VGA_SEQ_IDX, 0x00); // start the sequencer
WRITE_REGISTER_UCHAR(VGA_SEQ_DATA, 0x03); //
WRITE_REGISTER_USHORT(VGA_CRT_IDX, 0xa640); // VLB: 3Wait
WRITE_REGISTER_USHORT(VGA_CRT_IDX, 0x1841);
WRITE_REGISTER_USHORT(VGA_CRT_IDX, 0x0050);
WRITE_REGISTER_USHORT(VGA_CRT_IDX, 0x0051);
WRITE_REGISTER_USHORT(VGA_CRT_IDX, 0xff52);
WRITE_REGISTER_USHORT(VGA_CRT_IDX, 0x0053);
WRITE_REGISTER_USHORT(VGA_CRT_IDX, 0x3854);
WRITE_REGISTER_USHORT(VGA_CRT_IDX, 0x0055);
WRITE_REGISTER_USHORT(VGA_CRT_IDX, 0x0056);
WRITE_REGISTER_USHORT(VGA_CRT_IDX, 0x0057);
WRITE_REGISTER_USHORT(VGA_CRT_IDX, 0x8058); // ISA Latch ? (bit 3)
WRITE_REGISTER_USHORT(VGA_CRT_IDX, 0x005c);
WRITE_REGISTER_USHORT(VGA_CRT_IDX, 0x005d);
WRITE_REGISTER_USHORT(VGA_CRT_IDX, 0x005e);
WRITE_REGISTER_USHORT(VGA_CRT_IDX, 0x0760);
WRITE_REGISTER_USHORT(VGA_CRT_IDX, 0x8061);
WRITE_REGISTER_USHORT(VGA_CRT_IDX, 0xa162);
WRITE_REGISTER_USHORT(VGA_CRT_IDX, 0x0043); // Extended Mode
WRITE_REGISTER_USHORT(VGA_CRT_IDX, 0x0045); // HW graphics Cursor Mode
WRITE_REGISTER_USHORT(VGA_CRT_IDX, 0x0046); // HW graphics Cursor Orig x
WRITE_REGISTER_USHORT(VGA_CRT_IDX, 0xff47); // HW graphics Cursor Orig x
WRITE_REGISTER_USHORT(VGA_CRT_IDX, 0xfc48); // HW graphics Cursor Orig y
WRITE_REGISTER_USHORT(VGA_CRT_IDX, 0xff49); // HW graphics Cursor Orig y
WRITE_REGISTER_USHORT(VGA_CRT_IDX, 0xff4a); // HW graphics Cursor Orig y
WRITE_REGISTER_USHORT(VGA_CRT_IDX, 0xff4b); // HW graphics Cursor Orig y
WRITE_REGISTER_USHORT(VGA_CRT_IDX, 0xff4c); // HW graphics Cursor Orig y
WRITE_REGISTER_USHORT(VGA_CRT_IDX, 0xff4d); // HW graphics Cursor Orig y
WRITE_REGISTER_USHORT(VGA_CRT_IDX, 0xff4e); // Dsp Start x pixel pos
WRITE_REGISTER_USHORT(VGA_CRT_IDX, 0xdf4f); // Dsp Start y pixel pos
WRITE_REGISTER_USHORT(VGA_CRT_IDX, 0x0042); // select default clock
WRITE_REGISTER_UCHAR(VGA_MISC_WRITE, 0x63); // Clock select
/*
// this should be done in the InitializeVGA code ...
WRITE_REGISTER_UCHAR(VGA_SEQ_IDX, 0x01); // Screen on
byte = READ_REGISTER_UCHAR(VGA_SEQ_DATA);
WRITE_REGISTER_UCHAR(VGA_SEQ_DATA, (byte & 0xdf)); // in the sequencer
*/
WRITE_REGISTER_USHORT(VGA_CRT_IDX, 0x0038); // lock s3 regs
WRITE_REGISTER_USHORT(VGA_CRT_IDX, 0x0039); // lock more s3 regs
}
VOID
HalReturnToFirmware(
IN FIRMWARE_REENTRY Routine
)
/*++
Routine Description:
This function returns control to the specified firmware routine.
In most cases it generates a soft reset.
Arguments:
Routine - Supplies a value indicating which firmware routine to invoke.
Return Value:
Does not return.
--*/
{
KIRQL OldIrql;
UCHAR DataByte;
//
// Disable Interrupts.
//
KeRaiseIrql(HIGH_LEVEL, &OldIrql);
//
// Case on the type of return.
//
switch (Routine) {
case HalHaltRoutine:
//
// Hang looping.
//
// power off asked by DCU/IDC (power - fan or ... failure)
if (((ULONG)(((SNI_PRIVATE_VECTOR *)(SYSTEM_BLOCK->VendorVector))->EipRoutine) != (ULONG)-1) &&
(((SNI_PRIVATE_VECTOR *)(SYSTEM_BLOCK->VendorVector))->EipHalInfo == 1))
((SNI_PRIVATE_VECTOR *)(SYSTEM_BLOCK->VendorVector))->EipRoutine(
((SNI_PRIVATE_VECTOR *)(SYSTEM_BLOCK->VendorVector))->EipContext
);
for (;;) {}
case HalPowerDownRoutine:
// power off always done by DCU
if ((ULONG)(((SNI_PRIVATE_VECTOR *)(SYSTEM_BLOCK->VendorVector))->EipRoutine) != (ULONG)-1)
((SNI_PRIVATE_VECTOR *)(SYSTEM_BLOCK->VendorVector))->EipRoutine(
((SNI_PRIVATE_VECTOR *)(SYSTEM_BLOCK->VendorVector))->EipContext
);
//
// PowerOff is done by the SNI machines by writing the Power_Off bit to the machine control register ...
//
if (HalpIsTowerPci){
WRITE_REGISTER_ULONG((PULONG) PCI_TOWER_DCU_CONTROL, DC_POWEROFF);
}else{
WRITE_REGISTER_UCHAR((PUCHAR) PCI_MCR_ADDR, PCI_MCR_POWEROFF);
}
for (;;) {} // hang looping
case HalRestartRoutine:
case HalRebootRoutine:
case HalInteractiveModeRoutine:
// power off asked by DCU/IDC (power - fan or ... failure)
if (((ULONG)(((SNI_PRIVATE_VECTOR *)(SYSTEM_BLOCK->VendorVector))->EipRoutine) != (ULONG)-1) &&
(((SNI_PRIVATE_VECTOR *)(SYSTEM_BLOCK->VendorVector))->EipHalInfo == 1))
((SNI_PRIVATE_VECTOR *)(SYSTEM_BLOCK->VendorVector))->EipRoutine(
((SNI_PRIVATE_VECTOR *)(SYSTEM_BLOCK->VendorVector))->EipContext
);
if (HalpIsMulti) {
ULONG Mask,i;
for (i=0;i<HalpIsMulti;i++)
if (((SNI_PRIVATE_VECTOR *)(SYSTEM_BLOCK->VendorVector))->ActiveProcessor[PCR->Number])
Mask |= 1<<i;
Mask = Mask & ~(PCR->SetMember);
#if DBGG
DbgPrint("Send message RESTART to maskcpu = %x \n",Mask);
#endif
HalpRequestIpi(Mask,MPA_RESTART_MESSAGE);
//
// if this is not the Boot CPU, we call a special Firmware entry to stop it
//
//
// remove this processor from the list of active processors
//
((SNI_PRIVATE_VECTOR *)(SYSTEM_BLOCK->VendorVector))->ActiveProcessor[PCR->Number]=0;
if (PCR->Number ) {
#if DBGG
DbgPrint(" Reinit slave %x \n", ((SNI_PRIVATE_VECTOR *)(SYSTEM_BLOCK->VendorVector))->reinit_slave);
#endif
((SNI_PRIVATE_VECTOR *)(SYSTEM_BLOCK->VendorVector))->reinit_slave();
} else HalpBootCpuRestart();
}
HalpColumn = 0;HalpRow = 0; // if we already were in VGA mode
HalDisplayString("\n");
HalpClearVGADisplay();
HalDisplayString("\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n");
HalDisplayString(" ���������������������������������������ͻ\n");
HalDisplayString(" � �\n");
HalDisplayString(" � Restart in Progress �\n");
HalDisplayString(" � �\n");
HalDisplayString(" ���������������������������������������ͼ\n");
DataByte = READ_REGISTER_UCHAR(
&((PEISA_CONTROL) HalpOnboardControlBase)->ExtendedNmiResetControl);
((PNMI_EXTENDED_CONTROL) &DataByte)->BusReset = 1;
WRITE_REGISTER_UCHAR(
&((PEISA_CONTROL) HalpOnboardControlBase)->ExtendedNmiResetControl,
DataByte
);
KeStallExecutionProcessor(10000);
((PNMI_EXTENDED_CONTROL) &DataByte)->BusReset = 0;
WRITE_REGISTER_UCHAR(
&((PEISA_CONTROL) HalpOnboardControlBase)->ExtendedNmiResetControl,
DataByte
);
ArcReboot();
for (;;) ;
default:
DbgPrint("HalReturnToFirmware invalid argument\n");
KeLowerIrql(OldIrql);
DbgBreakPoint();
}
}
VOID
HalpBootCpuRestart(
VOID
)
/*++
Routine Description:
This function returns control to the firmware Arcreboot routine.
it waits until all other cpu's have beet shut down.
this code is executed only on the boot cpu
Arguments:
None
Return Value:
Does not return.
--*/
{
UCHAR DataByte;
ULONG cpt;
HalpColumn = 0;HalpRow = 0; // if we already were in VGA mode
HalDisplayString("\n");
HalpClearVGADisplay();
HalDisplayString("\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n");
HalDisplayString(" ���������������������������������������ͻ\n");
HalDisplayString(" � �\n");
HalDisplayString(" � Restart in Progress �\n");
HalDisplayString(" � �\n");
HalDisplayString(" ���������������������������������������ͼ\n");
cpt = 0;
while(*(PULONG)(& (((SNI_PRIVATE_VECTOR *)(SYSTEM_BLOCK->VendorVector))->ActiveProcessor[0]) )) {
KeStallExecutionProcessor(500000);
++cpt;if (cpt == 20) break;
}
//
// if there are still ssome processors active, we do a reset of the entire machine
//
if (*(PULONG)(& (((SNI_PRIVATE_VECTOR *)(SYSTEM_BLOCK->VendorVector))->ActiveProcessor[0]) )) {
#if DBG
DbgPrint(" Some processors did not answer . Reset machine started. \n");
#endif
if (HalpIsTowerPci) {
WRITE_REGISTER_ULONG((PULONG) PCI_TOWER_DCU_CONTROL, DC_SWRESET);
}else {
WRITE_REGISTER_UCHAR((PUCHAR) PCI_MCR_ADDR, PCI_MCR_SOFTRESET);
}
} else {
#if DBG
DbgPrint("Reboot started \n");
#endif
}
DataByte = READ_REGISTER_UCHAR(
&((PEISA_CONTROL) HalpOnboardControlBase)->ExtendedNmiResetControl);
((PNMI_EXTENDED_CONTROL) &DataByte)->BusReset = 1;
WRITE_REGISTER_UCHAR(
&((PEISA_CONTROL) HalpOnboardControlBase)->ExtendedNmiResetControl,
DataByte
);
KeStallExecutionProcessor(10000);
((PNMI_EXTENDED_CONTROL) &DataByte)->BusReset = 0;
WRITE_REGISTER_UCHAR(
&((PEISA_CONTROL) HalpOnboardControlBase)->ExtendedNmiResetControl,
DataByte
);
ArcReboot();
for (;;) ;
}
VOID
KdpWriteIoSpace (
IN PDBGKD_MANIPULATE_STATE64 m,
IN PSTRING AdditionalData,
IN PCONTEXT Context
)
/*++
Routine Description:
This function is called in response of a write io space state
manipulation message. Its function is to write to system io
locations.
Arguments:
m - Supplies the state manipulation message.
AdditionalData - Supplies any additional data for the message.
Context - Supplies the current context.
Return Value:
None.
--*/
{
PDBGKD_READ_WRITE_IO64 a = &m->u.ReadWriteIo;
STRING MessageHeader;
PUCHAR b;
PUSHORT s;
PULONG l;
HARDWARE_PTE Opaque;
MessageHeader.Length = sizeof(*m);
MessageHeader.Buffer = (PCHAR)m;
ASSERT(AdditionalData->Length == 0);
m->ReturnStatus = STATUS_SUCCESS;
//
// Check Size and Alignment
//
switch ( a->DataSize ) {
case 1:
b = (PUCHAR)MmDbgWriteCheck((PVOID)a->IoAddress, &Opaque);
if ( b ) {
WRITE_REGISTER_UCHAR(b,(UCHAR)a->DataValue);
MmDbgReleaseAddress(b, &Opaque);
} else {
m->ReturnStatus = STATUS_ACCESS_VIOLATION;
}
break;
case 2:
if ((ULONG_PTR)a->IoAddress & 1 ) {
m->ReturnStatus = STATUS_DATATYPE_MISALIGNMENT;
} else {
s = (PUSHORT)MmDbgWriteCheck((PVOID)a->IoAddress, &Opaque);
if ( s ) {
WRITE_REGISTER_USHORT(s,(USHORT)a->DataValue);
MmDbgReleaseAddress(s, &Opaque);
} else {
m->ReturnStatus = STATUS_ACCESS_VIOLATION;
}
}
break;
case 4:
if ((ULONG_PTR)a->IoAddress & 3 ) {
m->ReturnStatus = STATUS_DATATYPE_MISALIGNMENT;
} else {
l = (PULONG)MmDbgWriteCheck((PVOID)a->IoAddress, &Opaque);
if ( l ) {
WRITE_REGISTER_ULONG(l,a->DataValue);
MmDbgReleaseAddress(l, &Opaque);
} else {
m->ReturnStatus = STATUS_ACCESS_VIOLATION;
}
}
break;
default:
m->ReturnStatus = STATUS_INVALID_PARAMETER;
}
KdpSendPacket(
PACKET_TYPE_KD_STATE_MANIPULATE,
&MessageHeader,
NULL
);
}
VOID
HalpWriteClockRegister (
UCHAR Register,
UCHAR Value
)
/*++
Routine Description:
This routine writes the specified value to the specified realtime
clock register.
Arguments:
Register - Supplies the number of the register whose value is written.
Value - Supplies the value that is written to the specified register.
Return Value:
The value of the register is returned as the function value.
--*/
{
/* start M0001 */
#if defined(_R94A_)
//
// Insert the realtime clock register number, and write the value back
// to RTC Index register. This selects the realtime clock
// register that is written.
//
WRITE_REGISTER_UCHAR(&((PRTC_REGISTERS) HalpRealTimeClockBase)->Index,
Register);
#else // _R94A_
//
// Insert the realtime clock register number, and write the value back
// to the EISA NMI enable register. This selects the realtime clock
// register that is written. Note this is a write only register and
// the EISA NMI is always enabled.
//
Register |= 0x80;
WRITE_REGISTER_UCHAR(&((PEISA_CONTROL) HalpEisaControlBase)->NmiEnable,
Register);
#endif // _R94A_
/* end M0001 */
//
// Write the realtime clock register value.
//
/* start M0002 */
#if defined(_R94A_) // M0004
WRITE_REGISTER_UCHAR( &((PRTC_REGISTERS) HalpRealTimeClockBase)->Data, Value);
#else // _R94A_
WRITE_REGISTER_UCHAR((PUCHAR)HalpRealTimeClockBase, Value);
#endif // _R94A_
/* end M0002 */
return;
}
UCHAR
HalpReadClockRegister (
UCHAR Register
)
/*++
Routine Description:
This routine reads the specified realtime clock register.
Arguments:
Register - Supplies the number of the register whose value is read.
Return Value:
The value of the register is returned as the function value.
--*/
{
/* start M0001 */
#if defined(_R94A_) /* M0003 */
// Insert the realtime clock register number, and write the value back
// to RTC Index register. This selects the realtime clock register
// that is read.
//
WRITE_REGISTER_UCHAR(&((PRTC_REGISTERS) HalpRealTimeClockBase)->Index,
Register);
#else // _R94A_
//
// Insert the realtime clock register number, and write the value back
// to the EISA NMI enable register. This selects the realtime clock register
// that is read. Note this is a write only register and the EISA NMI
// is always enabled.
//
//
// TEMPTEMP Disable NMI's for now because this is causing machines in the
// build lab to get NMI's during boot.
//
Register |= 0x80;
WRITE_REGISTER_UCHAR(&((PEISA_CONTROL) HalpEisaControlBase)->NmiEnable,
Register);
#endif // _R94A_
/* end M0001 */
//
// Read the realtime clock register value.
//
/* start M0002 */
#if defined(_R94A_) // M0004
return READ_REGISTER_UCHAR( &((PRTC_REGISTERS) HalpRealTimeClockBase)->Data);
#else // _R94A_
return READ_REGISTER_UCHAR((PUCHAR)HalpRealTimeClockBase);
#endif // _R94A_
/* end M0002 */
}
