static void LatchPower(void) { latche=latcheinit; WSync(); SetReadHandler(0x8000,0xFFFF,defread); SetWriteHandler(addrreg0,addrreg1,LatchWrite); }
static void LatchPower(void) { latche = latcheinit; WSync(); if (WRAM) { SetReadHandler(0x6000, 0xFFFF, CartBR); SetWriteHandler(0x6000, 0x7FFF, CartBW); FCEU_CheatAddRAM(WRAMSIZE >> 10, 0x6000, WRAM); } else {
static DECLFW(LatchWrite) { // FCEU_printf("bs %04x %02x\n",A,V); if (bus_conflict) latche = (V == CartBR(A)) ? V : 0; else latche = V; WSync(); }
static void LH10Power(void) { reg[0] = reg[1] = reg[2] = reg[3] = reg[4] = reg[5] = reg[6] = reg[7] = 0; WSync(); SetReadHandler(0x6000, 0xFFFF, CartBR); SetWriteHandler(0x8000, 0xBFFF, UNLKS7037Write); SetWriteHandler(0xC000, 0xDFFF, CartBW); SetWriteHandler(0xE000, 0xFFFF, UNLKS7037Write); }
static DECLFW(UNLKS7037Write) { switch(A & 0xE001) { case 0x8000: cmd = V & 7; break; case 0x8001: reg[cmd] = V; WSync(); break; } }
static void LatchPower(void) { latche = latcheinit; WSync(); if (WRAM) { SetReadHandler(0x6000, 0xFFFF, CartBR); SetWriteHandler(0x6000, 0x7FFF, CartBW); } else SetReadHandler(0x6000, 0xFFFF, defread); SetWriteHandler(addrreg0, addrreg1, LatchWrite); }
static void StateRestore(int version) { WSync(); }
static void LatchReset(void) { latche = latcheinit; WSync(); }
static DECLFW(LatchWrite) { latche = A; WSync(); }
static DECLFW(LatchWrite) { FCEU_printf("%04x:%02x\n",A,V); latche=A; WSync(); }