/*
procedure CallPatch(Location, CallTo: DWORD); stdcall;
var
lgCall: array[0..4] of Byte;
begin
lgCall[0] := $E8;
WriteLn('Creating Call Patch at: 0x' + IntToHex(Location,8) + ' to: 0x' +
IntToHex(CallTo,8) + ' [ 0x' + IntToHex((CallTo - Location) - 5,8)
+ ']');
PDWORD(@lgCall[1])^ := (CallTo - Location) - 5;
WriteMem(Location, DWORD(@lgCall), 5);
end;
*/
void Patcher::CallPatch(DWORD Location, DWORD CallTo) {
unsigned char* lgCall = (unsigned char*)malloc(5);
lgCall[0] = 0xE8;
*((PDWORD)&lgCall[1]) = (CallTo - Location) - 5;
WriteMem(Location, (DWORD)lgCall, 5);
free(lgCall);
}
/*
* doStartTask:
*
* handle NFY_STARTTASK notification
*
* If we are waiting for the debuggee to load, then this is the task.
* We remember the module and task ID's, and plant a breakpoint at the
* starting address of the application. We can do that now, since we
* now know the code selector for the segment with the start address.
*
* Otherwise, we simply record it so that we can notify the debugger
* about a loaded module later.
*/
static BOOL doStartTask( DWORD data )
{
char val;
TASKENTRY te;
te.dwSize = sizeof( te );
TaskFindHandle( &te, TaskAtNotify );
if( DebuggerState == LOADING_DEBUGEE ) {
DebugeeModule = te.hModule;
DebugeeTask = TaskAtNotify;
StopNewTask.loc.segment = HIWORD( data );
ReadMem( StopNewTask.loc.segment, StopNewTask.loc.offset,
&StopNewTask.value, 1 );
val = '\xcc';
WriteMem( StopNewTask.loc.segment, StopNewTask.loc.offset,
&val, 1 );
ReadMem( StopNewTask.loc.segment, StopNewTask.loc.offset,
&val, 1 );
Out((OUT_RUN," wrote breakpoint at %04x:%04lx, oldbyte=%02x(is now %02x)",
StopNewTask.loc.segment, StopNewTask.loc.offset,
StopNewTask.value, val ));
Out((OUT_RUN," StartTask: cs:ip = %Fp", data ));
ToDebugger( TASK_LOADED );
} else {
AddModuleLoaded( te.hModule, FALSE );
}
return( FALSE );
} /* doStartTask */
bool AviListAvi::writeMainHeaderStruct(const MainAVIHeader &hdr)
{
ADMMemioAvi mem(sizeof(hdr));
mem.writeMainHeaderStruct(hdr);
WriteMem(mem);
return true;
}
/**
* SoftwareDisableImc - Software disable IMC strap
*
*
* @param[in] FchDataPtr Fch configuration structure pointer.
*
*/
VOID
SoftwareDisableImc (
IN VOID *FchDataPtr
)
{
UINT8 ValueByte;
UINT8 PortStatusByte;
UINT32 AbValue;
UINT32 ABStrapOverrideReg;
AMD_CONFIG_PARAMS *StdHeader;
StdHeader = ((FCH_DATA_BLOCK *) FchDataPtr)->StdHeader;
GetChipSysMode (&PortStatusByte, StdHeader);
RwPci ((LPC_BUS_DEV_FUN << 16) + FCH_LPC_REGC8 + 3, AccessWidth8, 0x7F, BIT7, StdHeader);
ReadPmio (FCH_PMIOA_REGBF, AccessWidth8, &ValueByte, StdHeader);
ReadMem ((ACPI_MMIO_BASE + MISC_BASE + FCH_MISC_REG80), AccessWidth32, &AbValue);
ABStrapOverrideReg = AbValue;
ABStrapOverrideReg &= ~BIT2; // bit2=0 EcEnableStrap
WriteMem ((ACPI_MMIO_BASE + MISC_BASE + FCH_MISC_REG84), AccessWidth32, &ABStrapOverrideReg);
ReadPmio (FCH_PMIOA_REGD7, AccessWidth8, &ValueByte, StdHeader);
ValueByte |= BIT1; // Set GenImcClkEn to 1
WritePmio (FCH_PMIOA_REGD7, AccessWidth8, &ValueByte, StdHeader);
ValueByte = 06;
LibAmdIoWrite (AccessWidth8, 0xcf9, &ValueByte, StdHeader);
FchStall (0xffffffff, StdHeader);
}
/*
procedure JmpPatch(Location, JumpTo: DWORD); stdcall;
var
lgJmp: array[0..4] of Byte;
begin
lgJmp[0] := $E9;
WriteLn('Creating Jump Patch at: 0x' + IntToHex(Location,8) + ' to: 0x' +
IntToHex(JumpTo,8) + ' [ 0x' + IntToHex((JumpTo - Location) - 5,8)
+ ']');
PDWORD(@lgJmp[1])^ := (JumpTo - Location) - 5;
WriteMem(Location, DWORD(@lgJmp), 5);
end;
*/
void Patcher::JmpPatch(DWORD Location, DWORD JumpTo) {
unsigned char* lgJmp = (unsigned char*)malloc(5);
lgJmp[0] = 0xE9;
*((PDWORD)&lgJmp[1]) = (JumpTo - Location) - 5;
WriteMem(Location, (DWORD)lgJmp, 5);
free(lgJmp);
}
int StartPatch(void)
{
BYTE *p;
HMODULE h_dll;
char buf[10];
DWORD new_addr;
for(int i=0;i<PATCH_NUM;i++)
{
h_dll = LoadLibrary(patch_list[i*2]);
if (h_dll==NULL)
{
printf("Error! Can not LoadLibrary(%s)\n", patch_list[i*2]);
return 1;
}
MyProc = (def_MyProc)GetProcAddress(h_dll, patch_list[i*2+1]);
if (MyProc==NULL)
{
printf("Error! Can not GetProcAddress(%s)\n", patch_list[i*2+1]);
return 1;
}
p = (BYTE*)MyProc;
if (i==1)
{
memcpy(buf, p, 5);
buf[5]=0xe9;
new_addr = (DWORD)p;
new_addr -= (DWORD)old_I_CryptGetDefaultCryptProv;
new_addr -= 5;
memcpy(buf+6, &new_addr, 4);
WriteMem((DWORD)old_I_CryptGetDefaultCryptProv, buf, 10);
buf[0]=0xe9;
new_addr = (DWORD)my_I_CryptGetDefaultCryptProv;
new_addr -= (DWORD)MyProc;
new_addr -= 5;
memcpy(buf+1, &new_addr, 4);
WriteMem((DWORD)MyProc, buf, 5);
}
else
{
WriteMem((int)p, "\xb8\x01\x00\x00\x00\xC2\x04\x00", 8); //mov ax,1 - ret 4
}
}
return 0;
}
void CallPatch(void* dest, void* patch)
{
u8 temp[5];
temp[0] = 0xE8;
*(int*)&temp[1] = (int)patch - (int)dest - 5;
WriteMem(dest, temp, 5);
return;
}
void ResetCommArea( void )
{
if( CommonAddr.segment != 0 ) { /* reset common variables */
Comm.pop_no = 0;
Comm.push_no = 0;
WriteMem( Pid, &Comm.pop_no, CommonAddr.offset + 11, 2 * sizeof( short ) );
}
}
/**
* GcpuRelatedSetting - Program Gcpu C related function
*
*
*
* @param[in] FchDataPtr Fch configuration structure pointer.
*
*/
VOID
GcpuRelatedSetting (
IN VOID *FchDataPtr
)
{
UINT8 FchAcDcMsg;
UINT8 FchTimerTickTrack;
UINT8 FchClockInterruptTag;
UINT8 FchOhciTrafficHanding;
UINT8 FchEhciTrafficHanding;
UINT8 FchGcpuMsgCMultiCore;
UINT8 FchGcpuMsgCStage;
UINT32 Value;
FCH_DATA_BLOCK *LocalCfgPtr;
LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr;
FchAcDcMsg = (UINT8) LocalCfgPtr->Gcpu.AcDcMsg;
FchTimerTickTrack = (UINT8) LocalCfgPtr->Gcpu.TimerTickTrack;
FchClockInterruptTag = (UINT8) LocalCfgPtr->Gcpu.ClockInterruptTag;
FchOhciTrafficHanding = (UINT8) LocalCfgPtr->Gcpu.OhciTrafficHanding;
FchEhciTrafficHanding = (UINT8) LocalCfgPtr->Gcpu.EhciTrafficHanding;
FchGcpuMsgCMultiCore = (UINT8) LocalCfgPtr->Gcpu.GcpuMsgCMultiCore;
FchGcpuMsgCStage = (UINT8) LocalCfgPtr->Gcpu.GcpuMsgCStage;
ReadMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGA0, AccessWidth32, &Value);
Value = Value & 0xC07F00A0;
if ( FchAcDcMsg ) {
Value = Value | BIT0;
}
if ( FchTimerTickTrack ) {
Value = Value | BIT1;
}
if ( FchClockInterruptTag ) {
Value = Value | BIT10;
}
if ( FchOhciTrafficHanding ) {
Value = Value | BIT13;
}
if ( FchEhciTrafficHanding ) {
Value = Value | BIT15;
}
if ( FchGcpuMsgCMultiCore ) {
Value = Value | BIT23;
}
if ( FchGcpuMsgCMultiCore ) {
Value = (Value | (BIT6 + BIT4 + BIT3 + BIT2));
}
WriteMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGA0, AccessWidth32, &Value);
}
/*
procedure Unpatch;
var
I, J: Integer;
begin
for I := 0 to Length(PatchedArr) - 1 do
begin
with PatchedArr[I] do
begin
for J := 0 to Length(OrigMemory) - 1 do
begin
WriteMem(Addr+Cardinal(J),Cardinal(@OrigMemory[J]),1);
end;
end;
end;
for I := 0 to Length(PatchedMemArr) - 1 do
begin
with PatchedMemArr[I] do
begin
for J := 0 to Length(OrigMemory) - 1 do
begin
WriteMem(Addr+Cardinal(J),Cardinal(@OrigMemory[J]),1);
end;
end;
end;
Patched := False;
end;
*/
void Patcher::Unpatch()
{
for(int i = 0; i < patchArrPos; i++) {
WriteMem(patchedArr[i]->addr, (DWORD)patchedArr[i]->origMemory, 5 + patchedArr[i]->numNops);
//for(int j = 0; j < patchedArr[i]->numNops+5; j++) {
// WriteMem(patchedArr[i]->addr+j, (DWORD)patchedArr[i]->origMemory[j], 1);
//}
}
for(int i = 0; i < patchMemPos; i++) {
WriteMem(patchedMemArr[i]->addr, (DWORD)patchedMemArr[i]->origMemory, patchedMemArr[i]->memLength);
//for(int j = 0; j < patchedMemArr[i]->memLength; j++) {
// WriteMem(patchedMemArr[i]->addr+j, (DWORD)patchedMemArr[i]->origMemory[j], 1);
//}
}
patched = false;
}
void CPersSub::PersSub()
{
if (PR_htValid) {
switch (PR_htInst) {
case SUB_ENTRY: {
if (SendCallBusy_mult()) {
HtRetry();
break;
}
// Generate a seperate thread for each multiply operation within a matrix element
if (P_calcIdx < SR_comRC) {
SendCallFork_mult(SUB_JOIN, P_rowIdx, P_eleIdx, P_calcIdx);
HtContinue(SUB_ENTRY);
P_calcIdx += 1;
} else {
RecvReturnPause_mult(SUB_STORE);
}
break;
}
case SUB_JOIN: {
// Add resulting products into a sum variable
// The resulting element will be the sum of all multiply operations
P_eleSum += P_result;
RecvReturnJoin_mult();
break;
}
case SUB_STORE: {
if (WriteMemBusy()) {
HtRetry();
break;
}
// Memory write request - element
MemAddr_t memWrAddr = (ht_uint48)(SR_mcBase + ((P_rowIdx*SR_mcCol) << 3) + (P_eleIdx << 3));
WriteMem(memWrAddr, P_eleSum);
WriteMemPause(SUB_RTN);
break;
}
case SUB_RTN: {
if (SendReturnBusy_sub()) {
HtRetry();
break;
}
// Finished calculating matrix element
SendReturn_sub();
break;
}
default:
assert(0);
}
}
}
FARPROC PatchImportOld(char* sourceModule, char* importModule, LPCSTR name, void* patchFunction)
{
if ( !name )
return NULL;
HMODULE tempModule = GetModuleHandleA(sourceModule);
if ( !tempModule )
return NULL;
IMAGE_THUNK_DATA32* importOrigin = _GetImportsList(sourceModule, importModule);
if ( !importOrigin )
return NULL;
DWORD* importFunction = _GetFunctionsList(sourceModule, importModule);
if ( !importFunction )
return NULL;
for (u32 i = 0; importOrigin[i].u1.Ordinal != 0; i++)
{
if ((DWORD)name < 0xFFFF)
{
if (IMAGE_SNAP_BY_ORDINAL32(importOrigin[i].u1.Ordinal) && IMAGE_ORDINAL32(importOrigin[i].u1.Ordinal) == IMAGE_ORDINAL32((DWORD)name))
{
FARPROC oldFxn = (FARPROC)importFunction[i];
WriteMem(&importFunction[i], &patchFunction, 4);
return oldFxn;
}
}
else
{
#pragma warning(suppress: 6387)
if (_strcmpi(name, (const char*)((PIMAGE_IMPORT_BY_NAME)((u32)importOrigin[i].u1.AddressOfData + (u32)tempModule))->Name) == 0)
{
FARPROC oldFxn = (FARPROC)importFunction[i];
WriteMem(&importFunction[i], &patchFunction, 4);
return oldFxn;
}
}
}
return NULL;
}
/*
procedure Patch;
const
Nop: Byte = $90;
var
I,J: Integer;
begin
for I := 0 to Length(PatchedArr) - 1 do
begin
with PatchedArr[I] do
begin
JmpPatch(Addr,Cardinal(@NewMemory[0]));
if Length(OrigMemory) > 5 then
begin
for J := 5 to Length(OrigMemory) - 1 do
WriteMem(Addr+Cardinal(J),Cardinal(@Nop),1);
end;
end;
end;
for I := 0 to Length(PatchedMemArr) - 1 do
begin
with PatchedMemArr[I] do
begin
for J := 0 to Length(NewMemory) - 1 do
begin
WriteMem(Addr+Cardinal(J),Cardinal(@NewMemory[J]),1);
end;
end;
end;
Patched := True;
end;
*/
void Patcher::Patch()
{
const unsigned char Nop = 0x90;
for(int i = 0; i < patchArrPos; i++) {
JmpPatch(patchedArr[i]->addr,(DWORD)patchedArr[i]->newMemory);
for(int j = 0; j < patchedArr[i]->numNops; j++) {
WriteMem(patchedArr[i]->addr+j+5,(DWORD)&Nop,1);
}
}
for(int i = 0; i < patchMemPos; i++) {
WriteMem(patchedMemArr[i]->addr, (DWORD)&patchedMemArr[i]->newMemory[0], patchedMemArr[i]->memLength);
//for(int j = 0; j < patchedMemArr[i]->memLength; j++) {
// WriteMem(patchedMemArr[i]->addr + j, (DWORD)&patchedMemArr[i]->newMemory[j],1);
//}
}
patched = true;
}
/**
* RwMem - Read & Write FCH BAR Memory
*
* @param[in] Address - Memory BAR address
* @param[in] OpFlag - Access width
* @param[in] Mask - Mask Value of data
* @param[in] Data - Write data
*
*/
VOID
RwMem (
IN UINT32 Address,
IN UINT8 OpFlag,
IN UINT32 Mask,
IN UINT32 Data
)
{
UINT32 Result;
ReadMem (Address, OpFlag, &Result);
Result = (Result & Mask) | Data;
WriteMem (Address, OpFlag, &Result);
}
unsigned ReqWrite_mem( void )
{
write_mem_req *acc;
write_mem_ret *ret;
unsigned len;
acc = GetInPtr( 0 );
CONV_LE_32( acc->mem_addr.offset );
CONV_LE_16( acc->mem_addr.segment );
ret = GetOutPtr( 0 );
len = GetTotalSize() - sizeof( *acc );
ret->len = WriteMem( pid, GetInPtr( sizeof( *acc ) ), acc->mem_addr.offset, len );
CONV_LE_16( ret->len );
return( sizeof( *ret ) );
}
/*
* FlagWin32AppAsDebugged - check if a given module handle is a Win32 application
*/
void FlagWin32AppAsDebugged( HMODULE hmod )
{
GLOBALENTRY ge;
winext_data wedata;
ge.dwSize = sizeof( GLOBALENTRY );
if( !GlobalEntryModule( &ge, hmod, 1 ) ) {
return;
}
ReadMem( (WORD)ge.hBlock, 0, (LPVOID)&wedata, sizeof( wedata ) );
if( !memcmp( wedata.sig, win386Sig, sizeof( win386Sig ) ) ) {
WriteMem( (WORD)ge.hBlock, 0, win386Sig2, 4 );
}
} /* FlagWin32AppAsDebugged */
unsigned ReqWrite_mem( void )
{
DWORD len;
LPVOID data;
write_mem_req *acc;
write_mem_ret *ret;
acc = GetInPtr(0);
data = GetInPtr( sizeof( *acc ) );
ret = GetOutPtr(0);
len = GetTotalSize() - sizeof( *acc );
ret->len = WriteMem( acc->mem_addr.segment, acc->mem_addr.offset, data, len );
return( sizeof( *ret ) );
}
bool VIRTUALMACHINE::push(VMFLOAT val)
{
bool result= false;
VMREGTYPE sp= 0;
if(GetRegister(SP,sp))
{
sp-= sizeof(VMREGTYPE);
if(SetRegister(SP,sp))
{
SetFlags(val);
result= WriteMem((VPVOID)sp,&val,sizeof(val));
}
}
return result;
}
void
CPersRelu::PersRelu()
{
if (PR_htValid) {
switch (PR_htInst) {
case RELU_LD1: {
BUSY_RETRY(ReadMemBusy());
// Memory read request
//printf("calculate address idx: %u", P_vecIdx);
fflush(stdout);
MemAddr_t memRdAddr = SR_op1Addr + (P_vecIdx << 3);
//printf("About to read ");
ReadMem_op1(memRdAddr);
ReadMemPause(RELU_ST);
}
break;
case RELU_ST: {
BUSY_RETRY(WriteMemBusy());
uint64_t basemask = 0x000000000000FFFF;
P_result = 0;
for(int i = 0; i < 64; i+=16){
if((int16_t)(PR_op1 >> i) > 0){
P_result = P_result | (PR_op1 & (basemask << i));
}else{
//Rectify the i'th element to 0
//P_result = 0;
}
}
//printf("ST op1: %ld => %ld\n",PR_op1, P_result);
// Memory write request
MemAddr_t memWrAddr = SR_resAddr + (P_vecIdx << 3);
WriteMem(memWrAddr, P_result);
WriteMemPause(RELU_RTN);
}
break;
case RELU_RTN: {
BUSY_RETRY(SendReturnBusy_relu());
SendReturn_relu();
}
break;
default:
assert(0);
}
}
unsigned ReqClear_break( void )
{
clear_break_req *acc;
bp_t opcode;
acc = GetInPtr( 0 );
CONV_LE_32( acc->break_addr.offset );
CONV_LE_16( acc->break_addr.segment );
opcode = acc->old;
WriteMem( pid, &opcode, acc->break_addr.offset, sizeof( opcode ) );
Out( "ReqClear_break at " );
OutNum( acc->break_addr.offset );
Out( " (setting to " );
OutNum( opcode );
Out( ")\n" );
return( 0 );
}
/*
* doStartDLL:
*
* handle a NFY_STARTDLL notification
*
* Record the module to notify the debugger of it later.
*/
static BOOL doStartDLL( DWORD data )
{
NFYSTARTDLL *sd;
char val;
sd = (NFYSTARTDLL *) data;
AddModuleLoaded( sd->hModule, TRUE );
if( DebuggerState == RUNNING_DEBUGEE ) {
ReadMem( sd->wCS, sd->wIP, &DLLLoadSaveByte, 1 );
DLLLoadCS = sd->wCS;
DLLLoadIP = sd->wIP;
val = '\xcc';
WriteMem( sd->wCS, sd->wIP, &val, 1 );
}
Out((OUT_ERR,"DLL Loaded '%4.4x:%4.4x'",sd->wCS,sd->wIP));
return( FALSE );
} /* doStartDLL */
EFI_STATUS
EFIAPI
AmdSmiEinjChkErr (
IN OUT VOID
)
{
UINT8 Value8;
UINT8 PortId;
UINT32 Value32;
EFI_STATUS Status;
AMD_CONFIG_PARAMS StdHeader;
Status = EFI_SUCCESS;
PortId = 7;
ReadMem (ACPI_MMIO_BASE + SMI_BASE + 0x3C, AccessWidth8, &Value8);
if (Value8 & BIT2) {
Value32 = ReadAlink (0x104C | (UINT32) (ABCFG << 29), &StdHeader);
if (Value32 & BIT4) {
PortId = 0;
WriteAlink (0x104C | (UINT32) (ABCFG << 29), BIT4, &StdHeader);
} else if (Value32 & BIT5) {
PortId = 1;
WriteAlink (0x104C | (UINT32) (ABCFG << 29), BIT5, &StdHeader);
} else if (Value32 & BIT6) {
PortId = 2;
WriteAlink (0x104C | (UINT32) (ABCFG << 29), BIT6, &StdHeader);
} else if (Value32 & BIT7) {
PortId = 3;
WriteAlink (0x104C | (UINT32) (ABCFG << 29), BIT7, &StdHeader);
}
Value8 = BIT2;
WriteMem (ACPI_MMIO_BASE + SMI_BASE + 0x3C, AccessWidth8, &Value8);
AmdFchWheaElogGpp (PortId);
}
return Status;
}
unsigned ReqSet_break( void )
{
set_break_req *acc;
set_break_ret *ret;
bp_t opcode;
acc = GetInPtr( 0 );
ret = GetOutPtr( 0 );
CONV_LE_32( acc->break_addr.offset );
CONV_LE_16( acc->break_addr.segment );
ReadMem( pid, &opcode, acc->break_addr.offset, sizeof( opcode ) );
ret->old = opcode;
opcode = BRK_POINT;
WriteMem( pid, &opcode, acc->break_addr.offset, sizeof( opcode ) );
Out( "ReqSet_break at " );
OutNum( acc->break_addr.offset );
Out( " (was " );
OutNum( ret->old );
Out( ")\n" );
return( sizeof( *ret ) );
}
void
CPersOver::PersOver()
{
if (PR_htValid) {
switch (PR_htInstr) {
case OVER_RD: {
BUSY_RETRY(ReadMemBusy());
ReadMem_data(P_addr);
ReadMemPause(OVER_WR);
}
break;
case OVER_WR: {
BUSY_RETRY(WriteMemBusy());
WriteMem(P_addr, ~PR_data);
WriteMemPause(OVER_RSM);
}
break;
case OVER_RSM: {
S_bResume = true;
HtPause(OVER_RTN);
}
break;
case OVER_RTN: {
BUSY_RETRY(SendReturnBusy_htmain());
SendReturn_htmain();
}
break;
default:
assert(0);
}
}
if (SR_bResume) {
S_bResume = false;
HtResume(0);
}
}
/**
* EnableEhciController - Assign resources and enable EHCI controllers
*
* @param[in] Value Controller PCI config address (bus# + device# + function#)
* @param[in] BarAddress Base address for Ehci controller
* @param[in] StdHeader AMD standard header config param
*/
VOID
EnableEhciController (
IN UINT32 Value,
IN UINT32 BarAddress,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT32 Var;
WritePci ((UINT32) Value + FCH_EHCI_REG10, AccessWidth32, &BarAddress, StdHeader);
RwPci ((UINT32) Value + FCH_EHCI_REG04, AccessWidth8, 0, BIT1 + BIT2, StdHeader);
ReadPci ((UINT32) Value + FCH_EHCI_REG10, AccessWidth32, &BarAddress, StdHeader);
if ( (BarAddress != - 1) && (BarAddress != 0) ) {
RwPci ((UINT32) Value + FCH_EHCI_REG04, AccessWidth8, 0, BIT1, StdHeader);
Var = 0x00020F00;
WriteMem (BarAddress + FCH_EHCI_BAR_REGC0, AccessWidth32, &Var);
RwMem (BarAddress + FCH_EHCI_BAR_REGA4, AccessWidth32, 0xFF00FF00, 0x00400040);
RwMem (BarAddress + FCH_EHCI_BAR_REGBC, AccessWidth32, ~( BIT12 + BIT14), BIT12 + BIT14);
RwMem (BarAddress + FCH_EHCI_BAR_REGB0, AccessWidth32, ~BIT5, BIT5);
RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGF0, AccessWidth16, ~BIT12, BIT12);
RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGF0, AccessWidth32, ~BIT16, BIT16);
RwMem (BarAddress + FCH_EHCI_BAR_REGB4, AccessWidth32, ~BIT12, BIT12);
RwMem (BarAddress + FCH_EHCI_BAR_REGC4, AccessWidth32, (UINT32) (~ 0x00000f00), 0x00000200);
RwMem (BarAddress + FCH_EHCI_BAR_REGC0, AccessWidth32, (UINT32) (~ 0x0000ff00), 0x00000f00);
RwPci ((UINT32) Value + FCH_EHCI_REG50, AccessWidth32, ~ ((UINT32) (0x01 << 6)), (UINT32) (0x01 << 6), StdHeader);
RwPci ((UINT32) Value + FCH_EHCI_REG50, AccessWidth32, ~ ((UINT32) (0x0F << 8)), (UINT32) (0x01 << 8), StdHeader);
RwPci ((UINT32) Value + FCH_EHCI_REG50, AccessWidth32, ~ ((UINT32) (0x0F << 12)), (UINT32) (0x01 << 12), StdHeader);
RwPci ((UINT32) Value + FCH_EHCI_REG50, AccessWidth32, ~ ((UINT32) (0x01 << 17)), (UINT32) (0x01 << 17), StdHeader);
RwPci ((UINT32) Value + FCH_EHCI_REG50, AccessWidth32, ~ ((UINT32) (0x01 << 21)), (UINT32) (0x01 << 21), StdHeader);
RwPci ((UINT32) Value + FCH_EHCI_REG50, AccessWidth32, ~ ((UINT32) (0x01 << 29)), (UINT32) (0x01 << 29), StdHeader);
RwPci ((UINT32) Value + FCH_EHCI_REG50 + 2, AccessWidth16, (UINT16)0xFFFF, BIT16 + BIT10, StdHeader);
RwPci ((UINT32) Value + FCH_EHCI_REG54, AccessWidth32, ~ (BIT0 + (3 << 5) + (7 << 7)), 0x0000026b, StdHeader);
RwPci ((UINT32) Value + FCH_EHCI_REG54, AccessWidth32, ~BIT4, BIT4, StdHeader);
RwPci ((UINT32) Value + FCH_EHCI_REG54, AccessWidth32, ~BIT11, BIT11, StdHeader);
RwPci ((UINT32) Value + FCH_EHCI_REG54, AccessWidth16, (UINT16)0x5FFF, BIT13 + BIT15, StdHeader);
RwPci ((UINT32) Value + FCH_EHCI_REG50 + 2, AccessWidth16, ~BIT3, BIT3, StdHeader);
RwPci ((UINT32) Value + FCH_EHCI_REG54 + 2, AccessWidth16, (UINT16)0xFFFC, BIT0 + BIT1, StdHeader);
RwPci ((UINT32) Value + FCH_EHCI_REG54 + 2, AccessWidth16, (UINT16)0xFFFB, BIT2, StdHeader);
RwPci ((UINT32) Value + FCH_EHCI_REG54 + 2, AccessWidth16, (UINT16)0xFFF7, BIT3, StdHeader);
}
}
void
CPersGupsCore::PersGupsCore()
{
MemAddr_t rndIdx = SR_base + ((PR_ran & (SR_tblSize - 1)) << 3); // QW index
if (PR_htValid) {
switch (PR_htInst) {
case PGC_ENTRY: {
P_ran = (uint64_t)(PR_ran << 1) ^ ((int64_t) PR_ran < 0 ? POLY : 0);
HtContinue(PGC_READ);
break;
}
case PGC_READ: {
BUSY_RETRY(ReadMemBusy());
ReadMem_intData(rndIdx);
ReadMemPause(PGC_WRITE);
break;
}
case PGC_WRITE: {
BUSY_RETRY(WriteMemBusy());
WriteMem(rndIdx, PR_intData^PR_ran, /*orderChk=*/ false);
P_ran = (uint64_t)(PR_ran << 1) ^ ((int64_t) PR_ran < 0 ? POLY : 0);
P_vecIdx += 1;
if (P_vecIdx < SR_vecLen) {
HtContinue(PGC_READ);
} else
HtContinue(PGC_RTN);
break;
}
case PGC_RTN: {
BUSY_RETRY(SendReturnBusy_GupsCore());
SendReturn_GupsCore();
break;
}
default:
assert(0);
}
}
}
/**
Function for 'mm' command.
@param[in] ImageHandle Handle to the Image (NULL if Internal).
@param[in] SystemTable Pointer to the System Table (NULL if Internal).
**/
SHELL_STATUS
EFIAPI
ShellCommandRunMm (
IN EFI_HANDLE ImageHandle,
IN EFI_SYSTEM_TABLE *SystemTable
)
{
EFI_STATUS Status;
EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev;
UINT64 Address;
UINT64 PciEAddress;
UINT64 Value;
UINT32 SegmentNumber;
EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width;
EFI_ACCESS_TYPE AccessType;
UINT64 Buffer;
UINTN Index;
UINTN Size;
// CHAR16 *ValueStr;
BOOLEAN Complete;
CHAR16 *InputStr;
BOOLEAN Interactive;
EFI_HANDLE *HandleBuffer;
UINTN BufferSize;
UINTN ItemValue;
LIST_ENTRY *Package;
CHAR16 *ProblemParam;
SHELL_STATUS ShellStatus;
CONST CHAR16 *Temp;
Value = 0;
Address = 0;
PciEAddress = 0;
IoDev = NULL;
HandleBuffer = NULL;
BufferSize = 0;
SegmentNumber = 0;
ShellStatus = SHELL_SUCCESS;
InputStr = NULL;
//
// Parse arguments
//
Width = EfiPciWidthUint8;
Size = 1;
AccessType = EfiMemory;
// ValueStr = NULL;
Interactive = TRUE;
Package = NULL;
Status = ShellCommandLineParse (ParamList, &Package, &ProblemParam, TRUE);
if (EFI_ERROR(Status)) {
if (Status == EFI_VOLUME_CORRUPTED && ProblemParam != NULL) {
ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_PROBLEM), gShellDebug1HiiHandle, ProblemParam);
FreePool(ProblemParam);
ShellStatus = SHELL_INVALID_PARAMETER;
goto Done;
} else {
ASSERT(FALSE);
}
} else {
if (ShellCommandLineGetCount(Package) < 2) {
ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_TOO_FEW), gShellDebug1HiiHandle);
ShellStatus = SHELL_INVALID_PARAMETER;
goto Done;
} else if (ShellCommandLineGetCount(Package) > 3) {
ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_TOO_MANY), gShellDebug1HiiHandle);
ShellStatus = SHELL_INVALID_PARAMETER;
goto Done;
} else if (ShellCommandLineGetFlag(Package, L"-w") && ShellCommandLineGetValue(Package, L"-w") == NULL) {
ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_NO_VALUE), gShellDebug1HiiHandle, L"-w");
ShellStatus = SHELL_INVALID_PARAMETER;
goto Done;
} else {
if (ShellCommandLineGetFlag(Package, L"-mmio")) {
AccessType = EFIMemoryMappedIo;
if (ShellCommandLineGetFlag(Package, L"-mem")
||ShellCommandLineGetFlag(Package, L"-io")
||ShellCommandLineGetFlag(Package, L"-pci")
||ShellCommandLineGetFlag(Package, L"-pcie")
){
ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_TOO_MANY), gShellDebug1HiiHandle);
ShellStatus = SHELL_INVALID_PARAMETER;
goto Done;
}
} else if (ShellCommandLineGetFlag(Package, L"-mem")) {
AccessType = EfiMemory;
if (ShellCommandLineGetFlag(Package, L"-io")
||ShellCommandLineGetFlag(Package, L"-pci")
||ShellCommandLineGetFlag(Package, L"-pcie")
){
ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_TOO_MANY), gShellDebug1HiiHandle);
ShellStatus = SHELL_INVALID_PARAMETER;
goto Done;
}
} else if (ShellCommandLineGetFlag(Package, L"-io")) {
AccessType = EfiIo;
if (ShellCommandLineGetFlag(Package, L"-pci")
||ShellCommandLineGetFlag(Package, L"-pcie")
){
ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_TOO_MANY), gShellDebug1HiiHandle);
ShellStatus = SHELL_INVALID_PARAMETER;
goto Done;
}
} else if (ShellCommandLineGetFlag(Package, L"-pci")) {
AccessType = EfiPciConfig;
if (ShellCommandLineGetFlag(Package, L"-pcie")
){
ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_TOO_MANY), gShellDebug1HiiHandle);
ShellStatus = SHELL_INVALID_PARAMETER;
goto Done;
}
} else if (ShellCommandLineGetFlag(Package, L"-pcie")) {
AccessType = EfiPciEConfig;
}
}
//
// Non interactive for a script file or for the specific parameter
//
if (gEfiShellProtocol->BatchIsActive() || ShellCommandLineGetFlag (Package, L"-n")) {
Interactive = FALSE;
}
Temp = ShellCommandLineGetValue(Package, L"-w");
if (Temp != NULL) {
ItemValue = ShellStrToUintn (Temp);
switch (ItemValue) {
case 1:
Width = EfiPciWidthUint8;
Size = 1;
break;
case 2:
Width = EfiPciWidthUint16;
Size = 2;
break;
case 4:
Width = EfiPciWidthUint32;
Size = 4;
break;
case 8:
Width = EfiPciWidthUint64;
Size = 8;
break;
default:
ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_PROBLEM_VAL), gShellDebug1HiiHandle, L"-w");
ShellStatus = SHELL_INVALID_PARAMETER;
goto Done;
}
}
Temp = ShellCommandLineGetRawValue(Package, 1);
if (!ShellIsHexOrDecimalNumber(Temp, TRUE, FALSE) || EFI_ERROR(ShellConvertStringToUint64(Temp, (UINT64*)&Address, TRUE, FALSE))) {
ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_PROBLEM), gShellDebug1HiiHandle, Temp);
ShellStatus = SHELL_INVALID_PARAMETER;
goto Done;
}
Temp = ShellCommandLineGetRawValue(Package, 2);
if (Temp != NULL) {
//
// Per spec if value is specified, then -n is assumed.
//
Interactive = FALSE;
if (!ShellIsHexOrDecimalNumber(Temp, TRUE, FALSE) || EFI_ERROR(ShellConvertStringToUint64(Temp, &Value, TRUE, FALSE))) {
ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_PROBLEM), gShellDebug1HiiHandle, Temp);
ShellStatus = SHELL_INVALID_PARAMETER;
goto Done;
}
switch (Size) {
case 1:
if (Value > 0xFF) {
ShellStatus = SHELL_INVALID_PARAMETER;
}
break;
case 2:
if (Value > 0xFFFF) {
ShellStatus = SHELL_INVALID_PARAMETER;
}
break;
case 4:
if (Value > 0xFFFFFFFF) {
ShellStatus = SHELL_INVALID_PARAMETER;
}
break;
default:
break;
}
if (ShellStatus != SHELL_SUCCESS) {
ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_PROBLEM), gShellDebug1HiiHandle, Temp);
ShellStatus = SHELL_INVALID_PARAMETER;
goto Done;
}
}
if ((Address & (Size - 1)) != 0) {
ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_MM_NOT_ALIGNED), gShellDebug1HiiHandle, Address);
ShellStatus = SHELL_INVALID_PARAMETER;
goto Done;
}
//
// locate DeviceIO protocol interface
//
if (AccessType != EfiMemory) {
Status = gBS->LocateHandleBuffer (
ByProtocol,
&gEfiPciRootBridgeIoProtocolGuid,
NULL,
&BufferSize,
&HandleBuffer
);
if (EFI_ERROR (Status)) {
ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_PCIRBIO_NF), gShellDebug1HiiHandle);
ShellStatus = SHELL_NOT_FOUND;
goto Done;
}
//
// In the case of PCI or PCIE
// Get segment number and mask the segment bits in Address
//
if (AccessType == EfiPciEConfig) {
SegmentNumber = (UINT32) RShiftU64 (Address, 36) & 0xff;
Address &= 0xfffffffffULL;
} else {
if (AccessType == EfiPciConfig) {
SegmentNumber = (UINT32) RShiftU64 (Address, 32) & 0xff;
Address &= 0xffffffff;
}
}
//
// Find the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL of the specified segment number
//
for (Index = 0; Index < BufferSize; Index++) {
Status = gBS->HandleProtocol (
HandleBuffer[Index],
&gEfiPciRootBridgeIoProtocolGuid,
(VOID *) &IoDev
);
if (EFI_ERROR (Status)) {
continue;
}
if (IoDev->SegmentNumber != SegmentNumber) {
IoDev = NULL;
}
}
if (IoDev == NULL) {
ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_MM_SEGMENT_NOT_FOUND), gShellDebug1HiiHandle, SegmentNumber);
ShellStatus = SHELL_INVALID_PARAMETER;
goto Done;
}
}
if (AccessType == EfiIo && Address + Size > 0x10000) {
ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_MM_ADDRESS_RANGE), gShellDebug1HiiHandle);
ShellStatus = SHELL_INVALID_PARAMETER;
goto Done;
}
if (AccessType == EfiPciEConfig) {
GetPciEAddressFromInputAddress (Address, &PciEAddress);
}
//
// Set value
//
if (ShellCommandLineGetRawValue(Package, 2) != NULL) {
if (AccessType == EFIMemoryMappedIo) {
IoDev->Mem.Write (IoDev, Width, Address, 1, &Value);
} else if (AccessType == EfiIo) {
IoDev->Io.Write (IoDev, Width, Address, 1, &Value);
} else if (AccessType == EfiPciConfig) {
IoDev->Pci.Write (IoDev, Width, Address, 1, &Value);
} else if (AccessType == EfiPciEConfig) {
IoDev->Pci.Write (IoDev, Width, PciEAddress, 1, &Value);
} else {
WriteMem (Width, Address, 1, &Value);
}
ASSERT(ShellStatus == SHELL_SUCCESS);
goto Done;
}
//
// non-interactive mode
//
if (!Interactive) {
Buffer = 0;
if (AccessType == EFIMemoryMappedIo) {
if (!gEfiShellProtocol->BatchIsActive()) {
ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_MM_MMIO), gShellDebug1HiiHandle);
}
IoDev->Mem.Read (IoDev, Width, Address, 1, &Buffer);
} else if (AccessType == EfiIo) {
if (!gEfiShellProtocol->BatchIsActive()) {
ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_MM_IO), gShellDebug1HiiHandle);
}
IoDev->Io.Read (IoDev, Width, Address, 1, &Buffer);
} else if (AccessType == EfiPciConfig) {
if (!gEfiShellProtocol->BatchIsActive()) {
ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_MM_PCI), gShellDebug1HiiHandle);
}
IoDev->Pci.Read (IoDev, Width, Address, 1, &Buffer);
} else if (AccessType == EfiPciEConfig) {
if (!gEfiShellProtocol->BatchIsActive()) {
ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_MM_PCIE), gShellDebug1HiiHandle);
}
IoDev->Pci.Read (IoDev, Width, PciEAddress, 1, &Buffer);
} else {
if (!gEfiShellProtocol->BatchIsActive()) {
ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_MM_MEM), gShellDebug1HiiHandle);
}
ReadMem (Width, Address, 1, &Buffer);
}
if (!gEfiShellProtocol->BatchIsActive()) {
ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_MM_ADDRESS), gShellDebug1HiiHandle, Address);
}
if (Size == 1) {
ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_MM_BUF2), gShellDebug1HiiHandle, (UINTN)Buffer);
} else if (Size == 2) {
ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_MM_BUF4), gShellDebug1HiiHandle, (UINTN)Buffer);
} else if (Size == 4) {
ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_MM_BUF8), gShellDebug1HiiHandle, (UINTN)Buffer);
} else if (Size == 8) {
ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_MM_BUF16), gShellDebug1HiiHandle, Buffer);
}
ShellPrintEx(-1, -1, L"\r\n");
ASSERT(ShellStatus == SHELL_SUCCESS);
goto Done;
}
//
// interactive mode
//
Complete = FALSE;
do {
if (AccessType == EfiIo && Address + Size > 0x10000) {
ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_MM_ADDRESS_RANGE2), gShellDebug1HiiHandle);
break;
}
Buffer = 0;
if (AccessType == EFIMemoryMappedIo) {
ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_MM_MMIO), gShellDebug1HiiHandle);
IoDev->Mem.Read (IoDev, Width, Address, 1, &Buffer);
} else if (AccessType == EfiIo) {
ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_MM_IO), gShellDebug1HiiHandle);
IoDev->Io.Read (IoDev, Width, Address, 1, &Buffer);
} else if (AccessType == EfiPciConfig) {
ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_MM_PCI), gShellDebug1HiiHandle);
IoDev->Pci.Read (IoDev, Width, Address, 1, &Buffer);
} else if (AccessType == EfiPciEConfig) {
ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_MM_PCIE), gShellDebug1HiiHandle);
IoDev->Pci.Read (IoDev, Width, PciEAddress, 1, &Buffer);
} else {
ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_MM_MEM), gShellDebug1HiiHandle);
ReadMem (Width, Address, 1, &Buffer);
}
ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_MM_ADDRESS), gShellDebug1HiiHandle, Address);
if (Size == 1) {
ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_MM_BUF2), gShellDebug1HiiHandle, (UINTN)Buffer);
} else if (Size == 2) {
ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_MM_BUF4), gShellDebug1HiiHandle, (UINTN)Buffer);
} else if (Size == 4) {
ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_MM_BUF8), gShellDebug1HiiHandle, (UINTN)Buffer);
} else if (Size == 8) {
ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_MM_BUF16), gShellDebug1HiiHandle, Buffer);
}
ShellPrintEx(-1, -1, L" > ");
//
// wait user input to modify
//
if (InputStr != NULL) {
FreePool(InputStr);
InputStr = NULL;
}
ShellPromptForResponse(ShellPromptResponseTypeFreeform, NULL, (VOID**)&InputStr);
//
// skip space characters
//
for (Index = 0; InputStr != NULL && InputStr[Index] == ' '; Index++);
//
// parse input string
//
if (InputStr != NULL && (InputStr[Index] == '.' || InputStr[Index] == 'q' || InputStr[Index] == 'Q')) {
Complete = TRUE;
} else if (InputStr == NULL || InputStr[Index] == CHAR_NULL) {
//
// Continue to next address
//
} else if (GetHex (InputStr + Index, &Buffer) && Buffer <= MaxNum[Width]) {
if (AccessType == EFIMemoryMappedIo) {
IoDev->Mem.Write (IoDev, Width, Address, 1, &Buffer);
} else if (AccessType == EfiIo) {
IoDev->Io.Write (IoDev, Width, Address, 1, &Buffer);
} else if (AccessType == EfiPciConfig) {
IoDev->Pci.Write (IoDev, Width, Address, 1, &Buffer);
} else if (AccessType == EfiPciEConfig) {
IoDev->Pci.Write (IoDev, Width, PciEAddress, 1, &Buffer);
} else {
WriteMem (Width, Address, 1, &Buffer);
}
} else {
ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_MM_ERROR), gShellDebug1HiiHandle);
continue;
// PrintToken (STRING_TOKEN (STR_IOMOD_ERROR), HiiHandle);
}
Address += Size;
if (AccessType == EfiPciEConfig) {
GetPciEAddressFromInputAddress (Address, &PciEAddress);
}
ShellPrintEx(-1, -1, L"\r\n");
// Print (L"\n");
} while (!Complete);
}
ASSERT(ShellStatus == SHELL_SUCCESS);
Done:
if (InputStr != NULL) {
FreePool(InputStr);
}
if (HandleBuffer != NULL) {
FreePool (HandleBuffer);
}
if (Package != NULL) {
ShellCommandLineFreeVarList (Package);
}
return ShellStatus;
}
void
CPersStencil::PersStencil()
{
if (PR_htValid) {
//fprintf(stderr,"stencil was called and r_ts_htValid is %d and state is %d and thread id is %d\n",
// r_ts_htValid, (int)r_ts_htInst, PR_htId.to_int());
switch (PR_htInst) {
case START: // 1
{
P_change = 0;
P_i = 0;
P_ram_rdVal = PR_htId; // indexed only by thread id
HtContinue(FIRST_TWO_ROWS_LOOP_TOP);
}
break;
// fill in first two rows of temp array
// for (i = 0; i < m; i++) {
// tempa[0][i] = a[0][i]; // main memory read
// tempa[1][i] = a[1][i]; // main memory read
// }
case FIRST_TWO_ROWS_LOOP_TOP: // 3
{
if (!(P_i < P_p_m)) {
HtContinue(FIRST_TWO_ROWS_LOOP_EXIT);
break;
}
if (ReadMemBusy()) {
HtRetry();
break;
}
// First read request
memAddrT memAddr = addr(P_p_a, 0 + P_p_js, P_i + P_p_is);
sc_uint<STENCIL_HTID_W> ramWrAddr = PR_htId;
// Mif0RdReq(rsmInst, memAddr, rdDstId, ramIdx, bFirst, bLast)
// Mif0RdReq(CHAINED_READ, /* rsmInst */
ReadMem_j0(memAddr, /* memAddr */
ramWrAddr); /* ramIdx */
HtContinue(FIRST_TWO_ROWS_READ2);
}
break;
case FIRST_TWO_ROWS_READ2: // 4
{
// Second read request
if (ReadMemBusy()) {
HtRetry();
break;
}
// Set up for write to tempa[P_i] on next clock
P_ram_i = tempaIndex(P_i);
memAddrT memAddr = addr(P_p_a, 1 + P_p_js, P_i + P_p_is);
sc_uint<STENCIL_HTID_W> ramWrAddr = PR_htId;
// Mif0RdReq(rsmInst, memAddr, rdDstId, ramIdx, bFirst, bLast)
ReadMem_j1(memAddr, /* memAddr */
ramWrAddr); /* ramIdx */
ReadMemPause(FIRST_TWO_ROWS_ASSIGN);
}
break;
case FIRST_TWO_ROWS_ASSIGN: // 5
{
// tempa[0][P_i] = MifRdVal(1);
// tempa[1][P_i] = MifRdVal(2);
GW_tempa.write_addr(P_ram_i);
GW_tempa.j0 = GR_mifRdVal.j0;
GW_tempa.j1 = GR_mifRdVal.j1;
// increment i and loop back
P_i = P_i + 1;
HtContinue(FIRST_TWO_ROWS_LOOP_TOP);
}
break;
case FIRST_TWO_ROWS_LOOP_EXIT: // 6
{
// for (j = 2; j < n; j++) {
P_j = 2;
// Set up for read from tempa[0] on next clock
P_ram_i = tempaIndex(0);
HtContinue(J_LOOP_TOP);
}
break;
case J_LOOP_TOP: // 7
{
if (!(P_j < P_p_n)) {
HtContinue(J_LOOP_EXIT);
break;
}
if (ReadMemBusy()) {
HtRetry();
break;
}
P_t00 = GR_tempa.j0;
P_t10 = GR_tempa.j1;
// Set up to read from tempa[1] on next clock
P_ram_i = tempaIndex(1);
#if 0
// These have to be delayeduntil next slot
// copy initial values for first two columns into "registers"
// j i j i
P_t01 = tempa[0][1];
P_t11 = tempa[1][1];
#endif
// P_t20 = a[j][0]; P_t21 = a[j][1]; // main memory reads
// First read request
memAddrT memAddr = addr(P_p_a, P_j + P_p_js, 0 + P_p_is);
sc_uint<STENCIL_HTID_W> ramWrAddr = PR_htId; // P_t20
// Mif0RdReq(rsmInst, memAddr, rdDstId, ramIdx, bFirst, bLast)
ReadMem_j0(memAddr, /* memAddr */
ramWrAddr); /* ramIdx */
HtContinue(J_LOOP_READ2);
}
break;
case J_LOOP_READ2: // 8
{
// Second read request
if (ReadMemBusy()) {
HtRetry();
break;
}
P_t01 = GR_tempa.j0;
P_t11 = GR_tempa.j1;
memAddrT memAddr = addr(P_p_a, P_j + P_p_js, 1 + P_p_is);
sc_uint<STENCIL_HTID_W> ramWrAddr = PR_htId; // P_t21
// Mif0RdReq(rsmInst, memAddr, rdDstId, ramIdx, bFirst, bLast)
ReadMem_j1(memAddr, /* memAddr */
ramWrAddr); /* ramIdx */
// Set up to write to tempa[0] on next clock
P_ram_i = tempaIndex(0);
ReadMemPause(J_LOOP_ASSIGN);
}
break;
case J_LOOP_ASSIGN: // 9
{
P_t20 = GR_mifRdVal.j0;
P_t21 = GR_mifRdVal.j1;
// Save these first two values (shift columns up) for next j
// tempa[0][0] = P_t10;
// tempa[1][0] = P_t20;
GW_tempa.write_addr(P_ram_i);
GW_tempa.j0 = P_t10;
GW_tempa.j1 = P_t20;
#if 0
// block ram writes to slot 1 delayed until next clock
tempa[0][1] = P_t11;
tempa[1][1] = P_t21;
#endif
// Set up to write to tempa[1] on next clock
P_ram_i = tempaIndex(1);
// for (i = 2; i < m; i++) {
P_i = 2;
HtContinue(J_LOOP_ASSIGN2);
}
break;
case J_LOOP_ASSIGN2: // 15
{
// tempa[0][1] = P_t11;
// tempa[1][1] = P_t21;
GW_tempa.write_addr(P_ram_i);
GW_tempa.j0 = P_t11;
GW_tempa.j1 = P_t21;
// Set up to read from tempa[P_i] on next clock
P_ram_i = tempaIndex(P_i);
HtContinue(I_LOOP_TOP);
}
break;
case I_LOOP_TOP: // 11
{
if (!(P_i < P_p_m)) {
HtContinue(I_LOOP_EXIT);
break;
}
if (ReadMemBusy()) {
HtRetry();
break;
}
// Get third column
// P_t02 = tempa[0][P_i]; // AE memory
// P_t12 = tempa[1][P_i]; // AE memory
P_t02 = GR_tempa.j0;
P_t12 = GR_tempa.j1;
// P_t22 = a[j][i]; // main memory read
memAddrT memAddr = addr(P_p_a, P_j + P_p_js, P_i + P_p_is);
sc_uint<STENCIL_HTID_W> ramWrAddr = PR_htId; // P_t22
// Mif0RdReq(rsmInst, memAddr, rdDstId, ramIdx, bFirst, bLast)
ReadMem_j0(memAddr, /* memAddr */
ramWrAddr); /* ramIdx */
// Set up to write to tempa[P_i] on next clock
assert(P_ram_i == tempaIndex(P_i)); // should already be set
P_ram_i = tempaIndex(P_i);
ReadMemPause(I_LOOP_ASSIGN);
}
break;
case I_LOOP_ASSIGN: // 12
{
if (WriteMemBusy()) {
HtRetry();
break;
}
// Get third column
P_t22 = GR_mifRdVal.j0;
// Save these values (shift column up) for next j
// tempa[0][P_i] = P_t12;
// tempa[1][P_i] = P_t22;
GW_tempa.write_addr(P_ram_i);
GW_tempa.j0 = P_t12;
GW_tempa.j1 = P_t22;
P_res =
mulX(P_p_w0, P_t11) +
mulX(P_p_w1, (P_t10 + P_t01 + P_t12 + P_t21)) +
mulX(P_p_w2, (P_t00 + P_t20 + P_t02 + P_t22));
// newa[j-1][i-1] = res; // main memory store
memAddrT memAddr = addr(P_p_newa, P_p_js + P_j - 1, P_p_is + P_i - 1);
WriteMem(memAddr, (sc_uint<MEM_DATA_W>)P_res);
WriteMemPause(I_LOOP_CHANGE);
}
break;
case I_LOOP_CHANGE: // 13
{
P_diff = fabs(P_res - P_t11);
P_change = fmax(P_change, P_diff);
// prepare for next iteration; shift columns left
P_t00 = P_t01; P_t01 = P_t02;
P_t10 = P_t11; P_t11 = P_t12;
P_t20 = P_t21; P_t21 = P_t22;
P_i = P_i + 1;
// Set up to read from tempa[P_i] on next clock
P_ram_i = tempaIndex(P_i);
HtContinue(I_LOOP_TOP);
}
break;
case I_LOOP_EXIT: // 14
{
// increment j and loop back
P_j = P_j + 1;
// Set up for read from tempa[0] on next clock
P_ram_i = tempaIndex(0);
HtContinue(J_LOOP_TOP);
}
break;
case J_LOOP_EXIT: // 10
{
HtContinue(DONE);
}
break;
case DONE: // 2
{
if (SendReturnBusy_stencil()) {
HtRetry();
break;
}
#if 0
fprintf(stderr, "not busy -- doing return from thread %d change is %g\n",
(int)(P_htId),
((double)P_change) / ((double)(ONE)));
#endif
SendReturn_stencil(P_change);
// HtPause();
}
break;
default:
#if 0
fprintf(stderr, "Stencil did not handle state %d\n", (int)r_ts_htInst);
#endif
break;
}
} // r_ts_htValid
}
void CPersBcm::PersBcm()
{
if (PR1_htValid) {
switch (PR1_htInst) {
// Initial Entry Point from Host Code -> BCM_ENTRY
//
// Read in Task information
// GR_task -> midState[8]/data[3]/initNonce/lastNonce/target[3]
case BCM_ENTRY: {
if (ReadMemBusy()) {
HtRetry();
break;
}
ReadMem_task(PR1_pBcmTask);
ReadMemPause(BCM_TASK_VALID);
}
break;
// Force initial task to be valid
// Setup initial Nonce
case BCM_TASK_VALID: {
S_bTaskValid = true;
S_nonce = S_task.m_initNonce;
S_hashCount = 0;
HtContinue(BCM_CHK_RTN);
}
break;
// Main hash loop, sit and check the result queue
case BCM_CHK_RTN: {
if (SendReturnBusy_bcm() || SendHostMsgBusy()) {
HtRetry();
break;
}
if (S_hashCount > 1000000) {
SendHostMsg(BCM_HASHES_COMPLETED, (ht_uint56)S_hashCount);
S_hashCount = 0;
}
if (S_nonceHitQue.empty()) {
// No results waiting
if (S_bTaskValid) {
HtContinue(BCM_CHK_RTN);
} else {
if (S_hashCount > 0) {
SendHostMsg(BCM_HASHES_COMPLETED, (ht_uint56)S_hashCount);
S_hashCount = 0;
}
SendReturn_bcm(P1_pBcmTask);
}
} else {
// Results are waiting to be processed
if (S_bcmRsltQue.empty())
HtContinue(BCM_CHK_RTN);
else
HtContinue(BCM_WR_RSLT1);
}
// Reset index for results to zero (for writing to memory)
S_rsltQwIdx = 0;
}
break;
// BCM_WR_RSLT1->3, steps to write a result to memory
case BCM_WR_RSLT1: {
if (WriteMemBusy()) {
HtRetry();
break;
}
ht_uint48 memAddr = S_bcmRsltQue.front() | (S_rsltQwIdx << 3);
WriteMem(memAddr, S_task.m_qw[S_rsltQwIdx]);
S_rsltQwIdx += 1;
if (S_rsltQwIdx < 5)
HtContinue(BCM_WR_RSLT1);
else
HtContinue(BCM_WR_RSLT2);
}
break;
case BCM_WR_RSLT2: {
if (WriteMemBusy()) {
HtRetry();
break;
}
ht_uint48 memAddr = S_bcmRsltQue.front() | (5 << 3);
ht_uint64 memData;
memData(31, 0) = S_task.m_qw[5] & 0xffffffff;
memData(63, 32) = BcmByteSwap32(S_nonceHitQue.front());
S_nonceHitQue.pop();
WriteMem(memAddr, memData);
WriteMemPause(BCM_WR_RSLT3);
}
break;
case BCM_WR_RSLT3: {
if (SendHostMsgBusy()) {
HtRetry();
break;
}
SendHostMsg(BCM_RSLT_BUF_RDY, (ht_uint56)S_bcmRsltQue.front());
S_bcmRsltQue.pop();
HtContinue(BCM_CHK_RTN);
}
break;
default:
assert(0);
}
}
// temps used within macros
uint32_t temp1, temp2, tmp;
// Input Valid Signal reflects Task Valid Signal
T1_vld = S_bTaskValid;
// *** State Setup ***
// Setup T1_data
T1_data.m_dw[0] = S_task.m_data[0];
T1_data.m_dw[1] = S_task.m_data[1];
T1_data.m_dw[2] = S_task.m_data[2];
T1_data.m_dw[3] = S_nonce;
T1_data.m_dw[4] = 0x80000000;
T1_data.m_dw[5] = 0x00000000;
T1_data.m_dw[6] = 0x00000000;
T1_data.m_dw[7] = 0x00000000;
T1_data.m_dw[8] = 0x00000000;
T1_data.m_dw[9] = 0x00000000;
T1_data.m_dw[10] = 0x00000000;
T1_data.m_dw[11] = 0x00000000;
T1_data.m_dw[12] = 0x00000000;
T1_data.m_dw[13] = 0x00000000;
T1_data.m_dw[14] = 0x00000000;
T1_data.m_dw[15] = 0x00000280;
// Setup T1_state
T1_state.m_state[0] = S_task.m_midState.m_state[0];
T1_state.m_state[1] = S_task.m_midState.m_state[1];
T1_state.m_state[2] = S_task.m_midState.m_state[2];
T1_state.m_state[3] = S_task.m_midState.m_state[3];
T1_state.m_state[4] = S_task.m_midState.m_state[4];
T1_state.m_state[5] = S_task.m_midState.m_state[5];
T1_state.m_state[6] = S_task.m_midState.m_state[6];
T1_state.m_state[7] = S_task.m_midState.m_state[7];
// Nonce
T1_nonce = S_nonce;
// *** Do Work ***
// 64-deep Hash Cycle 1
Q(T2_state, 0, T2_data, 0x428A2F98);
Q(T3_state, 7, T3_data, 0x71374491);
Q(T4_state, 6, T4_data, 0xB5C0FBCF);
Q(T5_state, 5, T5_data, 0xE9B5DBA5);
Q(T6_state, 4, T6_data, 0x3956C25B);
Q(T7_state, 3, T7_data, 0x59F111F1);
Q(T8_state, 2, T8_data, 0x923F82A4);
Q(T9_state, 1, T9_data, 0xAB1C5ED5);
Q(T10_state, 0, T10_data, 0xD807AA98);
Q(T11_state, 7, T11_data, 0x12835B01);
Q(T12_state, 6, T12_data, 0x243185BE);
Q(T13_state, 5, T13_data, 0x550C7DC3);
Q(T14_state, 4, T14_data, 0x72BE5D74);
Q(T15_state, 3, T15_data, 0x80DEB1FE);
Q(T16_state, 2, T16_data, 0x9BDC06A7);
Q(T17_state, 1, T17_data, 0xC19BF174);
R(T18_state, 0, T18_data, 0xE49B69C1);
R(T19_state, 7, T19_data, 0xEFBE4786);
R(T20_state, 6, T20_data, 0x0FC19DC6);
R(T21_state, 5, T21_data, 0x240CA1CC);
R(T22_state, 4, T22_data, 0x2DE92C6F);
R(T23_state, 3, T23_data, 0x4A7484AA);
R(T24_state, 2, T24_data, 0x5CB0A9DC);
R(T25_state, 1, T25_data, 0x76F988DA);
R(T26_state, 0, T26_data, 0x983E5152);
R(T27_state, 7, T27_data, 0xA831C66D);
R(T28_state, 6, T28_data, 0xB00327C8);
R(T29_state, 5, T29_data, 0xBF597FC7);
R(T30_state, 4, T30_data, 0xC6E00BF3);
R(T31_state, 3, T31_data, 0xD5A79147);
R(T32_state, 2, T32_data, 0x06CA6351);
R(T33_state, 1, T33_data, 0x14292967);
R(T34_state, 0, T34_data, 0x27B70A85);
R(T35_state, 7, T35_data, 0x2E1B2138);
R(T36_state, 6, T36_data, 0x4D2C6DFC);
R(T37_state, 5, T37_data, 0x53380D13);
R(T38_state, 4, T38_data, 0x650A7354);
R(T39_state, 3, T39_data, 0x766A0ABB);
R(T40_state, 2, T40_data, 0x81C2C92E);
R(T41_state, 1, T41_data, 0x92722C85);
R(T42_state, 0, T42_data, 0xA2BFE8A1);
R(T43_state, 7, T43_data, 0xA81A664B);
R(T44_state, 6, T44_data, 0xC24B8B70);
R(T45_state, 5, T45_data, 0xC76C51A3);
R(T46_state, 4, T46_data, 0xD192E819);
R(T47_state, 3, T47_data, 0xD6990624);
R(T48_state, 2, T48_data, 0xF40E3585);
R(T49_state, 1, T49_data, 0x106AA070);
R(T50_state, 0, T50_data, 0x19A4C116);
R(T51_state, 7, T51_data, 0x1E376C08);
R(T52_state, 6, T52_data, 0x2748774C);
R(T53_state, 5, T53_data, 0x34B0BCB5);
R(T54_state, 4, T54_data, 0x391C0CB3);
R(T55_state, 3, T55_data, 0x4ED8AA4A);
R(T56_state, 2, T56_data, 0x5B9CCA4F);
R(T57_state, 1, T57_data, 0x682E6FF3);
R(T58_state, 0, T58_data, 0x748F82EE);
R(T59_state, 7, T59_data, 0x78A5636F);
R(T60_state, 6, T60_data, 0x84C87814);
R(T61_state, 5, T61_data, 0x8CC70208);
R(T62_state, 4, T62_data, 0x90BEFFFA);
R(T63_state, 3, T63_data, 0xA4506CEB);
R(T64_state, 2, T64_data, 0xBEF9A3F7);
R(T65_state, 1, T65_data, 0xC67178F2);
// Add following hash cycle 1
T66_state.m_state[0] = T66_state.m_state[0] + S_task.m_midState.m_state[0];
T66_state.m_state[1] = T66_state.m_state[1] + S_task.m_midState.m_state[1];
T66_state.m_state[2] = T66_state.m_state[2] + S_task.m_midState.m_state[2];
T66_state.m_state[3] = T66_state.m_state[3] + S_task.m_midState.m_state[3];
T66_state.m_state[4] = T66_state.m_state[4] + S_task.m_midState.m_state[4];
T66_state.m_state[5] = T66_state.m_state[5] + S_task.m_midState.m_state[5];
T66_state.m_state[6] = T66_state.m_state[6] + S_task.m_midState.m_state[6];
T66_state.m_state[7] = T66_state.m_state[7] + S_task.m_midState.m_state[7];
// State Setup
// Setup T67_data
T67_data.m_dw[0] = T67_state.m_state[0];
T67_data.m_dw[1] = T67_state.m_state[1];
T67_data.m_dw[2] = T67_state.m_state[2];
T67_data.m_dw[3] = T67_state.m_state[3];
T67_data.m_dw[4] = T67_state.m_state[4];
T67_data.m_dw[5] = T67_state.m_state[5];
T67_data.m_dw[6] = T67_state.m_state[6];
T67_data.m_dw[7] = T67_state.m_state[7];
T67_data.m_dw[8] = 0x00000000;
T67_data.m_dw[9] = 0x00000000;
T67_data.m_dw[10] = 0x00000000;
T67_data.m_dw[11] = 0x00000000;
T67_data.m_dw[12] = 0x00000000;
T67_data.m_dw[13] = 0x00000000;
T67_data.m_dw[14] = 0x00000000;
T67_data.m_dw[15] = 0x00000000;
T67_data.m_uc[35] = 0x80;
T67_data.m_uc[61] = 0x01;
// Setup T67_state
T67_state.m_state[0] = 0x6A09E667;
T67_state.m_state[1] = 0xBB67AE85;
T67_state.m_state[2] = 0x3C6EF372;
T67_state.m_state[3] = 0xA54FF53A;
T67_state.m_state[4] = 0x510E527F;
T67_state.m_state[5] = 0x9B05688C;
T67_state.m_state[6] = 0x1F83D9AB;
T67_state.m_state[7] = 0x5BE0CD19;
// 64-deep Hash Cycle 2
Q(T68_state, 0, T68_data, 0x428A2F98);
Q(T69_state, 7, T69_data, 0x71374491);
Q(T70_state, 6, T70_data, 0xB5C0FBCF);
Q(T71_state, 5, T71_data, 0xE9B5DBA5);
Q(T72_state, 4, T72_data, 0x3956C25B);
Q(T73_state, 3, T73_data, 0x59F111F1);
Q(T74_state, 2, T74_data, 0x923F82A4);
Q(T75_state, 1, T75_data, 0xAB1C5ED5);
Q(T76_state, 0, T76_data, 0xD807AA98);
Q(T77_state, 7, T77_data, 0x12835B01);
Q(T78_state, 6, T78_data, 0x243185BE);
Q(T79_state, 5, T79_data, 0x550C7DC3);
Q(T80_state, 4, T80_data, 0x72BE5D74);
Q(T81_state, 3, T81_data, 0x80DEB1FE);
Q(T82_state, 2, T82_data, 0x9BDC06A7);
Q(T83_state, 1, T83_data, 0xC19BF174);
R(T84_state, 0, T84_data, 0xE49B69C1);
R(T85_state, 7, T85_data, 0xEFBE4786);
R(T86_state, 6, T86_data, 0x0FC19DC6);
R(T87_state, 5, T87_data, 0x240CA1CC);
R(T88_state, 4, T88_data, 0x2DE92C6F);
R(T89_state, 3, T89_data, 0x4A7484AA);
R(T90_state, 2, T90_data, 0x5CB0A9DC);
R(T91_state, 1, T91_data, 0x76F988DA);
R(T92_state, 0, T92_data, 0x983E5152);
R(T93_state, 7, T93_data, 0xA831C66D);
R(T94_state, 6, T94_data, 0xB00327C8);
R(T95_state, 5, T95_data, 0xBF597FC7);
R(T96_state, 4, T96_data, 0xC6E00BF3);
R(T97_state, 3, T97_data, 0xD5A79147);
R(T98_state, 2, T98_data, 0x06CA6351);
R(T99_state, 1, T99_data, 0x14292967);
R(T100_state, 0, T100_data, 0x27B70A85);
R(T101_state, 7, T101_data, 0x2E1B2138);
R(T102_state, 6, T102_data, 0x4D2C6DFC);
R(T103_state, 5, T103_data, 0x53380D13);
R(T104_state, 4, T104_data, 0x650A7354);
R(T105_state, 3, T105_data, 0x766A0ABB);
R(T106_state, 2, T106_data, 0x81C2C92E);
R(T107_state, 1, T107_data, 0x92722C85);
R(T108_state, 0, T108_data, 0xA2BFE8A1);
R(T109_state, 7, T109_data, 0xA81A664B);
R(T110_state, 6, T110_data, 0xC24B8B70);
R(T111_state, 5, T111_data, 0xC76C51A3);
R(T112_state, 4, T112_data, 0xD192E819);
R(T113_state, 3, T113_data, 0xD6990624);
R(T114_state, 2, T114_data, 0xF40E3585);
R(T115_state, 1, T115_data, 0x106AA070);
R(T116_state, 0, T116_data, 0x19A4C116);
R(T117_state, 7, T117_data, 0x1E376C08);
R(T118_state, 6, T118_data, 0x2748774C);
R(T119_state, 5, T119_data, 0x34B0BCB5);
R(T120_state, 4, T120_data, 0x391C0CB3);
R(T121_state, 3, T121_data, 0x4ED8AA4A);
R(T122_state, 2, T122_data, 0x5B9CCA4F);
R(T123_state, 1, T123_data, 0x682E6FF3);
R(T124_state, 0, T124_data, 0x748F82EE);
R(T125_state, 7, T125_data, 0x78A5636F);
R(T126_state, 6, T126_data, 0x84C87814);
R(T127_state, 5, T127_data, 0x8CC70208);
R(T128_state, 4, T128_data, 0x90BEFFFA);
R(T129_state, 3, T129_data, 0xA4506CEB);
R(T130_state, 2, T130_data, 0xBEF9A3F7);
R(T131_state, 1, T131_data, 0xC67178F2);
// Add following hash cycle 2
T132_state.m_state[0] = BcmByteSwap32(T132_state.m_state[0] + 0x6A09E667);
T132_state.m_state[1] = BcmByteSwap32(T132_state.m_state[1] + 0xBB67AE85);
T132_state.m_state[2] = BcmByteSwap32(T132_state.m_state[2] + 0x3C6EF372);
T132_state.m_state[3] = BcmByteSwap32(T132_state.m_state[3] + 0xA54FF53A);
T132_state.m_state[4] = BcmByteSwap32(T132_state.m_state[4] + 0x510E527F);
T132_state.m_state[5] = BcmByteSwap32(T132_state.m_state[5] + 0x9B05688C);
T132_state.m_state[6] = BcmByteSwap32(T132_state.m_state[6] + 0x1F83D9AB);
T132_state.m_state[7] = BcmByteSwap32(T132_state.m_state[7] + 0x5BE0CD19);
// *** End Checks ***
// Increment Nonce
if (T1_vld)
S_nonce++;
// Send MSG back if we need to!
// Check for Result Found
if (T133_vld && !S_nonceHitQue.full()) {
bool bW7Eq = T133_state.m_state[7] == S_task.m_target[2];
bool bW7Lt = T133_state.m_state[7] < S_task.m_target[2];
bool bW6Eq = T133_state.m_state[6] == S_task.m_target[1];
bool bW6Lt = T133_state.m_state[6] < S_task.m_target[1];
bool bW5Eq = T133_state.m_state[5] == S_task.m_target[0];
bool bW5Lt = T133_state.m_state[5] < S_task.m_target[0];
bool bMatch = bW7Lt || bW7Eq && (bW6Lt || bW6Eq && (bW5Lt || bW5Eq));
if (bMatch)
S_nonceHitQue.push(BcmByteSwap32(T133_nonce));
// Check for Last Nonce / Increment count
if (S_task.m_lastNonce == T133_nonce)
S_bTaskValid = false;
else
S_hashCount++;
}
// Check force return / reset
if (S_forceReturn) {
S_bTaskValid = false;
S_forceReturn = false;
}
if (GR_htReset) {
S_zeroInput = true;
S_bTaskValid = false;
S_forceReturn = false;
}
}
/********************************************************************
* Function: void WritePM(WORD length, DWORD_VAL sourceAddr)
*
* PreCondition: Page containing rows to write should be erased.
*
* Input: length - number of rows to write
* sourceAddr - row aligned address to write to
*
* Output: None.
*
* Side Effects: None.
*
* Overview: Writes number of rows indicated from buffer into
* flash memory
*
* Note: None
********************************************************************/
void WritePM(WORD length, DWORD_VAL sourceAddr)
{
WORD bytesWritten;
DWORD_VAL data;
#ifdef USE_RUNAWAY_PROTECT
WORD temp = (WORD)sourceAddr.Val;
#endif
bytesWritten = 0; //first 5 buffer locations are cmd,len,addr
//write length rows to flash
while((bytesWritten) < length*PM_ROW_SIZE)
{
asm("clrwdt");
//get data to write from buffer
data.v[0] = buffer[bytesWritten+5];
data.v[1] = buffer[bytesWritten+6];
data.v[2] = buffer[bytesWritten+7];
data.v[3] = buffer[bytesWritten+8];
//4 bytes per instruction: low word, high byte, phantom byte
bytesWritten+=PM_INSTR_SIZE;
//Flash configuration word handling
#ifndef DEV_HAS_CONFIG_BITS
//Mask of bit 15 of CW1 to ensure it is programmed as 0
//as noted in PIC24FJ datasheets
if(sourceAddr.Val == CONFIG_END){
data.Val &= 0x007FFF;
}
#endif
//Protect the bootloader & reset vector
#ifdef USE_BOOT_PROTECT
//protect BL reset & get user reset
if(sourceAddr.Val == 0x0){
//get user app reset vector lo word
userReset.Val = data.Val & 0xFFFF;
//program low word of BL reset
data.Val = 0x040000 + (0xFFFF & BOOT_ADDR_LOW);
userResetRead = 1;
}
if(sourceAddr.Val == 0x2){
//get user app reset vector hi byte
userReset.Val += (DWORD)(data.Val & 0x00FF)<<16;
//program high byte of BL reset
data.Val = ((DWORD)(BOOT_ADDR_LOW & 0xFF0000))>>16;
userResetRead = 1;
}
#else
//get user app reset vector lo word
if(sourceAddr.Val == 0x0){
userReset.Val = data.Val & 0xFFFF;
userResetRead = 1;
}
//get user app reset vector hi byte
if(sourceAddr.Val == 0x2) {
userReset.Val |= ((DWORD)(data.Val & 0x00FF))<<16;
userResetRead = 1;
}
#endif
//put information from reset vector in user reset vector location
if(sourceAddr.Val == USER_PROG_RESET){
if(userResetRead){ //has reset vector been grabbed from location 0x0?
//if yes, use that reset vector
data.Val = userReset.Val;
}else{
//if no, use the user's indicated reset vector
userReset.Val = data.Val;
}
}
//If address is delay timer location, store data and write empty word
if(sourceAddr.Val == DELAY_TIME_ADDR){
userTimeout.Val = data.Val;
data.Val = 0xFFFFFF;
}
#ifdef USE_BOOT_PROTECT //do not erase bootloader & reset vector
if(sourceAddr.Val < BOOT_ADDR_LOW || sourceAddr.Val > BOOT_ADDR_HI){
#endif
#ifdef USE_CONFIGWORD_PROTECT //do not erase last page
if(sourceAddr.Val < (CONFIG_START & 0xFFFC00)){
#endif
#ifdef USE_VECTOR_PROTECT //do not erase first page
//if(sourceAddr.Val >= PM_PAGE_SIZE/2){
if(sourceAddr.Val >= VECTOR_SECTION){
#endif
//write data into latches
WriteLatch(sourceAddr.word.HW, sourceAddr.word.LW,
data.word.HW, data.word.LW);
#ifdef USE_VECTOR_PROTECT
}//end vectors protect
#endif
#ifdef USE_CONFIGWORD_PROTECT
}//end config protect
#endif
#ifdef USE_BOOT_PROTECT
}//end bootloader protect
#endif
#ifdef USE_RUNAWAY_PROTECT
writeKey1 += 4; // Modify keys to ensure proper program flow
writeKey2 -= 4;
#endif
//write to flash memory if complete row is finished
if((bytesWritten % PM_ROW_SIZE) == 0)
{
#ifdef USE_RUNAWAY_PROTECT
//setup program flow protection test keys
keyTest1 = (0x0009 | temp) - length + bytesWritten - 5;
keyTest2 = (((0x557F << 1) + WT_FLASH) - bytesWritten) + 6;
#endif
#ifdef USE_BOOT_PROTECT //Protect the bootloader & reset vector
if((sourceAddr.Val < BOOT_ADDR_LOW || sourceAddr.Val > BOOT_ADDR_HI)){
#endif
#ifdef USE_CONFIGWORD_PROTECT //do not erase last page
if(sourceAddr.Val < (CONFIG_START & 0xFFFC00)){
#endif
#ifdef USE_VECTOR_PROTECT //do not erase first page
if(sourceAddr.Val >= VECTOR_SECTION){
#endif
//execute write sequence
WriteMem(PM_ROW_WRITE);
#ifdef USE_RUNAWAY_PROTECT
writeKey1 += 5; // Modify keys to ensure proper program flow
writeKey2 -= 6;
#endif
#ifdef USE_VECTOR_PROTECT
}//end vectors protect
#endif
#ifdef USE_CONFIGWORD_PROTECT
}//end config protect
#endif
#ifdef USE_BOOT_PROTECT
}//end boot protect
#endif
}
sourceAddr.Val = sourceAddr.Val + 2; //increment addr by 2
}//end while((bytesWritten-5) < length*PM_ROW_SIZE)
