示例#1
0
status_t
QuickCamDevice::SetIICBitsMode(size_t bits)
{
	switch (bits) {
		case 8:
			WriteReg8(STV_REG23, 0);
			break;
		case 16:
			WriteReg8(STV_REG23, 1);
			break;
		default:
			return EINVAL;
	}
	return B_OK;
}
示例#2
0
void BdPortPutByte(UINT8 Output)
{
    // Loop until the device is ready for output
    while ((ReadReg8(uartBase + COM_LSR) & LSR_THR_EMPTY) == 0) {
    }

    // The transmitter regiser is clear and can be written to.
    WriteReg8(uartBase + COM_DAT, Output);
}
示例#3
0
static void UartSetBaudRate(uint32 * BaseAddress, uint32 BaudRate)
{
    uint32 Divisor = OMAP_CLOCK_RATE / BaudRate;
    uint8 Enhanced;

    // Disable UART
    WriteReg8(BaseAddress + OMAP_UART_MDR1, 0x7);

    // Set register configuration mode B
    WriteReg8(BaseAddress + COM_LCR, 0xBF);

    // Save enhanced mode
    Enhanced = ReadReg8(BaseAddress + OMAP_UART_EFR);
    WriteReg8(BaseAddress + OMAP_UART_EFR, Enhanced | (1 << 4));

    // switch to operational mode
    WriteReg8(BaseAddress + COM_LCR, 0);

    // clear sleep mode
    WriteReg8(BaseAddress + OMAP_UART_IER, 0);

    // Set register configuration mode B
    WriteReg8(BaseAddress + COM_LCR, 0xBF);

    // Write the divisor value to DLL and DLM.
    WriteReg8(BaseAddress + COM_DLM, (uint8)((Divisor >> 8) & 0xff));
    WriteReg8(BaseAddress + COM_DLL, (uint8)(Divisor & 0xff));

    // Restore enhanced mode
    WriteReg8(BaseAddress + OMAP_UART_EFR, Enhanced);

    // Reset the Line Control Register.
    WriteReg8(BaseAddress + COM_LCR, LCR_DATA_SIZE);

    // Enable UART
    WriteReg8(BaseAddress + OMAP_UART_MDR1, 0);
}
示例#4
0
status_t
QuickCamDevice::StopTransfer()
{
	status_t err;
	
DumpRegs();
	err = CamDevice::StopTransfer();
#if 0
//	if (err < 0)
//		return err;
	err = ReadReg(SN9C102_CHIP_CTRL, &r, 1, true);
	if (err < 0)
		return err;
	r &= ~0x04;
	err = WriteReg8(SN9C102_CHIP_CTRL, r);
	if (err < 0)
		return err;
#endif
	return err;
}
示例#5
0
status_t
QuickCamDevice::StartTransfer()
{
	SetScale(1);
	if (Sensor())
		SetVideoFrame(BRect(0, 0, Sensor()->MaxWidth()-1, Sensor()->MaxHeight()-1));
	
	//SetVideoFrame(BRect(0, 0, 320-1, 240-1));

DumpRegs();
#if 0
	err = ReadReg(SN9C102_CHIP_CTRL, &r, 1, true);
	if (err < 0)
		return err;
	r |= 0x04;
	err = WriteReg8(SN9C102_CHIP_CTRL, r);
	if (err < 0)
		return err;
#endif
	return CamDevice::StartTransfer();
}
示例#6
0
bool BdPortInit(uint32 * BaseAddress, uint32 BaudRate)
{
#define PADCONF_CTS    ((1 << 4) | (1 << 3) | (1 << 8))
#define PADCONF_RTS    (0)
#define PADCONF_TX     (0)
#define PADCONF_RX     ((1 << 3) | (1 << 8))

    uartBase = BaseAddress;
    uint8 * HalpSCM = (uint8 *)OMAP_SCM_BASE;
    uint8 * HalpCORE_CM = (uint8 *)OMAP_CORE_CM_BASE;
    uint32 Value;

    if (BaseAddress == (uint32 *)OMAP_UART1_BASE) {
        // Power on the required function and interface units.
        Value = ReadReg32(HalpCORE_CM + CM_FCLKEN1_CORE);
        Value |= CM_CORE_EN_UART1;
        WriteReg32(HalpCORE_CM + CM_FCLKEN1_CORE, Value);

        Value = ReadReg32(HalpCORE_CM + CM_ICLKEN1_CORE);
        Value |= CM_CORE_EN_UART1;
        WriteReg32(HalpCORE_CM + CM_ICLKEN1_CORE, Value);

        // Configure uart1 pads per documentation example
        WriteReg32(HalpSCM + OMAP_CONTROL_PADCONF_UART1_TX,
                   PADCONF_TX | (PADCONF_RTS << 16));
        WriteReg32(HalpSCM + OMAP_CONTROL_PADCONF_UART1_CTS,
                   PADCONF_CTS | (PADCONF_RX << 16));
    }
    else if (BaseAddress == (uint32 *)OMAP_UART2_BASE) {
        // Power on the required function and interface units.
        Value = ReadReg32(HalpCORE_CM + CM_FCLKEN1_CORE);
        Value |= CM_CORE_EN_UART2;
        WriteReg32(HalpCORE_CM + CM_FCLKEN1_CORE, Value);

        Value = ReadReg32(HalpCORE_CM + CM_ICLKEN1_CORE);
        Value |= CM_CORE_EN_UART2;
        WriteReg32(HalpCORE_CM + CM_ICLKEN1_CORE, Value);

        WriteReg32(HalpSCM + OMAP_CONTROL_PADCONF_UART2_CTS,
                   PADCONF_CTS | (PADCONF_RTS << 16));
        WriteReg32(HalpSCM + OMAP_CONTROL_PADCONF_UART2_TX,
                   PADCONF_TX | (PADCONF_RX << 16));
    }

    // Set the default baudrate.
    UartSetBaudRate(BaseAddress, BaudRate);

    // Set DLAB to zero.  DLAB controls the meaning of the first two
    // registers.  When zero, the first register is used for all byte transfer
    // and the second register controls device interrupts.
    //
    WriteReg8(BaseAddress + COM_LCR,
              ReadReg8(BaseAddress + COM_LCR) & ~LCR_DLAB);

    // Disable device interrupts.  This implementation will handle state
    // transitions by request only.
    //
    WriteReg8(BaseAddress + COM_IEN, 0);

    // Reset and disable the FIFO queue.
    // N.B. FIFO will be reenabled before returning from this routine.
    //
    WriteReg8(BaseAddress + COM_FCR, FCR_CLEAR_TRANSMIT | FCR_CLEAR_RECEIVE);

    // Configure the Modem Control Register.  Disabled device interrupts,
    // turn off loopback.
    //
    WriteReg8(BaseAddress + COM_MCR,
              ReadReg8(BaseAddress + COM_MCR) & MCR_INITIALIZE);

    // Initialize the Modem Control Register.  Indicate to the device that
    // we are able to send and receive data.
    //
    WriteReg8(BaseAddress + COM_MCR, MCR_INITIALIZE);

    // Enable the FIFO queues.
    WriteReg8(BaseAddress + COM_FCR, FCR_ENABLE);

    return true;
}