C++ (Cpp) XCVR_PHY_EL_CFG_EL_ENABLE示例

示例#1

文件： fsl_xcvr_ble_config.c 项目： 01org/zephyr

                         RW1PS(11, 0x1CU) |
                         RW1PS(12, 0x1CU & 0xFU), /* Phase info #12 overlaps two initialization words */
    .phy_pre_ref2_init = (0x1C) >> 4 | /* Phase info #12 overlaps two initialization words - manually compute the shift*/
                         RW2PS(13, 0x1BU) |
                         RW2PS(14, 0x1AU) |
                         RW2PS(15, 0x19U),

    .phy_cfg1_init = XCVR_PHY_CFG1_AA_PLAYBACK(0) |
                     XCVR_PHY_CFG1_AA_OUTPUT_SEL(1) | 
                     XCVR_PHY_CFG1_FSK_BIT_INVERT(0) |
                     XCVR_PHY_CFG1_BSM_EN_BLE(0) |
                     XCVR_PHY_CFG1_DEMOD_CLK_MODE(0) |
                     XCVR_PHY_CFG1_CTS_THRESH(220) |
                     XCVR_PHY_CFG1_FSK_FTS_TIMEOUT(2),

    .phy_el_cfg_init = XCVR_PHY_EL_CFG_EL_ENABLE(1) /* Per SMB */
#if !RADIO_IS_GEN_2P1
                     | XCVR_PHY_EL_CFG_EL_ZB_ENABLE(0)
#endif /* !RADIO_IS_GEN_2P1 */
    ,

    /* XCVR_RX_DIG configs */
    .rx_dig_ctrl_init_26mhz = XCVR_RX_DIG_RX_DIG_CTRL_RX_FSK_ZB_SEL(0) | /* Depends on protocol */
                              XCVR_RX_DIG_RX_DIG_CTRL_RX_DC_RESID_EN(1) | /* Depends on protocol */
                              XCVR_RX_DIG_RX_DIG_CTRL_RX_SRC_RATE(0),

    .rx_dig_ctrl_init_32mhz =  XCVR_RX_DIG_RX_DIG_CTRL_RX_FSK_ZB_SEL(0) | /* Depends on protocol */
                               XCVR_RX_DIG_RX_DIG_CTRL_RX_DC_RESID_EN(1), /* Depends on protocol */

    .agc_ctrl_0_init = XCVR_RX_DIG_AGC_CTRL_0_AGC_DOWN_RSSI_THRESH(0xFF),
    /* XCVR_TSM configs */

示例#2

文件： fsl_xcvr_gfsk_bt_0p5_h_0p32_config.c 项目： bboozzoo/zephyr

                     XCVR_CTRL_XCVR_CTRL_DEMOD_SEL(1),
                     
    /* XCVR_PHY configs */
    .phy_pre_ref0_init = 0xBBDE739B,
    .phy_pre_ref1_init = 0xDEFBDEF7,
    .phy_pre_ref2_init = 0x0000E739,

    .phy_cfg1_init = XCVR_PHY_CFG1_AA_PLAYBACK(1) |
                    XCVR_PHY_CFG1_AA_OUTPUT_SEL(1) | 
                    XCVR_PHY_CFG1_FSK_BIT_INVERT(0) |
                    XCVR_PHY_CFG1_BSM_EN_BLE(0) |
                    XCVR_PHY_CFG1_DEMOD_CLK_MODE(0) |
                    XCVR_PHY_CFG1_CTS_THRESH(0xCD) |
                    XCVR_PHY_CFG1_FSK_FTS_TIMEOUT(2),                  

    .phy_el_cfg_init =XCVR_PHY_EL_CFG_EL_ENABLE(1) |
                   XCVR_PHY_EL_CFG_EL_ZB_ENABLE(0),
                    
    /* XCVR_RX_DIG configs */
    .rx_dig_ctrl_init_26mhz = 
                        XCVR_RX_DIG_RX_DIG_CTRL_RX_FSK_ZB_SEL(0) | /* Depends on protocol */
                        XCVR_RX_DIG_RX_DIG_CTRL_RX_DC_RESID_EN(1) | /* Depends on protocol */
                        XCVR_RX_DIG_RX_DIG_CTRL_RX_SRC_RATE(1),

    .rx_dig_ctrl_init_32mhz = 
                        XCVR_RX_DIG_RX_DIG_CTRL_RX_FSK_ZB_SEL(0) | /* Depends on protocol */
                        XCVR_RX_DIG_RX_DIG_CTRL_RX_DC_RESID_EN(1), /* Depends on protocol */

    .agc_ctrl_0_init = XCVR_RX_DIG_AGC_CTRL_0_AGC_DOWN_RSSI_THRESH(0xFF),

    /* XCVR_TSM configs */