/**
*
* This function initializes the Cresample core. This function must be called
* prior to using the Cresample core. Initialization of the Cresample includes
* setting up the instance data and ensuring the hardware is in a quiescent
* state.
*
* @param InstancePtr is a pointer to the XCresample instance.
* @param CfgPtr is a reference to a structure containing information
* about a specific Chroma Resampler driver.
* @param EffectiveAddr is the device base address in the virtual memory
* address space. The caller is responsible for keeping the
* address mapping from EffectiveAddr to the device physical base
* address unchanged once this function is invoked. Unexpected
* errors may occur if the address mapping changes after this
* function is called. If address translation is not used, pass in
* the physical address instead.
*
* @return - XST_SUCCESS if initialization was successful.
*
* @note None.
*
******************************************************************************/
int XCresample_CfgInitialize(XCresample *InstancePtr,
XCresample_Config *CfgPtr, u32 EffectiveAddr)
{
/* Verify arguments. */
Xil_AssertNonvoid(CfgPtr != NULL);
Xil_AssertNonvoid(EffectiveAddr != ((u32)0x0));
/* Setup the instance */
(void)memset((void *)InstancePtr, 0, sizeof(XCresample));
(void)memcpy((void *)(&(InstancePtr->Config)), (const void *)CfgPtr,
sizeof(XCresample_Config));
InstancePtr->Config.BaseAddress = EffectiveAddr;
/*
* Set all handlers to stub values, let user configure this data later.
*/
InstancePtr->ProcStartCallBack =
(XCresample_CallBack)((void *)StubCallBack);
InstancePtr->FrameDoneCallBack =
(XCresample_CallBack)((void *)StubCallBack);
InstancePtr->ErrCallBack =
(XCresample_ErrorCallBack)((void *)StubErrCallBack);
/*
* Reset the hardware and set the flag to indicate the driver is
* ready.
*/
XCresample_Reset(InstancePtr);
InstancePtr->IsReady = (u32)(XIL_COMPONENT_IS_READY);
return (XST_SUCCESS);
}
void avnet_config_vgap60_video(demo_t *pInstance) {
int status;
Xil_Out32(XPAR_TCM_RECEIVER_0_S00_AXI_BASEADDR + 0x0000, 0x0001);
XCfa_Reset(pInstance->pcfa);
XCcm_Reset(pInstance->pccm);
XRgb2YCrCb_Reset(pInstance->prgb2ycrcb);
XCresample_Reset(pInstance->pcresample);
XAxiVdma_Reset(pInstance->paxivdma, XAXIVDMA_WRITE);
XAxiVdma_Reset(pInstance->paxivdma, XAXIVDMA_READ);
XVtc_Reset(pInstance->pvtc);
XOSD_Reset(pInstance->posd);
/* CLKWIZ */
Xil_Out32(XPAR_CLK_WIZ_1_BASEADDR + 0x0200, 0x00002203);
Xil_Out32(XPAR_CLK_WIZ_1_BASEADDR + 0x0208, 0x0000002D);
Xil_Out32(XPAR_CLK_WIZ_1_BASEADDR + 0x025C, 0x00000007);
Xil_Out32(XPAR_CLK_WIZ_1_BASEADDR + 0x025C, 0x00000002);
status = 0;
while (!status) {
status = Xil_In32(XPAR_CLK_WIZ_1_BASEADDR + 0x0004);
}
/* ISERDES Reset Assert */
Xil_Out32(XPAR_TCM_RECEIVER_0_S00_AXI_BASEADDR + 0x0000, 0x0001);
/* TCM Initialization */
tca9548_i2c_mux_select(pInstance->piicps, EMBV_IIC_MUX_CAM);
// tcm5117pl_get_chip_id(pInstance->piicps);
tcm5117pl_init(pInstance->piicps, TCM5117PL_VGAP60);
/* CFA */
XCfa_Reset(pInstance->pcfa);
XCfa_Enable(pInstance->pcfa);
XCfa_SetBayerPhase(pInstance->pcfa, 0x00000001);
XCfa_SetActiveSize(pInstance->pcfa, 656, 496);
XCfa_RegUpdateEnable(pInstance->pcfa);
/* CCM */
XCcm_Reset(pInstance->pccm);
XCcm_Enable(pInstance->pccm);
XCcm_SetCoefMatrix(pInstance->pccm, &CCM_IDENTITY);
XCcm_SetRgbOffset(pInstance->pccm, 0, 0, 0);
XCcm_SetActiveSize(pInstance->pccm, 656, 496);
XCcm_RegUpdateEnable(pInstance->pccm);
/* RGB2YCRCB */
XRgb2YCrCb_Reset(pInstance->prgb2ycrcb);
XRgb2YCrCb_Enable(pInstance->prgb2ycrcb);
XRgb2YCrCb_Configuration(pInstance->prgb2ycrcb, XRGB_STANDARD_ITU_601_SD, XRGB_TV_16_TO_240, XRGB_DATA_WIDTH_10);
XRgb2YCrCb_SetActiveSize(pInstance->prgb2ycrcb, 656, 496);
XRgb2YCrCb_RegUpdateEnable(pInstance->prgb2ycrcb);
/* CRESAMPLE */
XCresample_Reset(pInstance->pcresample);
XCresample_Enable(pInstance->pcresample);
XCresample_Configuration(pInstance->pcresample);
XCresample_SetActiveSize(pInstance->pcresample, 656, 496);
XCresample_RegUpdateEnable(pInstance->pcresample);
/* AXIVDMA */
XAxiVdma_Reset(pInstance->paxivdma, XAXIVDMA_WRITE);
XAxiVdma_Reset(pInstance->paxivdma, XAXIVDMA_READ);
ReadSetup(pInstance->paxivdma, 0x30000000, 2, 0, 1, 1, 0, 0, 656, 496, 2048,
2048);
WriteSetup(pInstance->paxivdma, 0x30000000, 2, 0, 1, 1, 0, 0, 656, 496, 2048,
2048);
StartTransfer(pInstance->paxivdma);
/* VTC */
XVtc_Timing Timing;
XVtc_Reset(pInstance->pvtc);
XVtc_RegUpdateEnable(pInstance->pvtc);
XVtc_Enable(pInstance->pvtc);
XVtc_ConvVideoMode2Timing(pInstance->pvtc, XVTC_VMODE_VGA, &Timing);
Timing.HSyncPolarity = 1;
Timing.VSyncPolarity = 1;
XVtc_SetGeneratorTiming(pInstance->pvtc, &Timing);
/* OSD */
XOSD_Reset(pInstance->posd);
XOSD_RegUpdateEnable(pInstance->posd);
XOSD_Enable(pInstance->posd);
XOSD_SetScreenSize(pInstance->posd, 656, 496);
XOSD_SetBackgroundColor(pInstance->posd, 0x80, 0x80, 0x80);
// Layer 0 - Test Pattern Generator
XOSD_SetLayerPriority(pInstance->posd, 0, XOSD_LAYER_PRIORITY_0);
XOSD_SetLayerAlpha(pInstance->posd, 0, 1, 0xFF);
XOSD_SetLayerDimension(pInstance->posd, 0, 0, 0, 656, 496);
XOSD_EnableLayer(pInstance->posd, 0);
// ISERDES Reset De-Assert
Xil_Out32(XPAR_TCM_RECEIVER_0_S00_AXI_BASEADDR + 0x0000, 0x0000);
}