void init_emacps_on_error (xemacpsif_s *xemacps, struct netif *netif)
{
unsigned mac_address = (unsigned)(netif->state);
XEmacPs *xemacpsp;
XEmacPs_Config *mac_config;
int Status = XST_SUCCESS;
/* obtain config of this emac */
mac_config = (XEmacPs_Config *)xemacps_lookup_config(mac_address);
xemacpsp = &xemacps->emacps;
/* set mac address */
Status = XEmacPs_SetMacAddress(xemacpsp, (void*)(netif->hwaddr), 1);
if (Status != XST_SUCCESS) {
xil_printf("In %s:Emac Mac Address set failed...\r\n",__func__);
}
XEmacPs_SetOperatingSpeed(xemacpsp, link_speed);
/* Setting the operating speed of the MAC needs a delay. */
{
volatile int wait;
for (wait=0; wait < 20000; wait++);
}
}
void
init_emacps(xemacpsif_s *xemacps, struct netif *netif)
{
int rdy;
unsigned mac_address = (unsigned)(netif->state);
unsigned link_speed = 1000;
unsigned options;
unsigned lock_message_printed = 0;
XEmacPs *xemacpsp;
XEmacPs_Config *mac_config;
int Status = XST_SUCCESS;
/* obtain config of this emac */
mac_config = lookup_config(mac_address);
xemacpsp = &xemacps->emacps;
#if 0
options = XEmacPs_GetOptions(xemacpsp);
options |= XEMACPS_FLOW_CONTROL_OPTION;
options |= XEMACPS_TRANSMITTER_ENABLE_OPTION;
options |= XEMACPS_RECEIVER_ENABLE_OPTION;
options |= XEMACPS_FCS_STRIP_OPTION;
options |= XEMACPS_BROADCAST_OPTION;
options |= XEMACPS_FCS_INSERT_OPTION;
options |= XEMACPS_RX_CHKSUM_ENABLE_OPTION;
options |= XEMACPS_TX_CHKSUM_ENABLE_OPTION;
options |= XEMACPS_LENTYPE_ERR_OPTION;
XEmacPs_SetOptions(xemacpsp, options);
XEmacPs_ClearOptions(xemacpsp, ~options);
#endif
/* set mac address */
Status = XEmacPs_SetMacAddress(xemacpsp, (void*)(netif->hwaddr), 1);
if (Status != XST_SUCCESS) {
xil_printf("In %s:Emac Mac Address set failed...\r\n",__func__);
}
link_speed = Phy_Setup(xemacpsp);
XEmacPs_SetOperatingSpeed(xemacpsp, link_speed);
/* Setting the operating speed of the MAC needs a delay. */
{
volatile int wait;
for (wait=0; wait < 20000; wait++);
}
Status = XEmacPs_SetOptions(xemacpsp, XEMACPS_PROMISC_OPTION);
if (Status != XST_SUCCESS) {
xil_printf("In %s:Setting up of promiscuous mode failed...\r\n",__func__);
}
}
/**
* Perform a graceful reset of the Ethernet MAC. Resets the DMA channels, the
* transmitter, and the receiver.
*
* Steps to reset
* - Stops transmit and receive channels
* - Stops DMA
* - Configure transmit and receive buffer size to default
* - Clear transmit and receive status register and counters
* - Clear all interrupt sources
* - Clear phy (if there is any previously detected) address
* - Clear MAC addresses (1-4) as well as Type IDs and hash value
*
* All options are placed in their default state. Any frames in the
* descriptor lists will remain in the lists. The side effect of doing
* this is that after a reset and following a restart of the device, frames
* were in the list before the reset may be transmitted or received.
*
* The upper layer software is responsible for re-configuring (if necessary)
* and restarting the MAC after the reset. Note also that driver statistics
* are not cleared on reset. It is up to the upper layer software to clear the
* statistics if needed.
*
* When a reset is required, the driver notifies the upper layer software of
* this need through the ErrorHandler callback and specific status codes.
* The upper layer software is responsible for calling this Reset function
* and then re-configuring the device.
*
* @param InstancePtr is a pointer to the instance to be worked on.
*
******************************************************************************/
void XEmacPs_Reset(XEmacPs *InstancePtr)
{
u32 Reg;
u8 i;
char EmacPs_zero_MAC[6] = { 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 };
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
/* Stop the device and reset hardware */
XEmacPs_Stop(InstancePtr);
InstancePtr->Options = XEMACPS_DEFAULT_OPTIONS;
/* Setup hardware with default values */
XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
XEMACPS_NWCTRL_OFFSET,
(XEMACPS_NWCTRL_STATCLR_MASK |
XEMACPS_NWCTRL_MDEN_MASK) &
~XEMACPS_NWCTRL_LOOPEN_MASK);
XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
XEMACPS_NWCFG_OFFSET,
XEMACPS_NWCFG_100_MASK |
XEMACPS_NWCFG_FDEN_MASK |
XEMACPS_NWCFG_UCASTHASHEN_MASK);
XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
XEMACPS_DMACR_OFFSET,
((((XEMACPS_RX_BUF_SIZE / XEMACPS_RX_BUF_UNIT) +
((XEMACPS_RX_BUF_SIZE %
XEMACPS_RX_BUF_UNIT) ? 1 : 0)) <<
XEMACPS_DMACR_RXBUF_SHIFT) &
XEMACPS_DMACR_RXBUF_MASK) |
XEMACPS_DMACR_RXSIZE_MASK |
XEMACPS_DMACR_TXSIZE_MASK);
XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
XEMACPS_TXSR_OFFSET, 0x0);
XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
XEMACPS_RXQBASE_OFFSET, 0x0);
XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
XEMACPS_TXQBASE_OFFSET, 0x0);
XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
XEMACPS_RXSR_OFFSET, 0x0);
XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, XEMACPS_IDR_OFFSET,
XEMACPS_IXR_ALL_MASK);
Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
XEMACPS_ISR_OFFSET);
XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, XEMACPS_ISR_OFFSET,
Reg);
XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
XEMACPS_PHYMNTNC_OFFSET, 0x0);
XEmacPs_ClearHash(InstancePtr);
for (i = 1; i < 5; i++) {
XEmacPs_SetMacAddress(InstancePtr, EmacPs_zero_MAC, i);
XEmacPs_SetTypeIdCheck(InstancePtr, 0x0, i);
}
/* clear all counters */
for (i = 0; i < (XEMACPS_LAST_OFFSET - XEMACPS_OCTTXL_OFFSET) / 4;
i++) {
XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
XEMACPS_OCTTXL_OFFSET + i * 4);
}
/* Disable the receiver */
Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
XEMACPS_NWCTRL_OFFSET);
Reg &= ~XEMACPS_NWCTRL_RXEN_MASK;
XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
XEMACPS_NWCTRL_OFFSET, Reg);
/* Sync default options with hardware but leave receiver and
* transmitter disabled. They get enabled with XEmacPs_Start() if
* XEMACPS_TRANSMITTER_ENABLE_OPTION and
* XEMACPS_RECEIVER_ENABLE_OPTION are set.
*/
XEmacPs_SetOptions(InstancePtr, InstancePtr->Options &
~(XEMACPS_TRANSMITTER_ENABLE_OPTION |
XEMACPS_RECEIVER_ENABLE_OPTION));
XEmacPs_ClearOptions(InstancePtr, ~InstancePtr->Options);
}
void init_emacps(xemacpsif_s *xemacps, struct netif *netif)
{
UINTPTR mac_address = (UINTPTR)(netif->state);
XEmacPs *xemacpsp;
XEmacPs_Config *mac_config;
s32_t status = XST_SUCCESS;
u32_t i;
u32_t phyfoundforemac0 = FALSE;
u32_t phyfoundforemac1 = FALSE;
/* obtain config of this emac */
mac_config = (XEmacPs_Config *)xemacps_lookup_config(mac_address);
xemacpsp = &xemacps->emacps;
/* set mac address */
status = XEmacPs_SetMacAddress(xemacpsp, (void*)(netif->hwaddr), 1);
if (status != XST_SUCCESS) {
xil_printf("In %s:Emac Mac Address set failed...\r\n",__func__);
}
XEmacPs_SetMdioDivisor(xemacpsp, MDC_DIV_224);
/* Please refer to file header comments for the file xemacpsif_physpeed.c
* to know more about the PHY programming sequence.
* For PCS PMA core, phy_setup is called with the predefined PHY address
* exposed through xaparemeters.h
* For RGMII case, assuming multiple PHYs can be present on the MDIO bus,
* detect_phy is called to get the addresses of the PHY present on
* a particular MDIO bus (emac0 or emac1). This address map is populated
* in phymapemac0 or phymapemac1.
* phy_setup is then called for each PHY present on the MDIO bus.
*/
#ifdef PCM_PMA_CORE_PRESENT
#ifdef XPAR_GIGE_PCS_PMA_1000BASEX_CORE_PRESENT
link_speed = phy_setup(xemacpsp, XPAR_PCSPMA_1000BASEX_PHYADDR);
#elif XPAR_GIGE_PCS_PMA_SGMII_CORE_PRESENT
link_speed = phy_setup(xemacpsp, XPAR_PCSPMA_SGMII_PHYADDR);
#endif
#else
detect_phy(xemacpsp);
for (i = 31; i > 0; i--) {
if (xemacpsp->Config.BaseAddress == XPAR_XEMACPS_0_BASEADDR) {
if (phymapemac0[i] == TRUE) {
link_speed = phy_setup(xemacpsp, i);
phyfoundforemac0 = TRUE;
}
} else {
if (phymapemac1[i] == TRUE) {
link_speed = phy_setup(xemacpsp, i);
phyfoundforemac1 = TRUE;
}
}
}
/* If no PHY was detected, use broadcast PHY address of 0 */
if (xemacpsp->Config.BaseAddress == XPAR_XEMACPS_0_BASEADDR) {
if (phyfoundforemac0 == FALSE)
link_speed = phy_setup(xemacpsp, 0);
} else {
if (phyfoundforemac1 == FALSE)
link_speed = phy_setup(xemacpsp, 0);
}
#endif
XEmacPs_SetOperatingSpeed(xemacpsp, link_speed);
/* Setting the operating speed of the MAC needs a delay. */
{
volatile s32_t wait;
for (wait=0; wait < 20000; wait++);
}
}
/**
* This function resets the device but preserves the options set by the user.
*
* The descriptor list could be reinitialized with the same calls to
* XEmacPs_BdRingClone() as used in main(). Doing this is a matter of
* preference.
* In many cases, an OS may have resources tied up in the descriptors.
* Reinitializing in this case may bad for the OS since its resources may be
* permamently lost.
*
* @param EmacPsInstancePtr is a pointer to the instance of the EmacPs
* driver.
*
* @return XST_SUCCESS if successful, else XST_FAILURE.
*
* @note None.
*
*****************************************************************************/
static int EmacPsResetDevice(XEmacPs * EmacPsInstancePtr)
{
int Status = 0;
u8 MacSave[6];
u32 Options;
XEmacPs_Bd BdTemplate;
/*
* Stop device
*/
XEmacPs_Stop(EmacPsInstancePtr);
/*
* Save the device state
*/
XEmacPs_GetMacAddress(EmacPsInstancePtr, &MacSave, 1);
Options = XEmacPs_GetOptions(EmacPsInstancePtr);
/*
* Stop and reset the device
*/
XEmacPs_Reset(EmacPsInstancePtr);
/*
* Restore the state
*/
XEmacPs_SetMacAddress(EmacPsInstancePtr, &MacSave, 1);
Status |= XEmacPs_SetOptions(EmacPsInstancePtr, Options);
Status |= XEmacPs_ClearOptions(EmacPsInstancePtr, ~Options);
if (Status != XST_SUCCESS) {
EmacPsUtilErrorTrap("Error restoring state after reset");
return XST_FAILURE;
}
/*
* Setup callbacks
*/
Status = XEmacPs_SetHandler(EmacPsInstancePtr,
XEMACPS_HANDLER_DMASEND,
(void *) XEmacPsSendHandler,
EmacPsInstancePtr);
Status |= XEmacPs_SetHandler(EmacPsInstancePtr,
XEMACPS_HANDLER_DMARECV,
(void *) XEmacPsRecvHandler,
EmacPsInstancePtr);
Status |= XEmacPs_SetHandler(EmacPsInstancePtr, XEMACPS_HANDLER_ERROR,
(void *) XEmacPsErrorHandler,
EmacPsInstancePtr);
if (Status != XST_SUCCESS) {
EmacPsUtilErrorTrap("Error assigning handlers");
return XST_FAILURE;
}
/*
* Setup RxBD space.
*
* We have already defined a properly aligned area of memory to store
* RxBDs at the beginning of this source code file so just pass its
* address into the function. No MMU is being used so the physical and
* virtual addresses are the same.
*
* Setup a BD template for the Rx channel. This template will be copied
* to every RxBD. We will not have to explicitly set these again.
*/
XEmacPs_BdClear(&BdTemplate);
/*
* Create the RxBD ring
*/
Status = XEmacPs_BdRingCreate(&(XEmacPs_GetRxRing
(EmacPsInstancePtr)),
RX_BD_LIST_START_ADDRESS,
RX_BD_LIST_START_ADDRESS,
XEMACPS_BD_ALIGNMENT,
RXBD_CNT);
if (Status != XST_SUCCESS) {
EmacPsUtilErrorTrap
("Error setting up RxBD space, BdRingCreate");
return XST_FAILURE;
}
Status = XEmacPs_BdRingClone(&
(XEmacPs_GetRxRing(EmacPsInstancePtr)),
&BdTemplate, XEMACPS_RECV);
if (Status != XST_SUCCESS) {
EmacPsUtilErrorTrap
("Error setting up RxBD space, BdRingClone");
return XST_FAILURE;
}
/*
* Setup TxBD space.
*
* Like RxBD space, we have already defined a properly aligned area of
* memory to use.
*
* Also like the RxBD space, we create a template. Notice we don't set
* the "last" attribute. The examples will be overriding this
* attribute so it does no good to set it up here.
*/
XEmacPs_BdClear(&BdTemplate);
XEmacPs_BdSetStatus(&BdTemplate, XEMACPS_TXBUF_USED_MASK);
/*
* Create the TxBD ring
*/
Status = XEmacPs_BdRingCreate(&(XEmacPs_GetTxRing
(EmacPsInstancePtr)),
TX_BD_LIST_START_ADDRESS,
TX_BD_LIST_START_ADDRESS,
XEMACPS_BD_ALIGNMENT,
TXBD_CNT);
if (Status != XST_SUCCESS) {
EmacPsUtilErrorTrap
("Error setting up TxBD space, BdRingCreate");
return XST_FAILURE;
}
Status = XEmacPs_BdRingClone(&
(XEmacPs_GetTxRing(EmacPsInstancePtr)),
&BdTemplate, XEMACPS_SEND);
if (Status != XST_SUCCESS) {
EmacPsUtilErrorTrap
("Error setting up TxBD space, BdRingClone");
return XST_FAILURE;
}
/*
* Restart the device
*/
XEmacPs_Start(EmacPsInstancePtr);
return XST_SUCCESS;
}
/**
*
* This function demonstrates the usage of the EmacPs driver by sending by
* sending and receiving frames in interrupt driven DMA mode.
*
*
* @param IntcInstancePtr is a pointer to the instance of the Intc driver.
* @param EmacPsInstancePtr is a pointer to the instance of the EmacPs
* driver.
* @param EmacPsDeviceId is Device ID of the EmacPs Device , typically
* XPAR_<EMACPS_instance>_DEVICE_ID value from xparameters.h.
* @param EmacPsIntrId is the Interrupt ID and is typically
* XPAR_<EMACPS_instance>_INTR value from xparameters.h.
*
* @return XST_SUCCESS to indicate success, otherwise XST_FAILURE.
*
* @note None.
*
*****************************************************************************/
int EmacPsDmaIntrExample(XScuGic * IntcInstancePtr,
XEmacPs * EmacPsInstancePtr,
u16 EmacPsDeviceId,
u16 EmacPsIntrId)
{
int Status;
XEmacPs_Config *Config;
XEmacPs_Bd BdTemplate;
#ifndef PEEP
u32 SlcrTxClkCntrl;
#endif
/*************************************/
/* Setup device for first-time usage */
/*************************************/
/* SLCR unlock */
*(volatile unsigned int *)(SLCR_UNLOCK_ADDR) = SLCR_UNLOCK_KEY_VALUE;
#ifdef PEEP
*(volatile unsigned int *)(SLCR_GEM0_CLK_CTRL_ADDR) =
SLCR_GEM_1G_CLK_CTRL_VALUE;
*(volatile unsigned int *)(SLCR_GEM1_CLK_CTRL_ADDR) =
SLCR_GEM_1G_CLK_CTRL_VALUE;
#else
if (EmacPsIntrId == XPS_GEM0_INT_ID) {
#ifdef XPAR_PS7_ETHERNET_0_ENET_SLCR_1000MBPS_DIV0
/* GEM0 1G clock configuration*/
SlcrTxClkCntrl =
*(volatile unsigned int *)(SLCR_GEM0_CLK_CTRL_ADDR);
SlcrTxClkCntrl &= EMACPS_SLCR_DIV_MASK;
SlcrTxClkCntrl |= (XPAR_PS7_ETHERNET_0_ENET_SLCR_1000MBPS_DIV1 << 20);
SlcrTxClkCntrl |= (XPAR_PS7_ETHERNET_0_ENET_SLCR_1000MBPS_DIV0 << 8);
*(volatile unsigned int *)(SLCR_GEM0_CLK_CTRL_ADDR) =
SlcrTxClkCntrl;
#endif
} else if (EmacPsIntrId == XPS_GEM1_INT_ID) {
#ifdef XPAR_PS7_ETHERNET_1_ENET_SLCR_1000MBPS_DIV1
/* GEM1 1G clock configuration*/
SlcrTxClkCntrl =
*(volatile unsigned int *)(SLCR_GEM1_CLK_CTRL_ADDR);
SlcrTxClkCntrl &= EMACPS_SLCR_DIV_MASK;
SlcrTxClkCntrl |= (XPAR_PS7_ETHERNET_1_ENET_SLCR_1000MBPS_DIV1 << 20);
SlcrTxClkCntrl |= (XPAR_PS7_ETHERNET_1_ENET_SLCR_1000MBPS_DIV0 << 8);
*(volatile unsigned int *)(SLCR_GEM1_CLK_CTRL_ADDR) =
SlcrTxClkCntrl;
#endif
}
#endif
/* SLCR lock */
*(unsigned int *)(SLCR_LOCK_ADDR) = SLCR_LOCK_KEY_VALUE;
sleep(1);
/*
* Initialize instance. Should be configured for DMA
* This example calls _CfgInitialize instead of _Initialize due to
* retiring _Initialize. So in _CfgInitialize we use
* XPAR_(IP)_BASEADDRESS to make sure it is not virtual address.
*/
Config = XEmacPs_LookupConfig(EmacPsDeviceId);
Status = XEmacPs_CfgInitialize(EmacPsInstancePtr, Config,
Config->BaseAddress);
if (Status != XST_SUCCESS) {
EmacPsUtilErrorTrap("Error in initialize");
return XST_FAILURE;
}
/*
* Set the MAC address
*/
Status = XEmacPs_SetMacAddress(EmacPsInstancePtr, EmacPsMAC, 1);
if (Status != XST_SUCCESS) {
EmacPsUtilErrorTrap("Error setting MAC address");
return XST_FAILURE;
}
/*
* Setup callbacks
*/
Status = XEmacPs_SetHandler(EmacPsInstancePtr,
XEMACPS_HANDLER_DMASEND,
(void *) XEmacPsSendHandler,
EmacPsInstancePtr);
Status |=
XEmacPs_SetHandler(EmacPsInstancePtr,
XEMACPS_HANDLER_DMARECV,
(void *) XEmacPsRecvHandler,
EmacPsInstancePtr);
Status |=
XEmacPs_SetHandler(EmacPsInstancePtr, XEMACPS_HANDLER_ERROR,
(void *) XEmacPsErrorHandler,
EmacPsInstancePtr);
if (Status != XST_SUCCESS) {
EmacPsUtilErrorTrap("Error assigning handlers");
return XST_FAILURE;
}
/*
* The BDs need to be allocated in uncached memory. Hence the 1 MB
* address range that starts at address 0xFF00000 is made uncached.
*/
Xil_SetTlbAttributes(0x0FF00000, 0xc02);
/*
* Setup RxBD space.
*
* We have already defined a properly aligned area of memory to store
* RxBDs at the beginning of this source code file so just pass its
* address into the function. No MMU is being used so the physical
* and virtual addresses are the same.
*
* Setup a BD template for the Rx channel. This template will be
* copied to every RxBD. We will not have to explicitly set these
* again.
*/
XEmacPs_BdClear(&BdTemplate);
/*
* Create the RxBD ring
*/
Status = XEmacPs_BdRingCreate(&(XEmacPs_GetRxRing
(EmacPsInstancePtr)),
RX_BD_LIST_START_ADDRESS,
RX_BD_LIST_START_ADDRESS,
XEMACPS_BD_ALIGNMENT,
RXBD_CNT);
if (Status != XST_SUCCESS) {
EmacPsUtilErrorTrap
("Error setting up RxBD space, BdRingCreate");
return XST_FAILURE;
}
Status = XEmacPs_BdRingClone(&(XEmacPs_GetRxRing(EmacPsInstancePtr)),
&BdTemplate, XEMACPS_RECV);
if (Status != XST_SUCCESS) {
EmacPsUtilErrorTrap
("Error setting up RxBD space, BdRingClone");
return XST_FAILURE;
}
/*
* Setup TxBD space.
*
* Like RxBD space, we have already defined a properly aligned area
* of memory to use.
*
* Also like the RxBD space, we create a template. Notice we don't
* set the "last" attribute. The example will be overriding this
* attribute so it does no good to set it up here.
*/
XEmacPs_BdClear(&BdTemplate);
XEmacPs_BdSetStatus(&BdTemplate, XEMACPS_TXBUF_USED_MASK);
/*
* Create the TxBD ring
*/
Status = XEmacPs_BdRingCreate(&(XEmacPs_GetTxRing
(EmacPsInstancePtr)),
TX_BD_LIST_START_ADDRESS,
TX_BD_LIST_START_ADDRESS,
XEMACPS_BD_ALIGNMENT,
TXBD_CNT);
if (Status != XST_SUCCESS) {
EmacPsUtilErrorTrap
("Error setting up TxBD space, BdRingCreate");
return XST_FAILURE;
}
Status = XEmacPs_BdRingClone(&(XEmacPs_GetTxRing(EmacPsInstancePtr)),
&BdTemplate, XEMACPS_SEND);
if (Status != XST_SUCCESS) {
EmacPsUtilErrorTrap
("Error setting up TxBD space, BdRingClone");
return XST_FAILURE;
}
/*
* Set emacps to phy loopback
*/
#ifndef PEEP /* For Zynq board */
XEmacPs_SetMdioDivisor(EmacPsInstancePtr, MDC_DIV_224);
sleep(1);
#endif
EmacPsUtilEnterLoopback(EmacPsInstancePtr, EMACPS_LOOPBACK_SPEED_1G);
XEmacPs_SetOperatingSpeed(EmacPsInstancePtr, EMACPS_LOOPBACK_SPEED_1G);
/*
* Setup the interrupt controller and enable interrupts
*/
Status = EmacPsSetupIntrSystem(IntcInstancePtr,
EmacPsInstancePtr, EmacPsIntrId);
/*
* Run the EmacPs DMA Single Frame Interrupt example
*/
Status = EmacPsDmaSingleFrameIntrExample(EmacPsInstancePtr);
if (Status != XST_SUCCESS) {
return XST_FAILURE;
}
/*
* Disable the interrupts for the EmacPs device
*/
EmacPsDisableIntrSystem(IntcInstancePtr, EmacPsIntrId);
/*
* Stop the device
*/
XEmacPs_Stop(EmacPsInstancePtr);
return XST_SUCCESS;
}
