/* Warm Reset a USB3 port */
static void xhci_reset_port_usb3(device_t dev, int port)
{
struct reg_script reset_port_usb3_script[] = {
/* Issue Warm Port Rest to the port */
REG_RES_OR32(PCI_BASE_ADDRESS_0, XHCI_USB3_PORTSC(port),
XHCI_USB3_PORTSC_WPR),
/* Wait up to 100ms for it to complete */
REG_RES_POLL32(PCI_BASE_ADDRESS_0, XHCI_USB3_PORTSC(port),
XHCI_USB3_PORTSC_WRC, XHCI_USB3_PORTSC_WRC,
XHCI_RESET_TIMEOUT),
/* Clear change status bits, do not set PED */
REG_RES_RMW32(PCI_BASE_ADDRESS_0, XHCI_USB3_PORTSC(port),
~XHCI_USB3_PORTSC_PED, XHCI_USB3_PORTSC_CHST),
REG_SCRIPT_END
};
reg_script_run_on_dev(dev, reset_port_usb3_script);
}
static void usb_xhci_reset_status_usb3(u8 *mem_base, int port)
{
u8 *portsc = mem_base + XHCI_USB3_PORTSC(port);
u32 status = read32(portsc);
/* Do not set Port Enabled/Disabled field */
status &= ~XHCI_USB3_PORTSC_PED;
/* Clear all change status bits */
status |= XHCI_USB3_PORTSC_CHST;
write32(portsc, status);
}
static void usb_xhci_reset_usb3(struct device *dev, int all)
#endif
{
u32 status, port_disabled;
int timeout, port;
int port_count = usb_xhci_port_count_usb3(dev);
u8 *mem_base = usb_xhci_mem_base(dev);
if (!mem_base || !port_count)
return;
/* Get mask of disabled ports */
port_disabled = pci_read_config32(dev, XHCI_USB3PDO);
/* Wait until all enabled ports are done polling */
for (timeout = XHCI_RESET_TIMEOUT; timeout; timeout--) {
int complete = 1;
for (port = 0; port < port_count; port++) {
/* Skip disabled ports */
if (port_disabled & (1 << port))
continue;
/* Read port link status field */
status = read32(mem_base + XHCI_USB3_PORTSC(port));
status &= XHCI_USB3_PORTSC_PLS;
if (status == XHCI_PLSR_POLLING)
complete = 0;
}
/* Exit if all ports not polling */
if (complete)
break;
udelay(XHCI_RESET_DELAY_US);
}
/* Reset all requested ports */
for (port = 0; port < port_count; port++) {
u8 *portsc = mem_base + XHCI_USB3_PORTSC(port);
/* Skip disabled ports */
if (port_disabled & (1 << port))
continue;
status = read32(portsc) & XHCI_USB3_PORTSC_PLS;
/* Reset all or only disconnected ports */
if (all || (status == XHCI_PLSR_RXDETECT ||
status == XHCI_PLSR_POLLING))
usb_xhci_reset_port_usb3(mem_base, port);
else
port_disabled |= 1 << port;
}
/* Wait for warm reset complete on all reset ports */
for (timeout = XHCI_RESET_TIMEOUT; timeout; timeout--) {
int complete = 1;
for (port = 0; port < port_count; port++) {
/* Only check ports that were reset */
if (port_disabled & (1 << port))
continue;
/* Check if warm reset is complete */
status = read32(mem_base + XHCI_USB3_PORTSC(port));
if (!(status & XHCI_USB3_PORTSC_WRC))
complete = 0;
}
/* Check for warm reset complete in any port */
if (complete)
break;
udelay(XHCI_RESET_DELAY_US);
}
/* Clear port change status bits */
for (port = 0; port < port_count; port++)
usb_xhci_reset_status_usb3(mem_base, port);
}
static void usb_xhci_reset_port_usb3(u8 *mem_base, int port)
{
u8 *portsc = mem_base + XHCI_USB3_PORTSC(port);
write32(portsc, read32(portsc) | XHCI_USB3_PORTSC_WPR);
}
/* Re-enable ports that are disabled */
static void usb_xhci_enable_ports_usb3(device_t dev)
{
#if CONFIG_FINALIZE_USB_ROUTE_XHCI
int port;
u32 portsc, status, disabled;
u32 mem_base = usb_xhci_mem_base(dev);
int port_count = usb_xhci_port_count_usb3(dev);
u8 port_reset = 0;
int timeout;
if (!mem_base || !port_count)
return;
/* Get port disable override map */
disabled = pci_read_config32(dev, XHCI_USB3PDO);
for (port = 0; port < port_count; port++) {
/* Skip overridden ports */
if (disabled & (1 << port))
continue;
portsc = mem_base + XHCI_USB3_PORTSC(port);
status = read32(portsc) & XHCI_USB3_PORTSC_PLS;
switch (status) {
case XHCI_PLSR_RXDETECT:
/* Clear change status */
printk(BIOS_DEBUG, "usb_xhci reset status %d\n", port);
usb_xhci_reset_status_usb3(mem_base, port);
break;
case XHCI_PLSR_DISABLED:
default:
/* Reset port */
printk(BIOS_DEBUG, "usb_xhci reset port %d\n", port);
usb_xhci_reset_port_usb3(mem_base, port);
port_reset |= 1 << port;
break;
}
}
if (!port_reset)
return;
/* Wait for warm reset complete on all reset ports */
for (timeout = XHCI_RESET_TIMEOUT; timeout; timeout--) {
int complete = 1;
for (port = 0; port < port_count; port++) {
/* Only check ports that were reset */
if (!(port_reset & (1 << port)))
continue;
/* Check if warm reset is complete */
status = read32(mem_base + XHCI_USB3_PORTSC(port));
if (!(status & XHCI_USB3_PORTSC_WRC))
complete = 0;
}
/* Check for warm reset complete in any port */
if (complete)
break;
udelay(XHCI_RESET_DELAY_US);
}
/* Enable ports that were reset */
for (port = 0; port < port_count; port++) {
/* Only check ports that were reset */
if (!(port_reset & (1 << port)))
continue;
/* Transition to enabled */
portsc = mem_base + XHCI_USB3_PORTSC(port);
status = read32(portsc);
status &= ~(XHCI_USB3_PORTSC_PLS | XHCI_USB3_PORTSC_PED);
status |= XHCI_PLSW_ENABLE | XHCI_USB3_PORTSC_LWS;
write32(portsc, status);
}
#endif
}