示例#1
0
//----------------------------------------------------------------------------
// Interrupt support
void
hal_platform_IRQ_init(void)
{
// We need first to have a decent decoding routine!
    XINTC_PPC_WRITE(XINTC_PPC_CIE,XINTC_PPC_ALL);
    XINTC_PPC_WRITE(XINTC_PPC_IAR,XINTC_PPC_ALL);
#ifndef CYGPKG_REDBOOT
    // This is a write-once bit, so if we are not planning to enable
    // interrupts at this time, we can safely delay this to a later time
#ifdef XIntc_mMasterEnable
    XIntc_mMasterEnable(UPBHWR_INTC_0_BASEADDR);
#else
#ifdef XIntc_MasterEnable
    XIntc_MasterEnable(UPBHWR_INTC_0_BASEADDR);
#endif
#endif
#endif
}
示例#2
0
void init_all(void) {
  XIntc_Initialize(&intc, XPAR_XPS_INTC_0_DEVICE_ID);
  microblaze_enable_interrupts();
  XIntc_mMasterEnable(XPAR_INTC_0_BASEADDR);
  XUartLite_mEnableIntr(XPAR_UARTLITE_0_BASEADDR);
  ////  пецхярпюжхъ  напюанрвхйнб ////////////////////////////////////////////
  XIntc_RegisterHandler(XPAR_XPS_INTC_0_BASEADDR,
                        XPAR_INTC_0_UARTLITE_0_VEC_ID,
                        (XInterruptHandler)handler_RS232,
                        (void *)0);
  XIntc_RegisterHandler(XPAR_XPS_INTC_0_BASEADDR,
                        XPAR_INTC_0_TMRCTR_0_VEC_ID,
                        (XInterruptHandler)handler_Timer,
                        (void *)0);
  ///////////////////////////////////////////////////////////////////////////////
  //// мюярпнийю  рюилепю //////////////////////////////////////////////////////
  XTmrCtr_mSetLoadReg(XPAR_XPS_TIMER_0_BASEADDR,
                      0,
                      0x61a8 //(25 MHz / 25000 = 1mS
                    //0x124F8//(75 MHz : 75.000 = 1 mS
                      );
  XIntc_mEnableIntr(XPAR_INTC_0_BASEADDR,
              //    XPAR_XPS_TIMER_0_INTERRUPT_MASK |
                    XPAR_XPS_UARTLITE_0_INTERRUPT_MASK);
  XTmrCtr_mSetControlStatusReg(XPAR_XPS_TIMER_0_BASEADDR,
                               0,
                               XTC_CSR_ENABLE_TMR_MASK |
                               XTC_CSR_ENABLE_INT_MASK |
                               XTC_CSR_AUTO_RELOAD_MASK |
                               XTC_CSR_DOWN_COUNT_MASK);
  /////////////////////////////////////////////////////////////////////////////////
  ///////// мюярпнийю  сярпниярб  ббндю-бшбндю ////////////////////////////////////
  XGpio_Initialize(&photo, XPAR_XPS_GPIO_0_DEVICE_ID);
  XGpio_Initialize(&ircom, XPAR_XPS_GPIO_1_DEVICE_ID);
  XGpio_Initialize(&kt,    XPAR_XPS_GPIO_2_DEVICE_ID);

  XGpio_SetDataDirection(&photo, 1, 0xffffffff);  // ББНД
  XGpio_SetDataDirection(&photo, 2, 0x00);        // БШБНД
  XGpio_SetDataDirection(&ircom, 1, 0x00);        // БШБНД
  XGpio_SetDataDirection(&ircom, 2, 0x00);        // БШБНД
  XGpio_SetDataDirection(&kt,    1, 0x00);        // БШБНД
};